i80321reg.h Source File
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Go to the documentation of this file. 39 #ifndef _ARM_XSCALE_I80321REG_H_ 40 #define _ARM_XSCALE_I80321REG_H_ 57 #define VERDE_OUT_DIRECT_WIN_BASE 0x00000000UL 58 #define VERDE_OUT_DIRECT_WIN_SIZE 0x80000000UL 60 #define VERDE_OUT_XLATE_MEM_WIN_SIZE 0x04000000UL 61 #define VERDE_OUT_XLATE_IO_WIN_SIZE 0x00010000UL 63 #define VERDE_OUT_XLATE_MEM_WIN0_BASE 0x80000000UL 64 #define VERDE_OUT_XLATE_MEM_WIN1_BASE 0x84000000UL 66 #define VERDE_OUT_XLATE_IO_WIN0_BASE 0x90000000UL 68 #define VERDE_EXTMEM_BASE 0x90020000UL 70 #define VERDE_PMMR_BASE 0xffffe000UL 71 #define VERDE_PMMR_SIZE 0x00001700UL 77 #define VERDE_ATU_BASE 0x0100 78 #define VERDE_ATU_SIZE 0x0100 80 #define VERDE_MU_BASE 0x0300 81 #define VERDE_MU_SIZE 0x0100 83 #define VERDE_DMA_BASE 0x0400 84 #define VERDE_DMA_BASE0 (VERDE_DMA_BASE + 0x00) 85 #define VERDE_DMA_BASE1 (VERDE_DMA_BASE + 0x40) 86 #define VERDE_DMA_SIZE 0x0100 87 #define VERDE_DMA_CHSIZE 0x0040 89 #define VERDE_MCU_BASE 0x0500 90 #define VERDE_MCU_SIZE 0x0100 92 #define VERDE_SSP_BASE 0x0600 93 #define VERDE_SSP_SIZE 0x0080 95 #define VERDE_PBIU_BASE 0x0680 96 #define VERDE_PBIU_SIZE 0x0080 98 #define VERDE_AAU_BASE 0x0800 99 #define VERDE_AAU_SIZE 0x0100 101 #define VERDE_I2C_BASE 0x1680 102 #define VERDE_I2C_BASE0 (VERDE_I2C_BASE + 0x00) 103 #define VERDE_I2C_BASE1 (VERDE_I2C_BASE + 0x20) 104 #define VERDE_I2C_SIZE 0x0080 105 #define VERDE_I2C_CHSIZE 0x0020 111 #define ATU_IALR0 0x40 112 #define ATU_IATVR0 0x44 113 #define ATU_ERLR 0x48 114 #define ATU_ERTVR 0x4c 115 #define ATU_IALR1 0x50 116 #define ATU_IALR2 0x54 117 #define ATU_IATVR2 0x58 118 #define ATU_OIOWTVR 0x5c 119 #define ATU_OMWTVR0 0x60 120 #define ATU_OUMWTVR0 0x64 121 #define ATU_OMWTVR1 0x68 122 #define ATU_OUMWTVR1 0x6c 123 #define ATU_OUDWTVR 0x78 124 #define ATU_ATUCR 0x80 125 #define ATU_PCSR 0x84 126 #define ATU_ATUISR 0x88 127 #define ATU_ATUIMR 0x8c 128 #define ATU_IABAR3 0x90 129 #define ATU_IAUBAR3 0x94 130 #define ATU_IALR3 0x98 131 #define ATU_IATVR3 0x9c 132 #define ATU_OCCAR 0xa4 133 #define ATU_OCCDR 0xac 134 #define ATU_MSI_PORT 0xb4 135 #define ATU_PDSCR 0xbc 136 #define ATU_PCI_X_CAP_ID 0xe0 137 #define ATU_PCI_X_NEXT 0xe1 138 #define ATU_PCIXCMD 0xe2 139 #define ATU_PCIXSR 0xe4 141 #define ATUCR_DRC_ALIAS (1U << 19) 142 #define ATUCR_DAU2GXEN (1U << 18) 143 #define ATUCR_P_SERR_MA (1U << 16) 144 #define ATUCR_DTS (1U << 15) 145 #define ATUCR_P_SERR_DIE (1U << 9) 146 #define ATUCR_DAE (1U << 8) 147 #define ATUCR_BIST_IE (1U << 3) 148 #define ATUCR_OUT_EN (1U << 1) 150 #define PCSR_DAAAPE (1U << 18) 151 #define PCSR_PCI_X_CAP (3U << 16) 152 #define PCSR_PCI_X_CAP_BORING (0 << 16) 153 #define PCSR_PCI_X_CAP_66 (1U << 16) 154 #define PCSR_PCI_X_CAP_100 (2U << 16) 155 #define PCSR_PCI_X_CAP_133 (3U << 16) 156 #define PCSR_OTQB (1U << 15) 157 #define PCSR_IRTQB (1U << 14) 158 #define PCSR_DTV (1U << 12) 159 #define PCSR_BUS66 (1U << 10) 160 #define PCSR_BUS64 (1U << 8) 161 #define PCSR_RIB (1U << 5) 162 #define PCSR_RPB (1U << 4) 163 #define PCSR_CCR (1U << 2) 164 #define PCSR_CPR (1U << 1) 166 #define ATUISR_IMW1BU (1U << 14) 167 #define ATUISR_ISCEM (1U << 13) 168 #define ATUISR_RSCEM (1U << 12) 169 #define ATUISR_PST (1U << 11) 170 #define ATUISR_P_SERR_ASRT (1U << 10) 171 #define ATUISR_DPE (1U << 9) 172 #define ATUISR_BIST (1U << 8) 173 #define ATUISR_IBMA (1U << 7) 174 #define ATUISR_P_SERR_DET (1U << 4) 175 #define ATUISR_PMA (1U << 3) 176 #define ATUISR_PTAM (1U << 2) 177 #define ATUISR_PTAT (1U << 1) 178 #define ATUISR_PMPE (1U << 0) 180 #define ATUIMR_IMW1BU (1U << 11) 181 #define ATUIMR_ISCEM (1U << 10) 182 #define ATUIMR_RSCEM (1U << 9) 183 #define ATUIMR_PST (1U << 8) 184 #define ATUIMR_DPE (1U << 7) 185 #define ATUIMR_P_SERR_ASRT (1U << 6) 186 #define ATUIMR_PMA (1U << 5) 187 #define ATUIMR_PTAM (1U << 4) 188 #define ATUIMR_PTAT (1U << 3) 189 #define ATUIMR_PMPE (1U << 2) 190 #define ATUIMR_IE_SERR_EN (1U << 1) 191 #define ATUIMR_ECC_TAE (1U << 0) 193 #define PCIXCMD_MOST_1 (0 << 4) 194 #define PCIXCMD_MOST_2 (1 << 4) 195 #define PCIXCMD_MOST_3 (2 << 4) 196 #define PCIXCMD_MOST_4 (3 << 4) 197 #define PCIXCMD_MOST_8 (4 << 4) 198 #define PCIXCMD_MOST_12 (5 << 4) 199 #define PCIXCMD_MOST_16 (6 << 4) 200 #define PCIXCMD_MOST_32 (7 << 4) 201 #define PCIXCMD_MOST_MASK (7 << 4) 202 #define PCIXCMD_MMRBC_512 (0 << 2) 203 #define PCIXCMD_MMRBC_1024 (1 << 2) 204 #define PCIXCMD_MMRBC_2048 (2 << 2) 205 #define PCIXCMD_MMRBC_4096 (3 << 2) 206 #define PCIXCMD_MMRBC_MASK (3 << 2) 207 #define PCIXCMD_ERO (1U << 1) 208 #define PCIXCMD_DPERE (1U << 0) 210 #define PCIXSR_RSCEM (1U << 29) 211 #define PCIXSR_DMCRS_MASK (7 << 26) 212 #define PCIXSR_DMOST_MASK (7 << 23) 213 #define PCIXSR_COMPLEX (1U << 20) 214 #define PCIXSR_USC (1U << 19) 215 #define PCIXSR_SCD (1U << 18) 216 #define PCIXSR_133_CAP (1U << 17) 217 #define PCIXSR_32PCI (1U << 16) 218 #define PCIXSR_BUSNO(x) (((x) & 0xff00) >> 8) 219 #define PCIXSR_DEVNO(x) (((x) & 0xf8) >> 3) 220 #define PCIXSR_FUNCNO(x) ((x) & 0x7) 225 #define MCU_SDIR 0x00 226 #define MCU_SDCR 0x04 227 #define MCU_SDBR 0x08 228 #define MCU_SBR0 0x0c 229 #define MCU_SBR1 0x10 230 #define MCU_ECCR 0x34 231 #define MCU_ELOG0 0x38 232 #define MCU_ELOG1 0x3c 233 #define MCU_ECAR0 0x40 234 #define MCU_ECAR1 0x44 235 #define MCU_ECTST 0x48 236 #define MCU_MCISR 0x4c 238 #define MCU_DBUDSR 0x54 239 #define MCU_DBDDSR 0x58 240 #define MCU_CUDSR 0x5c 241 #define MCU_CDDSR 0x60 242 #define MCU_CEUDSR 0x64 243 #define MCU_CEDDSR 0x68 244 #define MCU_CSUDSR 0x6c 245 #define MCU_CSDDSR 0x70 246 #define MCU_REUDSR 0x74 247 #define MCU_REDDSR 0x78 248 #define MCU_ABUDSR 0x7c 249 #define MCU_ABDDSR 0x80 250 #define MCU_DSDR 0x84 251 #define MCU_REDR 0x88 253 #define SDCR_DIMMTYPE (1U << 1) 254 #define SDCR_BUSWIDTH (1U << 2) 256 #define SBRx_TECH (1U << 31) 257 #define SBRx_BOUND 0x0000003f 259 #define ECCR_SBERE (1U << 0) 260 #define ECCR_MBERE (1U << 1) 261 #define ECCR_SBECE (1U << 2) 262 #define ECCR_ECCEN (1U << 3) 264 #define ELOGx_SYNDROME 0x000000ff 265 #define ELOGx_ERRTYPE (1U << 8) 266 #define ELOGx_RW (1U << 12) 275 #define ELOGx_REQ_DEV(x) (((x) >> 19) & 0x1f) 276 #define ELOGx_REQ_FUNC(x) (((x) >> 16) & 0x3) 278 #define MCISR_ECC_ERR0 (1U << 0) 279 #define MCISR_ECC_ERR1 (1U << 1) 280 #define MCISR_ECC_ERRN (1U << 2) 299 #define TMRx_TC (1U << 0) 300 #define TMRx_ENABLE (1U << 1) 301 #define TMRx_RELOAD (1U << 2) 302 #define TMRx_CSEL_CORE (0 << 4) 303 #define TMRx_CSEL_CORE_div4 (1 << 4) 304 #define TMRx_CSEL_CORE_div8 (2 << 4) 305 #define TMRx_CSEL_CORE_div16 (3 << 4) 307 #define TISR_TMR0 (1U << 0) 308 #define TISR_TMR1 (1U << 1) 310 #define WDTCR_ENABLE1 0x1e1e1e1e 311 #define WDTCR_ENABLE2 0xe1e1e1e1 323 #define ICU_PIRSR 0x01ec 324 #define ICU_GPOE 0x07c4 325 #define ICU_GPID 0x07c8 326 #define ICU_GPOD 0x07cc 332 #define ICU_INT_HPI 31 333 #define ICU_INT_XINT0 27 334 #define ICU_INT_XINT(x) ((x) + ICU_INT_XINT0) 335 #define ICU_INT_bit26 26 336 #define ICU_INT_SSP 25 337 #define ICU_INT_MUE 24 338 #define ICU_INT_AAUE 23 339 #define ICU_INT_bit22 22 340 #define ICU_INT_DMA1E 21 341 #define ICU_INT_DMA0E 20 342 #define ICU_INT_MCUE 19 343 #define ICU_INT_ATUE 18 344 #define ICU_INT_BIUE 17 345 #define ICU_INT_PMU 16 346 #define ICU_INT_PPM 15 347 #define ICU_INT_BIST 14 348 #define ICU_INT_MU 13 349 #define ICU_INT_I2C1 12 350 #define ICU_INT_I2C0 11 351 #define ICU_INT_TMR1 10 352 #define ICU_INT_TMR0 9 353 #define ICU_INT_CPPM 8 354 #define ICU_INT_AAU_EOC 7 355 #define ICU_INT_AAU_EOT 6 356 #define ICU_INT_bit5 5 357 #define ICU_INT_bit4 4 358 #define ICU_INT_DMA1_EOC 3 359 #define ICU_INT_DMA1_EOT 2 360 #define ICU_INT_DMA0_EOC 1 361 #define ICU_INT_DMA0_EOT 0 363 #define ICU_INT_HWMASK (0xffffffff & \ 364 ~((1 << ICU_INT_bit26) | \ 365 (1 << ICU_INT_bit22) | \ 366 (1 << ICU_INT_bit5) | \ 367 (1 << ICU_INT_bit4))) 373 #define SSP_SSCR0 0x00 374 #define SSP_SSCR1 0x04 375 #define SSP_SSSR 0x08 376 #define SSP_SSITR 0x0c 377 #define SSP_SSDR 0x10 379 #define SSP_SSCR0_DSIZE(x) ((x) - 1) 380 #define SSP_SSCR0_FRF_SPI (0 << 4) 381 #define SSP_SSCR0_FRF_SSP (1U << 4) 382 #define SSP_SSCR0_FRF_UWIRE (2U << 4) 383 #define SSP_SSCR0_FRF_rsvd (3U << 4) 384 #define SSP_SSCR0_ECS (1U << 6) 385 #define SSP_SSCR0_SSE (1U << 7) 386 #define SSP_SSCR0_SCR(x) ((x) << 8) 390 #define SSP_SSCR1_RIE (1U << 0) 391 #define SSP_SSCR1_TIE (1U << 1) 392 #define SSP_SSCR1_LBM (1U << 2) 393 #define SSP_SSCR1_SPO (1U << 3) 394 #define SSP_SSCR1_SPH (1U << 4) 399 #define SSP_SSCR1_MWDS (1U << 5) 402 #define SSP_SSCR1_TFT (((x) - 1) << 6) 403 #define SSP_SSCR1_RFT (((x) - 1) << 10) 404 #define SSP_SSCR1_EFWR (1U << 14) 405 #define SSP_SSCR1_STRF (1U << 15) 409 #define SSP_SSSR_TNF (1U << 2) 410 #define SSP_SSSR_RNE (1U << 3) 411 #define SSP_SSSR_BSY (1U << 4) 412 #define SSP_SSSR_TFS (1U << 5) 413 #define SSP_SSSR_RFS (1U << 6) 414 #define SSP_SSSR_ROR (1U << 7) 415 #define SSP_SSSR_TFL(x) (((x) >> 8) & 0xf) 416 #define SSP_SSSR_RFL(x) (((x) >> 12) & 0xf) 418 #define SSP_SSITR_TTFS (1U << 5) 419 #define SSP_SSITR_TRFS (1U << 6) 420 #define SSP_SSITR_TROR (1U << 7) 426 #define PBIU_PBCR 0x00 427 #define PBIU_PBBAR0 0x08 428 #define PBIU_PBLR0 0x0c 429 #define PBIU_PBBAR1 0x10 430 #define PBIU_PBLR1 0x14 431 #define PBIU_PBBAR2 0x18 432 #define PBIU_PBLR2 0x1c 433 #define PBIU_PBBAR3 0x20 434 #define PBIU_PBLR3 0x24 435 #define PBIU_PBBAR4 0x28 436 #define PBIU_PBLR4 0x2c 437 #define PBIU_PBBAR5 0x30 438 #define PBIU_PBLR5 0x34 439 #define PBIU_DSCR 0x38 440 #define PBIU_MBR0 0x40 441 #define PBIU_MBR1 0x60 442 #define PBIU_MBR2 0x64 444 #define PBIU_PBCR_PBIEN (1 << 0) 445 #define PBIU_PBCR_PBI100 (1 << 1) 446 #define PBIU_PBCR_PBI66 (2 << 1) 447 #define PBIU_PBCR_PBI33 (3 << 1) 448 #define PBIU_PBCR_PBBEN (1 << 3) 450 #define PBIU_PBARx_WIDTH8 (0 << 0) 451 #define PBIU_PBARx_WIDTH16 (1 << 0) 452 #define PBIU_PBARx_WIDTH32 (2 << 0) 453 #define PBIU_PBARx_ADWAIT4 (0 << 2) 454 #define PBIU_PBARx_ADWAIT8 (1 << 2) 455 #define PBIU_PBARx_ADWAIT12 (2 << 2) 456 #define PBIU_PBARx_ADWAIT16 (3 << 2) 457 #define PBIU_PBARx_ADWAIT20 (4 << 2) 458 #define PBIU_PBARx_RCWAIT1 (0 << 6) 459 #define PBIU_PBARx_RCWAIT4 (1 << 6) 460 #define PBIU_PBARx_RCWAIT8 (2 << 6) 461 #define PBIU_PBARx_RCWAIT12 (3 << 6) 462 #define PBIU_PBARx_RCWAIT16 (4 << 6) 463 #define PBIU_PBARx_RCWAIT20 (5 << 6) 464 #define PBIU_PBARx_FWE (1 << 9) 465 #define PBIU_BASE_MASK 0xfffff000U 467 #define PBIU_PBLRx_SIZE(x) (~((x) - 1)) 472 #define MU_IMR0 0x0010 473 #define MU_IMR1 0x0014 474 #define MU_OMR0 0x0018 475 #define MU_OMR1 0x001c 476 #define MU_IDR 0x0020 477 #define MU_IISR 0x0024 478 #define MU_IIMR 0x0028 479 #define MU_ODR 0x002c 480 #define MU_OISR 0x0030 481 #define MU_OIMR 0x0034 482 #define MU_MUCR 0x0050 483 #define MU_QBAR 0x0054 484 #define MU_IFHPR 0x0060 485 #define MU_IFTPR 0x0064 486 #define MU_IPHPR 0x0068 487 #define MU_IPTPR 0x006c 488 #define MU_OFHPR 0x0070 489 #define MU_OFTPR 0x0074 490 #define MU_OPHPR 0x0078 491 #define MU_OPTPR 0x007c 492 #define MU_IAR 0x0080 494 #define MU_IIMR_IRI (1 << 6) 495 #define MU_IIMR_OFQFI (1 << 5) 496 #define MU_IIMR_IPQI (1 << 4) 497 #define MU_IIMR_EDI (1 << 3) 498 #define MU_IIMR_IDI (1 << 2) 499 #define MU_IIMR_IM1I (1 << 1) 500 #define MU_IIMR_IM0I (1 << 0)
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