armreg.h Source File
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Go to the documentation of this file. 55 #define PSR_FLAGS 0xf0000000 56 #define PSR_N_bit (1 << 31) 57 #define PSR_Z_bit (1 << 30) 58 #define PSR_C_bit (1 << 29) 59 #define PSR_V_bit (1 << 28) 61 #define PSR_Q_bit (1 << 27) 63 #define I32_bit (1 << 7) 64 #define F32_bit (1 << 6) 66 #define PSR_T_bit (1 << 5) 67 #define PSR_J_bit (1 << 24) 69 #define PSR_MODE 0x0000001f 70 #define PSR_USR26_MODE 0x00000000 71 #define PSR_FIQ26_MODE 0x00000001 72 #define PSR_IRQ26_MODE 0x00000002 73 #define PSR_SVC26_MODE 0x00000003 74 #define PSR_USR32_MODE 0x00000010 75 #define PSR_FIQ32_MODE 0x00000011 76 #define PSR_IRQ32_MODE 0x00000012 77 #define PSR_SVC32_MODE 0x00000013 78 #define PSR_ABT32_MODE 0x00000017 79 #define PSR_UND32_MODE 0x0000001b 80 #define PSR_SYS32_MODE 0x0000001f 81 #define PSR_32_MODE 0x00000010 83 #define PSR_IN_USR_MODE(psr) (!((psr) & 3)) 84 #define PSR_IN_32_MODE(psr) ((psr) & PSR_32_MODE) 88 #define R15_MODE 0x00000003 89 #define R15_MODE_USR 0x00000000 90 #define R15_MODE_FIQ 0x00000001 91 #define R15_MODE_IRQ 0x00000002 92 #define R15_MODE_SVC 0x00000003 94 #define R15_PC 0x03fffffc 96 #define R15_FIQ_DISABLE 0x04000000 97 #define R15_IRQ_DISABLE 0x08000000 99 #define R15_FLAGS 0xf0000000 100 #define R15_FLAG_N 0x80000000 101 #define R15_FLAG_Z 0x40000000 102 #define R15_FLAG_C 0x20000000 103 #define R15_FLAG_V 0x10000000 109 #define ARM_CP15_CPU_ID 0 117 #define CPU_ID_IMPLEMENTOR_MASK 0xff000000 118 #define CPU_ID_ARM_LTD 0x41000000 119 #define CPU_ID_DEC 0x44000000 120 #define CPU_ID_INTEL 0x69000000 121 #define CPU_ID_TI 0x54000000 124 #define CPU_ID_ISOLD(x) (((x) & 0x0000f000) == 0x00000000) 125 #define CPU_ID_IS7(x) (((x) & 0x0000f000) == 0x00007000) 126 #define CPU_ID_ISNEW(x) (!CPU_ID_ISOLD(x) && !CPU_ID_IS7(x)) 129 #define CPU_ID_FOUNDRY_MASK 0x00ff0000 130 #define CPU_ID_FOUNDRY_VLSI 0x00560000 133 #define CPU_ID_7ARCH_MASK 0x00800000 134 #define CPU_ID_7ARCH_V3 0x00000000 135 #define CPU_ID_7ARCH_V4T 0x00800000 136 #define CPU_ID_7VARIANT_MASK 0x007f0000 139 #define CPU_ID_ARCH_MASK 0x000f0000 140 #define CPU_ID_ARCH_V3 0x00000000 141 #define CPU_ID_ARCH_V4 0x00010000 142 #define CPU_ID_ARCH_V4T 0x00020000 143 #define CPU_ID_ARCH_V5 0x00030000 144 #define CPU_ID_ARCH_V5T 0x00040000 145 #define CPU_ID_ARCH_V5TE 0x00050000 146 #define CPU_ID_ARCH_V5TEJ 0x00060000 147 #define CPU_ID_ARCH_V6 0x00070000 148 #define CPU_ID_VARIANT_MASK 0x00f00000 151 #define CPU_ID_PARTNO_MASK 0x0000fff0 154 #define CPU_ID_XSCALE_COREGEN_MASK 0x0000e000 155 #define CPU_ID_XSCALE_COREREV_MASK 0x00001c00 156 #define CPU_ID_XSCALE_PRODUCT_MASK 0x000003f0 159 #define CPU_ID_REVISION_MASK 0x0000000f 162 #define CPU_ID_CPU_MASK 0xfffffff0 165 #define CPU_ID_ARM2 0x41560200 166 #define CPU_ID_ARM250 0x41560250 169 #define CPU_ID_ARM3 0x41560300 170 #define CPU_ID_ARM600 0x41560600 171 #define CPU_ID_ARM610 0x41560610 172 #define CPU_ID_ARM620 0x41560620 175 #define CPU_ID_ARM700 0x41007000 176 #define CPU_ID_ARM710 0x41007100 177 #define CPU_ID_ARM7500 0x41027100 178 #define CPU_ID_ARM710A 0x41047100 179 #define CPU_ID_ARM7500FE 0x41077100 180 #define CPU_ID_ARM710T 0x41807100 181 #define CPU_ID_ARM720T 0x41807200 182 #define CPU_ID_ARM740T8K 0x41807400 183 #define CPU_ID_ARM740T4K 0x41817400 186 #define CPU_ID_ARM810 0x41018100 187 #define CPU_ID_ARM920T 0x41129200 188 #define CPU_ID_ARM922T 0x41029220 189 #define CPU_ID_ARM940T 0x41029400 190 #define CPU_ID_ARM946ES 0x41049460 191 #define CPU_ID_ARM966ES 0x41049660 192 #define CPU_ID_ARM966ESR1 0x41059660 193 #define CPU_ID_ARM1020E 0x4115a200 194 #define CPU_ID_ARM1022ES 0x4105a220 195 #define CPU_ID_ARM1026EJS 0x4106a260 196 #define CPU_ID_ARM1136JS 0x4107b360 197 #define CPU_ID_ARM1136JSR1 0x4117b360 198 #define CPU_ID_SA110 0x4401a100 199 #define CPU_ID_SA1100 0x4401a110 200 #define CPU_ID_TI925T 0x54029250 201 #define CPU_ID_SA1110 0x6901b110 202 #define CPU_ID_IXP1200 0x6901c120 203 #define CPU_ID_80200 0x69052000 204 #define CPU_ID_PXA250 0x69052100 205 #define CPU_ID_PXA210 0x69052120 206 #define CPU_ID_PXA250A 0x69052100 207 #define CPU_ID_PXA210A 0x69052120 208 #define CPU_ID_PXA250B 0x69052900 209 #define CPU_ID_PXA210B 0x69052920 210 #define CPU_ID_PXA250C 0x69052d00 211 #define CPU_ID_PXA210C 0x69052d20 212 #define CPU_ID_PXA27X 0x69054110 213 #define CPU_ID_80321_400 0x69052420 214 #define CPU_ID_80321_600 0x69052430 215 #define CPU_ID_80321_400_B0 0x69052c20 216 #define CPU_ID_80321_600_B0 0x69052c30 217 #define CPU_ID_80321_600_2 0x69052c32 218 #define CPU_ID_80219_400 0x69052e20 219 #define CPU_ID_80219_600 0x69052e30 220 #define CPU_ID_IXP425_533 0x690541c0 221 #define CPU_ID_IXP425_400 0x690541d0 222 #define CPU_ID_IXP425_266 0x690541f0 225 #define ARM3_CP15_FLUSH 1 226 #define ARM3_CP15_CONTROL 2 227 #define ARM3_CP15_CACHEABLE 3 228 #define ARM3_CP15_UPDATEABLE 4 229 #define ARM3_CP15_DISRUPTIVE 5 232 #define ARM3_CTL_CACHE_ON 0x00000001 233 #define ARM3_CTL_SHARED 0x00000002 234 #define ARM3_CTL_MONITOR 0x00000004 273 #define CPU_CONTROL_MMU_ENABLE 0x00000001 274 #define CPU_CONTROL_AFLT_ENABLE 0x00000002 275 #define CPU_CONTROL_DC_ENABLE 0x00000004 276 #define CPU_CONTROL_WBUF_ENABLE 0x00000008 277 #define CPU_CONTROL_32BP_ENABLE 0x00000010 278 #define CPU_CONTROL_32BD_ENABLE 0x00000020 279 #define CPU_CONTROL_LABT_ENABLE 0x00000040 280 #define CPU_CONTROL_BEND_ENABLE 0x00000080 281 #define CPU_CONTROL_SYST_ENABLE 0x00000100 282 #define CPU_CONTROL_ROM_ENABLE 0x00000200 283 #define CPU_CONTROL_CPCLK 0x00000400 284 #define CPU_CONTROL_BPRD_ENABLE 0x00000800 285 #define CPU_CONTROL_IC_ENABLE 0x00001000 286 #define CPU_CONTROL_VECRELOC 0x00002000 287 #define CPU_CONTROL_ROUNDROBIN 0x00004000 288 #define CPU_CONTROL_V4COMPAT 0x00008000 290 #define CPU_CONTROL_IDC_ENABLE CPU_CONTROL_DC_ENABLE 293 #define XSCALE_AUXCTL_K 0x00000001 294 #define XSCALE_AUXCTL_P 0x00000002 295 #define XSCALE_AUXCTL_MD_WB_RA 0x00000000 296 #define XSCALE_AUXCTL_MD_WB_RWA 0x00000010 297 #define XSCALE_AUXCTL_MD_WT 0x00000020 298 #define XSCALE_AUXCTL_MD_MASK 0x00000030 301 #define CPU_CT_ISIZE(x) ((x) & 0xfff) 302 #define CPU_CT_DSIZE(x) (((x) >> 12) & 0xfff) 303 #define CPU_CT_S (1U << 24) 304 #define CPU_CT_CTYPE(x) (((x) >> 25) & 0xf) 306 #define CPU_CT_CTYPE_WT 0 307 #define CPU_CT_CTYPE_WB1 1 308 #define CPU_CT_CTYPE_WB2 2 309 #define CPU_CT_CTYPE_WB6 6 310 #define CPU_CT_CTYPE_WB7 7 312 #define CPU_CT_xSIZE_LEN(x) ((x) & 0x3) 313 #define CPU_CT_xSIZE_M (1U << 2) 314 #define CPU_CT_xSIZE_ASSOC(x) (((x) >> 3) & 0x7) 315 #define CPU_CT_xSIZE_SIZE(x) (((x) >> 6) & 0x7) 319 #define FAULT_TYPE_MASK 0x0f 320 #define FAULT_USER 0x10 322 #define FAULT_WRTBUF_0 0x00 323 #define FAULT_WRTBUF_1 0x02 324 #define FAULT_BUSERR_0 0x04 325 #define FAULT_BUSERR_1 0x06 326 #define FAULT_BUSERR_2 0x08 327 #define FAULT_BUSERR_3 0x0a 328 #define FAULT_BUSTRNL1 0x0c 329 #define FAULT_BUSTRNL2 0x0e 330 #define FAULT_ALIGN_0 0x01 331 #define FAULT_ALIGN_1 0x03 332 #define FAULT_TRANS_S 0x05 333 #define FAULT_TRANS_P 0x07 334 #define FAULT_DOMAIN_S 0x09 335 #define FAULT_DOMAIN_P 0x0b 336 #define FAULT_PERM_S 0x0d 337 #define FAULT_PERM_P 0x0f 339 #define FAULT_IMPRECISE 0x400 344 #define ARM_VECTORS_LOW 0x00000000U 345 #define ARM_VECTORS_HIGH 0xffff0000U 359 #define INSN_COND_MASK 0xf0000000 360 #define INSN_COND_AL 0xe0000000 362 #define THUMB_INSN_SIZE 2
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