58 #define CRIME_TICKSHIFT 14 59 #define CRIME_SPEED_MUL_FACTOR 1 60 #define CRIME_SPEED_DIV_FACTOR 1 67 #define DEV_CRIME_LENGTH 0x1000 82 uint32_t line = interrupt->
line, asserted;
101 uint32_t line = interrupt->
line, asserted;
134 int j, carry, old, new_, add_byte;
143 add_byte = what_to_add >> ((int64_t)j * 8);
145 new_ = old + add_byte + carry;
175 d->
reg[4] = 0x00; d->
reg[5] = 0x00; d->
reg[6] = 0x00;
192 memcpy(
data, &d->
reg[relative_addr], len);
197 memcpy(&d->
reg[relative_addr],
data, len);
199 memcpy(
data, &d->
reg[relative_addr], len);
201 switch (relative_addr) {
221 exit_without_entering_debugger = 1;
225 fatal(
"[ CRIME_CONTROL: unimplemented " 226 "control 0x%016llx ]\n", (
long long)idata);
248 debug(
"[ crime: read from 0x%x, len=%i:",
249 (
int)relative_addr, len);
250 for (i=0; i<len; i++)
254 debug(
"[ crime: write to 0x%x:", (
int)relative_addr);
255 for (i=0; i<len; i++)
257 debug(
" (len=%i) ]\n", len);
269 uint64_t baseaddr,
char *irq_path,
int use_fb)
283 for (i=0; i<32; i++) {
286 snprintf(name,
sizeof(name),
"%s.crime.0x%x", irq_path, 1 << i);
287 memset(&templ, 0,
sizeof(templ));
299 snprintf(tmpstr,
sizeof(tmpstr),
"mace addr=0x1f310000 irq=%s.crime",
311 #define DEV_MACE_LENGTH 0x100 326 uint32_t line = 1 << interrupt->
line;
346 uint32_t line = 1 << interrupt->
line;
371 memcpy(&d->
reg[relative_addr],
data, len);
373 memcpy(
data, &d->
reg[relative_addr], len);
375 switch (relative_addr) {
381 fatal(
"[ NOTE/TODO: WRITE to mace intr: " 382 "reladdr=0x%x data=", (
int)relative_addr);
383 for (i=0; i<len; i++)
385 fatal(
" (len=%i) ]\n", len);
405 debug(
"[ mace: read from 0x%x:", (
int)relative_addr);
406 for (i=0; i<len; i++)
408 debug(
" (len=%i) ]\n", len);
410 debug(
"[ mace: write to 0x%x:", (
int)relative_addr);
411 for (i=0; i<len; i++)
413 debug(
" (len=%i) ]\n", len);
430 snprintf(tmpstr,
sizeof(tmpstr),
"%s.0x%x",
434 snprintf(tmpstr,
sizeof(tmpstr),
"%s.0x%x",
443 for (i=0; i<32; i++) {
446 snprintf(name,
sizeof(name),
"%s.0x%x.mace.%i",
448 memset(&templ, 0,
sizeof(templ));
456 snprintf(name,
sizeof(name),
"%s.0x%x.mace.%i",
458 memset(&templ, 0,
sizeof(templ));
482 uint64_t idata = 0, odata=0;
483 int regnr, res = 1, bus, dev, func, pcireg;
488 regnr = relative_addr /
sizeof(uint32_t);
491 switch (relative_addr) {
521 &odata : &idata, len, writeflag);
526 debug(
"[ macepci: unimplemented write to address " 527 "0x%x, data=0x%02x ]\n",
528 (
int)relative_addr, (
int)idata);
530 debug(
"[ macepci: unimplemented read from address " 531 "0x%x ]\n", (
int)relative_addr);
546 struct memory *mem, uint64_t baseaddr,
char *irq_path)
561 "TODO: pci irq path",
585 #define MEC_TICK_SHIFT 14 587 #define MAX_TX_PACKET_LEN 1700 588 #define N_RX_ADDRESSES 16 594 unsigned char macaddr[6];
616 memset(d->
reg, 0,
sizeof(d->
reg));
627 debug(
"[ sgi_mec: CORE RESET ]\n");
636 static int mec_try_rx(
struct cpu *cpu,
struct sgi_mec_data *d)
639 unsigned char data[8];
640 int i, res, retval = 0;
644 fatal(
"[ mec_try_rx(): WARNING! lowest bits of base are " 645 "non-zero (0x%3x). TODO ]\n", (
int)(base & 0xfff));
646 base &= 0xfffff000ULL;
660 for (i=0; i<
sizeof(
data); i++) {
663 printf(
"%02x", data[i]);
669 if (data[0] & 0x80) {
671 goto skip_and_advance;
692 printf(
"RX: %i bytes, index %i, base = 0x%x\n",
699 memset(data, 0,
sizeof(data));
729 static int mec_try_tx(
struct cpu *cpu,
struct sgi_mec_data *d)
731 uint64_t base,
addr, dma_base;
732 int tx_ring_ptr, ringread, ringwrite, res, i, j;
733 unsigned char data[32];
734 int len, start_offset, dma_ptr_nr, dma_len;
748 if (ringread == ringwrite)
755 addr = base + tx_ring_ptr*128;
762 if (data[0] & 0x80) {
763 fatal(
"[ mec_try_tx: tx_ring_ptr = %i, already" 764 " transmitted? ]\n", tx_ring_ptr);
768 len = data[6] * 256 + data[7];
769 start_offset = data[5] & 0x7f;
779 printf(
"{ mec: txdesc %i: ", tx_ring_ptr);
780 for (i=0; i<
sizeof(
data); i++) {
783 printf(
"%02x", data[i]);
792 for (i=start_offset; i<start_offset+len; i++) {
795 if ((i & 0x7f) == 0x00)
804 fatal(
"[ mec_try_tx: packet too large? ]\n");
816 if (!(data[4] & (0x01 << dma_ptr_nr)))
818 dma_base = (data[dma_ptr_nr * 8 + 4] << 24)
819 + (data[dma_ptr_nr * 8 + 5] << 16)
820 + (data[dma_ptr_nr * 8 + 6] << 8)
821 + (data[dma_ptr_nr * 8 + 7]);
822 dma_base &= 0xfffffff8ULL;
823 dma_len = (data[dma_ptr_nr * 8 + 2] << 8)
824 + (data[dma_ptr_nr * 8 + 3]) + 1;
829 while (dma_len > 0) {
837 fatal(
"[ mec_try_tx: packet too large?" 848 fatal(
"[ mec_try_tx: not enough data? ]\n");
854 if (data[4] & 0x01) {
874 ringread = (ringread >> 16) + 1;
879 (ringwrite & MEC_TX_RING_WRITE_PTR) |
897 while (mec_try_tx(cpu, d))
900 while (mec_try_rx(cpu, d) && n < 16)
919 uint64_t idata = 0, odata = 0;
925 regnr = relative_addr /
sizeof(uint64_t);
929 switch (relative_addr) {
932 d->
reg[regnr] = (d->
reg[regnr] & ~0xff)
933 | ((d->
reg[regnr] & ~idata) & 0xff);
937 d->
reg[regnr] = (d->
reg[regnr] &
942 d->
reg[regnr] = idata;
945 odata = d->
reg[regnr];
947 switch (relative_addr) {
950 mec_control_write(cpu, d, idata);
959 debug(
"[ sgi_mec: write to MEC_INT_STATUS: " 960 "0x%016llx ]\n", (
long long)idata);
964 debug(
"[ sgi_mec: write to MEC_DMA_CONTROL: " 965 "0x%016llx ]\n", (
long long)idata);
976 debug(
"[ sgi_mec: write to MEC_TX_ALIAS: " 977 "0x%016llx ]\n", (
long long)idata);
979 debug(
"[ sgi_mec: read from MEC_TX_ALIAS: " 980 "0x%016llx ]\n", (
long long)idata);
986 debug(
"[ sgi_mec: write to MEC_RX_ALIAS: " 987 "0x%016llx ]\n", (
long long)idata);
991 debug(
"[ sgi_mec: write to MEC_TX_RING_PTR: " 992 "0x%016llx ]\n", (
long long)idata);
996 fatal(
"[ sgi_mec: write to MEC_PHY_DATA: " 997 "0x%016llx ]\n", (
long long)idata);
1003 debug(
"[ sgi_mec: write to MEC_PHY_ADDRESS: " 1004 "0x%016llx ]\n", (
long long)idata);
1008 debug(
"[ sgi_mec: write to MEC_PHY_READ_INITIATE: " 1009 "0x%016llx ]\n", (
long long)idata);
1013 debug(
"[ sgi_mec: write to 0x74: 0x%016llx ]\n",
1016 debug(
"[ sgi_mec: read from 0x74 ]\n");
1020 debug(
"[ sgi_mec: setting the MAC address to " 1021 "%02x:%02x:%02x:%02x:%02x:%02x ]\n",
1022 (idata >> 40) & 255, (idata >> 32) & 255,
1023 (idata >> 24) & 255, (idata >> 16) & 255,
1024 (idata >> 8) & 255, (idata >> 0) & 255);
1028 debug(
"[ sgi_mec: setting the ALTERNATIVE MAC address" 1029 " to %02x:%02x:%02x:%02x:%02x:%02x ]\n",
1030 (idata >> 40) & 255, (idata >> 32) & 255,
1031 (idata >> 24) & 255, (idata >> 16) & 255,
1032 (idata >> 8) & 255, (idata >> 0) & 255);
1036 debug(
"[ sgi_mec: write to MEC_MULTICAST: " 1037 "0x%016llx ]\n", (
long long)idata);
1041 debug(
"[ sgi_mec: write to MEC_TX_RING_BASE: " 1042 "0x%016llx ]\n", (
long long)idata);
1046 debug(
"[ sgi_mec: write to MEC_MCL_RX_FIFO: 0x" 1047 "%016llx ]\n", (
long long)idata);
1055 fatal(
"[ sgi_mec: unimplemented write to address" 1056 " 0x%llx, data=0x%016llx ]\n",
1057 (
long long)relative_addr, (
long long)idata);
1059 fatal(
"[ sgi_mec: unimplemented read from address" 1060 " 0x%llx ]\n", (
long long)relative_addr);
1066 dev_sgi_mec_tick(cpu, extra);
1076 uint64_t baseaddr,
char *irq_path,
unsigned char *
macaddr)
1086 memcpy(d->
macaddr, macaddr, 6);
1090 snprintf(name2, nlen,
"mec [%02x:%02x:%02x:%02x:%02x:%02x]",
1116 uint64_t idata = 0, odata = 0;
1120 regnr = relative_addr /
sizeof(uint64_t);
1124 d->
reg[regnr] = idata;
1126 odata = d->
reg[regnr];
1128 switch (relative_addr) {
1130 d->
reg[regnr] += 0x2710;
1134 debug(
"[ sgi_ust: unimplemented write to " 1135 "address 0x%llx, data=0x%016llx ]\n",
1136 (
long long)relative_addr, (
long long)idata);
1138 debug(
"[ sgi_ust: unimplemented read from address" 1139 " 0x%llx ]\n", (
long long)relative_addr);
1177 #define ZERO_CHUNK_LEN 4096 1187 uint64_t first_addr, last_addr, zerobuflen, fill_addr, fill_len;
1189 uint64_t idata = 0, odata = 0;
1193 regnr = relative_addr /
sizeof(uint32_t);
1201 d->
reg[regnr] = idata >> 32;
1202 d->
reg[regnr+1] = idata;
1204 odata = ((uint64_t)d->
reg[regnr] << 32) +
1209 d->
reg[regnr] = idata;
1211 odata = d->
reg[regnr];
1214 if (writeflag ==
MEM_WRITE && relative_addr >= 0x2000 &&
1215 relative_addr < 0x3000)
1216 fatal(
"[ MTE: 0x%08x: 0x%016llx ]\n", (
int)relative_addr,
1239 switch (relative_addr) {
1283 uint32_t
op = d->
reg[0x2060 /
sizeof(uint32_t)];
1284 uint32_t color = d->
reg[0x20d0 /
sizeof(uint32_t)]&255;
1285 uint32_t x1 = (d->
reg[0x2070 /
sizeof(uint32_t)]
1287 uint32_t y1 = d->
reg[0x2070 /
sizeof(uint32_t)]& 0xfff;
1288 uint32_t x2 = (d->
reg[0x2074 /
sizeof(uint32_t)]
1290 uint32_t y2 = d->
reg[0x2074 /
sizeof(uint32_t)]& 0xfff;
1300 int tmp = x1; x1 = x2; x2 = tmp;
1303 int tmp = y1; y1 = y2; y2 = tmp;
1305 for (y=y1; y<=y2; y++) {
1306 unsigned char buf[1280];
1307 int length = x2-x1+1;
1308 int addr = (x1 + y*1280);
1311 memset(buf, color, length);
1312 if (x1 < 1280 && y < 1024)
1314 0x38000000 + addr, buf,
1320 default:
fatal(
"\n--- MTE OP %i color 0x%02x: %i,%i - " 1321 "%i,%i\n\n", op, color, x1,y1, x2,y2);
1329 uint32_t pixeldata = d->
reg[0x20c4 /
sizeof(uint32_t)];
1330 uint32_t color = d->
reg[0x20d0 /
sizeof(uint32_t)]&255;
1331 uint32_t x1 = (d->
reg[0x2070 /
sizeof(uint32_t)]
1333 uint32_t y1 = d->
reg[0x2070 /
sizeof(uint32_t)]& 0xfff;
1334 uint32_t x2 = (d->
reg[0x2074 /
sizeof(uint32_t)]
1336 uint32_t y2 = d->
reg[0x2074 /
sizeof(uint32_t)]& 0xfff;
1340 int tmp = x1; x1 = x2; x2 = tmp;
1343 int tmp = y1; y1 = y2; y2 = tmp;
1349 while (x <= x2 && y <= y2) {
1350 unsigned char buf = color;
1351 int addr = x + y*1280;
1352 int bit_set = pixeldata & 0x80000000UL;
1354 if (x < 1280 && y < 1024 && bit_set)
1373 first_addr = d->
reg[0x3030 /
sizeof(uint32_t)];
1374 last_addr = d->
reg[0x3038 /
sizeof(uint32_t)];
1375 zerobuflen = last_addr - first_addr + 1;
1376 debug(
"[ sgi_mte: zerofill: first = 0x%016llx," 1377 " last = 0x%016llx, length = 0x%llx ]\n",
1378 (
long long)first_addr, (
long long)
1379 last_addr, (
long long)zerobuflen);
1383 memset(zerobuf, 0,
sizeof(zerobuf));
1384 fill_addr = first_addr;
1385 while (zerobuflen != 0) {
1386 if (zerobuflen >
sizeof(zerobuf))
1387 fill_len =
sizeof(zerobuf);
1389 fill_len = zerobuflen;
1393 fill_addr += fill_len;
1394 zerobuflen -=
sizeof(zerobuf);
1399 fatal(
"[ sgi_mte: UNKNOWN operation " 1406 debug(
"[ sgi_mte: unimplemented write to " 1407 "address 0x%llx, data=0x%016llx ]\n",
1408 (
long long)relative_addr, (
long long)idata);
1410 debug(
"[ sgi_mte: unimplemented read from address" 1411 " 0x%llx ]\n", (
long long)relative_addr);
uint64_t memory_readmax64(struct cpu *cpu, unsigned char *buf, int len)
#define MEC_INT_RX_MCL_FIFO_ALIAS
void net_ethernet_tx(struct net *net, void *extra, unsigned char *packet, int len)
void fatal(const char *fmt,...)
#define MEC_INT_STATUS_MASK
void(* interrupt_assert)(struct interrupt *)
#define CRM_MEM_BANK_CTRL0
unsigned char reg[DEV_MACE_LENGTH]
#define MACE_ISA_INT_STATUS
void dev_sgi_ust_init(struct memory *mem, uint64_t baseaddr)
void interrupt_handler_register(struct interrupt *templ)
void(* interrupt_deassert)(struct interrupt *)
#define MEC_INT_TX_RING_BUFFER_ALIAS
void crime_interrupt_deassert(struct interrupt *interrupt)
struct pci_data * dev_macepci_init(struct machine *machine, struct memory *mem, uint64_t baseaddr, char *irq_path)
#define DEV_SGI_UST_LENGTH
uint32_t reg[DEV_MACEPCI_LENGTH/4]
uint32_t reg[DEV_SGI_MTE_LENGTH/sizeof(uint32_t)]
int cur_rx_addr_index_write
void * device_add(struct machine *machine, const char *name_and_params)
uint64_t rx_addr[N_RX_ADDRESSES]
#define DEV_SGI_MEC_LENGTH
#define MAX_TX_PACKET_LEN
#define CRIME_SPEED_DIV_FACTOR
int net_ethernet_rx(struct net *net, void *extra, unsigned char **packetp, int *lenp)
struct pci_data * pci_data
#define CHECK_ALLOCATION(ptr)
void mace_interrupt_assert(struct interrupt *interrupt)
void net_add_nic(struct net *net, void *extra, unsigned char *macaddr)
int dev_sgi_mec_access(struct cpu *cpu, struct memory *mem, uint64_t relative_addr, unsigned char *data, size_t len, int writeflag, void *)
#define MEC_TX_RING_WRITE_PTR
void crime_interrupt_assert(struct interrupt *interrupt)
void dev_sgi_mec_init(struct machine *machine, struct memory *mem, uint64_t baseaddr, char *irq_path, unsigned char *macaddr)
#define MEC_MAC_CORE_RESET
void bus_pci_setaddr(struct cpu *cpu, struct pci_data *pci_data, int bus, int device, int function, int reg)
int(* memory_rw)(struct cpu *cpu, struct memory *mem, uint64_t vaddr, unsigned char *data, size_t len, int writeflag, int cache_flags)
void dev_sgi_mte_init(struct memory *mem, uint64_t baseaddr)
#define MEC_INT_RX_THRESHOLD
uint64_t reg[DEV_SGI_MEC_LENGTH/sizeof(uint64_t)]
#define INTERRUPT_ASSERT(istruct)
#define MEC_DMA_TX_INT_ENABLE
#define DEV_MACEPCI_LENGTH
int dev_sgi_mte_access(struct cpu *cpu, struct memory *mem, uint64_t relative_addr, unsigned char *data, size_t len, int writeflag, void *)
#define CRM_MEM_BANK_CTRL1
#define MEC_MAC_REVISION_SHIFT
struct interrupt irq_periph
#define MEC_PHY_READ_INITIATE
uint64_t reg[DEV_SGI_UST_LENGTH/sizeof(uint64_t)]
unsigned char reg[DEV_CRIME_LENGTH]
int net_ethernet_rx_avail(struct net *net, void *extra)
int dev_sgi_ust_access(struct cpu *cpu, struct memory *mem, uint64_t relative_addr, unsigned char *data, size_t len, int writeflag, void *)
#define INTERRUPT_CONNECT(name, istruct)
#define MACE_ISA_INT_MASK
void memory_writemax64(struct cpu *cpu, unsigned char *buf, int len, uint64_t data)
void dev_crime_init(struct machine *machine, struct memory *mem, uint64_t baseaddr, char *irq_path, int use_fb)
int dev_macepci_access(struct cpu *cpu, struct memory *mem, uint64_t relative_addr, unsigned char *data, size_t len, int writeflag, void *)
void memory_device_register(struct memory *mem, const char *, uint64_t baseaddr, uint64_t len, int(*f)(struct cpu *, struct memory *, uint64_t, unsigned char *, size_t, int, void *), void *extra, int flags, unsigned char *dyntrans_data)
#define MACE_PERIPH_SERIAL
unsigned char * cur_rx_packet
void bus_pci_decompose_1(uint32_t t, int *bus, int *dev, int *func, int *reg)
struct pci_data * bus_pci_init(struct machine *machine, const char *irq_path, uint64_t pci_actual_io_offset, uint64_t pci_actual_mem_offset, uint64_t pci_portbase, uint64_t pci_membase, const char *pci_irqbase, uint64_t isa_portbase, uint64_t isa_membase, const char *isa_irqbase)
void machine_add_tickfunction(struct machine *machine, void(*func)(struct cpu *, void *), void *extra, int clockshift)
#define CRIME_SPEED_MUL_FACTOR
struct interrupt irq_misc
void bus_pci_data_access(struct cpu *cpu, struct pci_data *pci_data, uint64_t *data, int len, int writeflag)
unsigned char cur_tx_packet[MAX_TX_PACKET_LEN]
#define MEC_TX_RING_READ_PTR
#define MEC_INT_TX_PACKET_SENT
void mace_interrupt_deassert(struct interrupt *interrupt)
#define DEV_SGI_MTE_LENGTH
#define INTERRUPT_DEASSERT(istruct)