tmp_mips_loadstore_multi.cc Source File

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tmp_mips_loadstore_multi.cc
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1 
2 /* AUTOMATICALLY GENERATED! Do not edit. */
3 
4 X(multi_lw_2_le)
5 {
6  uint32_t *page;
7  MODE_uint_t rX = reg(ic[0].arg[1]), r0, r1;
8  MODE_uint_t addr0 = rX + (int32_t)ic[0].arg[2];
9  MODE_uint_t addr1 = rX + (int32_t)ic[1].arg[2];
10  uint32_t index0 = addr0 >> 12;
11  uint32_t index1 = addr1 >> 12;
12  page = (uint32_t *) cpu->cd.mips.host_load[index0];
13  if (cpu->delay_slot ||
14  page == NULL || (addr0 & 3) || (addr1 & 3)
15  || index1 != index0) {
16  mips32_loadstore[5](cpu, ic);
17  return;
18  }
19  addr0 = (addr0 >> 2) & 0x3ff;
20  addr1 = (addr1 >> 2) & 0x3ff;
21  r0 = page[addr0];
22  r1 = page[addr1];
23  r0 = LE32_TO_HOST(r0);
24  r1 = LE32_TO_HOST(r1);
25  reg(ic[0].arg[0]) = r0;
26  reg(ic[1].arg[0]) = r1;
28  cpu->cd.mips.next_ic += 1;
29 }
30 
31 X(multi_lw_3_le)
32 {
33  uint32_t *page;
34  MODE_uint_t rX = reg(ic[0].arg[1]), r0, r1, r2;
35  MODE_uint_t addr0 = rX + (int32_t)ic[0].arg[2];
36  MODE_uint_t addr1 = rX + (int32_t)ic[1].arg[2];
37  MODE_uint_t addr2 = rX + (int32_t)ic[2].arg[2];
38  uint32_t index0 = addr0 >> 12;
39  uint32_t index1 = addr1 >> 12;
40  uint32_t index2 = addr2 >> 12;
41  page = (uint32_t *) cpu->cd.mips.host_load[index0];
42  if (cpu->delay_slot ||
43  page == NULL || (addr0 & 3) || (addr1 & 3) || (addr2 & 3)
44  || index1 != index0 || index2 != index0) {
45  mips32_loadstore[5](cpu, ic);
46  return;
47  }
48  addr0 = (addr0 >> 2) & 0x3ff;
49  addr1 = (addr1 >> 2) & 0x3ff;
50  addr2 = (addr2 >> 2) & 0x3ff;
51  r0 = page[addr0];
52  r1 = page[addr1];
53  r2 = page[addr2];
54  r0 = LE32_TO_HOST(r0);
55  r1 = LE32_TO_HOST(r1);
56  r2 = LE32_TO_HOST(r2);
57  reg(ic[0].arg[0]) = r0;
58  reg(ic[1].arg[0]) = r1;
59  reg(ic[2].arg[0]) = r2;
61  cpu->cd.mips.next_ic += 2;
62 }
63 
64 X(multi_lw_4_le)
65 {
66  uint32_t *page;
67  MODE_uint_t rX = reg(ic[0].arg[1]), r0, r1, r2, r3;
68  MODE_uint_t addr0 = rX + (int32_t)ic[0].arg[2];
69  MODE_uint_t addr1 = rX + (int32_t)ic[1].arg[2];
70  MODE_uint_t addr2 = rX + (int32_t)ic[2].arg[2];
71  MODE_uint_t addr3 = rX + (int32_t)ic[3].arg[2];
72  uint32_t index0 = addr0 >> 12;
73  uint32_t index1 = addr1 >> 12;
74  uint32_t index2 = addr2 >> 12;
75  uint32_t index3 = addr3 >> 12;
76  page = (uint32_t *) cpu->cd.mips.host_load[index0];
77  if (cpu->delay_slot ||
78  page == NULL || (addr0 & 3) || (addr1 & 3) || (addr2 & 3) || (addr3 & 3)
79  || index1 != index0 || index2 != index0 || index3 != index0) {
80  mips32_loadstore[5](cpu, ic);
81  return;
82  }
83  addr0 = (addr0 >> 2) & 0x3ff;
84  addr1 = (addr1 >> 2) & 0x3ff;
85  addr2 = (addr2 >> 2) & 0x3ff;
86  addr3 = (addr3 >> 2) & 0x3ff;
87  r0 = page[addr0];
88  r1 = page[addr1];
89  r2 = page[addr2];
90  r3 = page[addr3];
91  r0 = LE32_TO_HOST(r0);
92  r1 = LE32_TO_HOST(r1);
93  r2 = LE32_TO_HOST(r2);
94  r3 = LE32_TO_HOST(r3);
95  reg(ic[0].arg[0]) = r0;
96  reg(ic[1].arg[0]) = r1;
97  reg(ic[2].arg[0]) = r2;
98  reg(ic[3].arg[0]) = r3;
100  cpu->cd.mips.next_ic += 3;
101 }
102 
103 X(multi_sw_2_le)
104 {
105  uint32_t *page;
106  MODE_uint_t rX = reg(ic[0].arg[1]), r0, r1;
107  MODE_uint_t addr0 = rX + (int32_t)ic[0].arg[2];
108  MODE_uint_t addr1 = rX + (int32_t)ic[1].arg[2];
109  uint32_t index0 = addr0 >> 12;
110  uint32_t index1 = addr1 >> 12;
111  page = (uint32_t *) cpu->cd.mips.host_store[index0];
112  if (cpu->delay_slot ||
113  page == NULL || (addr0 & 3) || (addr1 & 3)
114  || index1 != index0) {
115  mips32_loadstore[12](cpu, ic);
116  return;
117  }
118  addr0 = (addr0 >> 2) & 0x3ff;
119  addr1 = (addr1 >> 2) & 0x3ff;
120  r0 = reg(ic[0].arg[0]);
121  r1 = reg(ic[1].arg[0]);
122  r0 = LE32_TO_HOST(r0);
123  r1 = LE32_TO_HOST(r1);
124  page[addr0] = r0;
125  page[addr1] = r1;
126  cpu->n_translated_instrs += 1;
127  cpu->cd.mips.next_ic += 1;
128 }
129 
130 X(multi_sw_3_le)
131 {
132  uint32_t *page;
133  MODE_uint_t rX = reg(ic[0].arg[1]), r0, r1, r2;
134  MODE_uint_t addr0 = rX + (int32_t)ic[0].arg[2];
135  MODE_uint_t addr1 = rX + (int32_t)ic[1].arg[2];
136  MODE_uint_t addr2 = rX + (int32_t)ic[2].arg[2];
137  uint32_t index0 = addr0 >> 12;
138  uint32_t index1 = addr1 >> 12;
139  uint32_t index2 = addr2 >> 12;
140  page = (uint32_t *) cpu->cd.mips.host_store[index0];
141  if (cpu->delay_slot ||
142  page == NULL || (addr0 & 3) || (addr1 & 3) || (addr2 & 3)
143  || index1 != index0 || index2 != index0) {
144  mips32_loadstore[12](cpu, ic);
145  return;
146  }
147  addr0 = (addr0 >> 2) & 0x3ff;
148  addr1 = (addr1 >> 2) & 0x3ff;
149  addr2 = (addr2 >> 2) & 0x3ff;
150  r0 = reg(ic[0].arg[0]);
151  r1 = reg(ic[1].arg[0]);
152  r2 = reg(ic[2].arg[0]);
153  r0 = LE32_TO_HOST(r0);
154  r1 = LE32_TO_HOST(r1);
155  r2 = LE32_TO_HOST(r2);
156  page[addr0] = r0;
157  page[addr1] = r1;
158  page[addr2] = r2;
159  cpu->n_translated_instrs += 2;
160  cpu->cd.mips.next_ic += 2;
161 }
162 
163 X(multi_sw_4_le)
164 {
165  uint32_t *page;
166  MODE_uint_t rX = reg(ic[0].arg[1]), r0, r1, r2, r3;
167  MODE_uint_t addr0 = rX + (int32_t)ic[0].arg[2];
168  MODE_uint_t addr1 = rX + (int32_t)ic[1].arg[2];
169  MODE_uint_t addr2 = rX + (int32_t)ic[2].arg[2];
170  MODE_uint_t addr3 = rX + (int32_t)ic[3].arg[2];
171  uint32_t index0 = addr0 >> 12;
172  uint32_t index1 = addr1 >> 12;
173  uint32_t index2 = addr2 >> 12;
174  uint32_t index3 = addr3 >> 12;
175  page = (uint32_t *) cpu->cd.mips.host_store[index0];
176  if (cpu->delay_slot ||
177  page == NULL || (addr0 & 3) || (addr1 & 3) || (addr2 & 3) || (addr3 & 3)
178  || index1 != index0 || index2 != index0 || index3 != index0) {
179  mips32_loadstore[12](cpu, ic);
180  return;
181  }
182  addr0 = (addr0 >> 2) & 0x3ff;
183  addr1 = (addr1 >> 2) & 0x3ff;
184  addr2 = (addr2 >> 2) & 0x3ff;
185  addr3 = (addr3 >> 2) & 0x3ff;
186  r0 = reg(ic[0].arg[0]);
187  r1 = reg(ic[1].arg[0]);
188  r2 = reg(ic[2].arg[0]);
189  r3 = reg(ic[3].arg[0]);
190  r0 = LE32_TO_HOST(r0);
191  r1 = LE32_TO_HOST(r1);
192  r2 = LE32_TO_HOST(r2);
193  r3 = LE32_TO_HOST(r3);
194  page[addr0] = r0;
195  page[addr1] = r1;
196  page[addr2] = r2;
197  page[addr3] = r3;
198  cpu->n_translated_instrs += 3;
199  cpu->cd.mips.next_ic += 3;
200 }
201 
202 X(multi_lw_2_be)
203 {
204  uint32_t *page;
205  MODE_uint_t rX = reg(ic[0].arg[1]), r0, r1;
206  MODE_uint_t addr0 = rX + (int32_t)ic[0].arg[2];
207  MODE_uint_t addr1 = rX + (int32_t)ic[1].arg[2];
208  uint32_t index0 = addr0 >> 12;
209  uint32_t index1 = addr1 >> 12;
210  page = (uint32_t *) cpu->cd.mips.host_load[index0];
211  if (cpu->delay_slot ||
212  page == NULL || (addr0 & 3) || (addr1 & 3)
213  || index1 != index0) {
214  mips32_loadstore[21](cpu, ic);
215  return;
216  }
217  addr0 = (addr0 >> 2) & 0x3ff;
218  addr1 = (addr1 >> 2) & 0x3ff;
219  r0 = page[addr0];
220  r1 = page[addr1];
221  r0 = BE32_TO_HOST(r0);
222  r1 = BE32_TO_HOST(r1);
223  reg(ic[0].arg[0]) = r0;
224  reg(ic[1].arg[0]) = r1;
225  cpu->n_translated_instrs += 1;
226  cpu->cd.mips.next_ic += 1;
227 }
228 
229 X(multi_lw_3_be)
230 {
231  uint32_t *page;
232  MODE_uint_t rX = reg(ic[0].arg[1]), r0, r1, r2;
233  MODE_uint_t addr0 = rX + (int32_t)ic[0].arg[2];
234  MODE_uint_t addr1 = rX + (int32_t)ic[1].arg[2];
235  MODE_uint_t addr2 = rX + (int32_t)ic[2].arg[2];
236  uint32_t index0 = addr0 >> 12;
237  uint32_t index1 = addr1 >> 12;
238  uint32_t index2 = addr2 >> 12;
239  page = (uint32_t *) cpu->cd.mips.host_load[index0];
240  if (cpu->delay_slot ||
241  page == NULL || (addr0 & 3) || (addr1 & 3) || (addr2 & 3)
242  || index1 != index0 || index2 != index0) {
243  mips32_loadstore[21](cpu, ic);
244  return;
245  }
246  addr0 = (addr0 >> 2) & 0x3ff;
247  addr1 = (addr1 >> 2) & 0x3ff;
248  addr2 = (addr2 >> 2) & 0x3ff;
249  r0 = page[addr0];
250  r1 = page[addr1];
251  r2 = page[addr2];
252  r0 = BE32_TO_HOST(r0);
253  r1 = BE32_TO_HOST(r1);
254  r2 = BE32_TO_HOST(r2);
255  reg(ic[0].arg[0]) = r0;
256  reg(ic[1].arg[0]) = r1;
257  reg(ic[2].arg[0]) = r2;
258  cpu->n_translated_instrs += 2;
259  cpu->cd.mips.next_ic += 2;
260 }
261 
262 X(multi_lw_4_be)
263 {
264  uint32_t *page;
265  MODE_uint_t rX = reg(ic[0].arg[1]), r0, r1, r2, r3;
266  MODE_uint_t addr0 = rX + (int32_t)ic[0].arg[2];
267  MODE_uint_t addr1 = rX + (int32_t)ic[1].arg[2];
268  MODE_uint_t addr2 = rX + (int32_t)ic[2].arg[2];
269  MODE_uint_t addr3 = rX + (int32_t)ic[3].arg[2];
270  uint32_t index0 = addr0 >> 12;
271  uint32_t index1 = addr1 >> 12;
272  uint32_t index2 = addr2 >> 12;
273  uint32_t index3 = addr3 >> 12;
274  page = (uint32_t *) cpu->cd.mips.host_load[index0];
275  if (cpu->delay_slot ||
276  page == NULL || (addr0 & 3) || (addr1 & 3) || (addr2 & 3) || (addr3 & 3)
277  || index1 != index0 || index2 != index0 || index3 != index0) {
278  mips32_loadstore[21](cpu, ic);
279  return;
280  }
281  addr0 = (addr0 >> 2) & 0x3ff;
282  addr1 = (addr1 >> 2) & 0x3ff;
283  addr2 = (addr2 >> 2) & 0x3ff;
284  addr3 = (addr3 >> 2) & 0x3ff;
285  r0 = page[addr0];
286  r1 = page[addr1];
287  r2 = page[addr2];
288  r3 = page[addr3];
289  r0 = BE32_TO_HOST(r0);
290  r1 = BE32_TO_HOST(r1);
291  r2 = BE32_TO_HOST(r2);
292  r3 = BE32_TO_HOST(r3);
293  reg(ic[0].arg[0]) = r0;
294  reg(ic[1].arg[0]) = r1;
295  reg(ic[2].arg[0]) = r2;
296  reg(ic[3].arg[0]) = r3;
297  cpu->n_translated_instrs += 3;
298  cpu->cd.mips.next_ic += 3;
299 }
300 
301 X(multi_sw_2_be)
302 {
303  uint32_t *page;
304  MODE_uint_t rX = reg(ic[0].arg[1]), r0, r1;
305  MODE_uint_t addr0 = rX + (int32_t)ic[0].arg[2];
306  MODE_uint_t addr1 = rX + (int32_t)ic[1].arg[2];
307  uint32_t index0 = addr0 >> 12;
308  uint32_t index1 = addr1 >> 12;
309  page = (uint32_t *) cpu->cd.mips.host_store[index0];
310  if (cpu->delay_slot ||
311  page == NULL || (addr0 & 3) || (addr1 & 3)
312  || index1 != index0) {
313  mips32_loadstore[28](cpu, ic);
314  return;
315  }
316  addr0 = (addr0 >> 2) & 0x3ff;
317  addr1 = (addr1 >> 2) & 0x3ff;
318  r0 = reg(ic[0].arg[0]);
319  r1 = reg(ic[1].arg[0]);
320  r0 = BE32_TO_HOST(r0);
321  r1 = BE32_TO_HOST(r1);
322  page[addr0] = r0;
323  page[addr1] = r1;
324  cpu->n_translated_instrs += 1;
325  cpu->cd.mips.next_ic += 1;
326 }
327 
328 X(multi_sw_3_be)
329 {
330  uint32_t *page;
331  MODE_uint_t rX = reg(ic[0].arg[1]), r0, r1, r2;
332  MODE_uint_t addr0 = rX + (int32_t)ic[0].arg[2];
333  MODE_uint_t addr1 = rX + (int32_t)ic[1].arg[2];
334  MODE_uint_t addr2 = rX + (int32_t)ic[2].arg[2];
335  uint32_t index0 = addr0 >> 12;
336  uint32_t index1 = addr1 >> 12;
337  uint32_t index2 = addr2 >> 12;
338  page = (uint32_t *) cpu->cd.mips.host_store[index0];
339  if (cpu->delay_slot ||
340  page == NULL || (addr0 & 3) || (addr1 & 3) || (addr2 & 3)
341  || index1 != index0 || index2 != index0) {
342  mips32_loadstore[28](cpu, ic);
343  return;
344  }
345  addr0 = (addr0 >> 2) & 0x3ff;
346  addr1 = (addr1 >> 2) & 0x3ff;
347  addr2 = (addr2 >> 2) & 0x3ff;
348  r0 = reg(ic[0].arg[0]);
349  r1 = reg(ic[1].arg[0]);
350  r2 = reg(ic[2].arg[0]);
351  r0 = BE32_TO_HOST(r0);
352  r1 = BE32_TO_HOST(r1);
353  r2 = BE32_TO_HOST(r2);
354  page[addr0] = r0;
355  page[addr1] = r1;
356  page[addr2] = r2;
357  cpu->n_translated_instrs += 2;
358  cpu->cd.mips.next_ic += 2;
359 }
360 
361 X(multi_sw_4_be)
362 {
363  uint32_t *page;
364  MODE_uint_t rX = reg(ic[0].arg[1]), r0, r1, r2, r3;
365  MODE_uint_t addr0 = rX + (int32_t)ic[0].arg[2];
366  MODE_uint_t addr1 = rX + (int32_t)ic[1].arg[2];
367  MODE_uint_t addr2 = rX + (int32_t)ic[2].arg[2];
368  MODE_uint_t addr3 = rX + (int32_t)ic[3].arg[2];
369  uint32_t index0 = addr0 >> 12;
370  uint32_t index1 = addr1 >> 12;
371  uint32_t index2 = addr2 >> 12;
372  uint32_t index3 = addr3 >> 12;
373  page = (uint32_t *) cpu->cd.mips.host_store[index0];
374  if (cpu->delay_slot ||
375  page == NULL || (addr0 & 3) || (addr1 & 3) || (addr2 & 3) || (addr3 & 3)
376  || index1 != index0 || index2 != index0 || index3 != index0) {
377  mips32_loadstore[28](cpu, ic);
378  return;
379  }
380  addr0 = (addr0 >> 2) & 0x3ff;
381  addr1 = (addr1 >> 2) & 0x3ff;
382  addr2 = (addr2 >> 2) & 0x3ff;
383  addr3 = (addr3 >> 2) & 0x3ff;
384  r0 = reg(ic[0].arg[0]);
385  r1 = reg(ic[1].arg[0]);
386  r2 = reg(ic[2].arg[0]);
387  r3 = reg(ic[3].arg[0]);
388  r0 = BE32_TO_HOST(r0);
389  r1 = BE32_TO_HOST(r1);
390  r2 = BE32_TO_HOST(r2);
391  r3 = BE32_TO_HOST(r3);
392  page[addr0] = r0;
393  page[addr1] = r1;
394  page[addr2] = r2;
395  page[addr3] = r3;
396  cpu->n_translated_instrs += 3;
397  cpu->cd.mips.next_ic += 3;
398 }
399 
#define MODE_uint_t
uint8_t delay_slot
Definition: cpu.h:356
page
X(multi_lw_2_le)
struct arm_instr_call * ic
union cpu::@1 cd
#define BE32_TO_HOST(x)
Definition: misc.h:181
#define reg(x)
#define LE32_TO_HOST(x)
Definition: misc.h:180
Definition: cpu.h:326
int n_translated_instrs
Definition: cpu.h:427
struct mips_cpu mips
Definition: cpu.h:443
addr & if(addr >=0x24 &&page !=NULL)

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