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cpu_arm.h
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1 #ifndef CPU_ARM_H
2 #define CPU_ARM_H
3 
4 /*
5  * Copyright (C) 2005-2010 Anders Gavare. All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions are met:
9  *
10  * 1. Redistributions of source code must retain the above copyright
11  * notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  * notice, this list of conditions and the following disclaimer in the
14  * documentation and/or other materials provided with the distribution.
15  * 3. The name of the author may not be used to endorse or promote products
16  * derived from this software without specific prior written permission.
17  *
18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28  * SUCH DAMAGE.
29  *
30  *
31  * ARM CPU definitions.
32  */
33 
34 #include "misc.h"
35 #include "interrupt.h"
36 
37 struct cpu_family;
38 
39 /* ARM CPU types: */
41  const char *name;
42  uint32_t cpu_id;
43  int flags;
45  int iway;
47  int dway;
48 };
49 
50 
51 #define ARM_SL 10
52 #define ARM_FP 11
53 #define ARM_IP 12
54 #define ARM_SP 13
55 #define ARM_LR 14
56 #define ARM_PC 15
57 #define N_ARM_REGS 16
58 
59 #define ARM_REG_NAMES { \
60  "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
61  "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }
62 
63 #define ARM_CONDITION_STRINGS { \
64  "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", \
65  "hi", "ls", "ge", "lt", "gt", "le", "" /*Always*/ , "(INVALID)" }
66 
67 /* Names of Data Processing Instructions: */
68 #define ARM_DPI_NAMES { \
69  "and", "eor", "sub", "rsb", "add", "adc", "sbc", "rsc", \
70  "tst", "teq", "cmp", "cmn", "orr", "mov", "bic", "mvn" }
71 
72 #define ARM_IC_ENTRIES_SHIFT 10
73 
74 #define ARM_N_IC_ARGS 3
75 #define ARM_INSTR_ALIGNMENT_SHIFT 2
76 #define ARM_IC_ENTRIES_PER_PAGE (1 << ARM_IC_ENTRIES_SHIFT)
77 #define ARM_PC_TO_IC_ENTRY(a) (((a)>>ARM_INSTR_ALIGNMENT_SHIFT) \
78  & (ARM_IC_ENTRIES_PER_PAGE-1))
79 #define ARM_ADDR_TO_PAGENR(a) ((a) >> (ARM_IC_ENTRIES_SHIFT \
80  + ARM_INSTR_ALIGNMENT_SHIFT))
81 
82 #define ARM_F_N 8 /* Same as ARM_FLAG_*, but */
83 #define ARM_F_Z 4 /* for the 'flags' field instead */
84 #define ARM_F_C 2 /* of cpsr. */
85 #define ARM_F_V 1
86 
87 #define ARM_FLAG_N 0x80000000 /* Negative flag */
88 #define ARM_FLAG_Z 0x40000000 /* Zero flag */
89 #define ARM_FLAG_C 0x20000000 /* Carry flag */
90 #define ARM_FLAG_V 0x10000000 /* Overflow flag */
91 #define ARM_FLAG_Q 0x08000000 /* DSP saturation overflow */
92 #define ARM_FLAG_I 0x00000080 /* Interrupt disable */
93 #define ARM_FLAG_F 0x00000040 /* Fast Interrupt disable */
94 #define ARM_FLAG_T 0x00000020 /* Thumb mode */
95 
96 #define ARM_FLAG_MODE 0x0000001f
97 #define ARM_MODE_USR26 0x00
98 #define ARM_MODE_FIQ26 0x01
99 #define ARM_MODE_IRQ26 0x02
100 #define ARM_MODE_SVC26 0x03
101 #define ARM_MODE_USR32 0x10
102 #define ARM_MODE_FIQ32 0x11
103 #define ARM_MODE_IRQ32 0x12
104 #define ARM_MODE_SVC32 0x13
105 #define ARM_MODE_ABT32 0x17
106 #define ARM_MODE_UND32 0x1b
107 #define ARM_MODE_SYS32 0x1f
108 
109 #define ARM_EXCEPTION_TO_MODE { \
110  ARM_MODE_SVC32, ARM_MODE_UND32, ARM_MODE_SVC32, ARM_MODE_ABT32, \
111  ARM_MODE_ABT32, 0, ARM_MODE_IRQ32, ARM_MODE_FIQ32 }
112 
113 #define N_ARM_EXCEPTIONS 8
114 
115 #define ARM_EXCEPTION_RESET 0
116 #define ARM_EXCEPTION_UND 1
117 #define ARM_EXCEPTION_SWI 2
118 #define ARM_EXCEPTION_PREF_ABT 3
119 #define ARM_EXCEPTION_DATA_ABT 4
120 /* 5 was address exception in 26-bit ARM */
121 #define ARM_EXCEPTION_IRQ 6
122 #define ARM_EXCEPTION_FIQ 7
123 
124 DYNTRANS_MISC_DECLARATIONS(arm,ARM,uint32_t)
125 
126 #define ARM_MAX_VPH_TLB_ENTRIES 384
127 
128 
129 struct arm_cpu {
130  /*
131  * Misc.:
132  */
133  struct arm_cpu_type_def cpu_type;
134  uint32_t of_emul_addr;
135 
136  void (*coproc[16])(struct cpu *, int opcode1,
137  int opcode2, int l_bit, int crn, int crm,
138  int rd);
139 
140  /*
141  * General Purpose Registers (including the program counter):
142  *
143  * r[] always contains the current register set. The others are
144  * only used to swap to/from when changing modes. (An exception is
145  * r[0..7], which are never swapped out, they are always present.)
146  */
147 
148  uint32_t r[N_ARM_REGS];
149 
150  uint32_t default_r8_r14[7]; /* usr and sys */
151  uint32_t fiq_r8_r14[7];
152  uint32_t irq_r13_r14[2];
153  uint32_t svc_r13_r14[2];
154  uint32_t abt_r13_r14[2];
155  uint32_t und_r13_r14[2];
156 
157  uint32_t tmp_pc; /* Used for load/stores */
158 
159  /*
160  * Flag/status registers:
161  *
162  * NOTE: 'flags' just contains the 4 flag bits. When cpsr is read,
163  * the flags should be copied from 'flags', and when cpsr is written
164  * to, 'flags' should be updated as well.
165  */
166  size_t flags;
167  uint32_t cpsr;
168  uint32_t spsr_svc;
169  uint32_t spsr_abt;
170  uint32_t spsr_und;
171  uint32_t spsr_irq;
172  uint32_t spsr_fiq;
173 
174 
175  /*
176  * System Control Coprocessor registers:
177  */
178  uint32_t cachetype; /* Cache Type Register */
179  uint32_t control; /* Control Register */
180  uint32_t auxctrl; /* Aux. Control Register */
181  uint32_t ttb; /* Translation Table Base */
182  uint32_t dacr; /* Domain Access Control */
183  uint32_t fsr; /* Fault Status Register */
184  uint32_t far; /* Fault Address Register */
185  uint32_t pid; /* Process Id Register */
186  uint32_t cpar; /* CoProcessor Access Reg. */
187 
188  /* i80321 Coprocessor 6: ICU (Interrupt controller) */
189  uint32_t i80321_inten; /* enable */
190  uint32_t i80321_isteer;
191  uint32_t i80321_isrc; /* current assertions */
192  uint32_t tmr0;
193  uint32_t tmr1;
194  struct interrupt tmr0_irq;
195  struct interrupt tmr1_irq;
196  uint32_t tcr0;
197  uint32_t tcr1;
198  uint32_t trr0;
199  uint32_t trr1;
200  uint32_t tisr;
201  uint32_t wdtcr;
202 
203  /* XScale Coprocessor 14: (Performance Monitoring Unit) */
204  /* XSC1 access style: */
205  uint32_t xsc1_pmnc; /* Perf. Monitor Ctrl Reg. */
206  uint32_t xsc1_ccnt; /* Clock Counter */
207  uint32_t xsc1_pmn0; /* Perf. Counter Reg. 0 */
208  uint32_t xsc1_pmn1; /* Perf. Counter Reg. 1 */
209  /* XSC2 access style: */
210  uint32_t xsc2_pmnc; /* Perf. Monitor Ctrl Reg. */
211  uint32_t xsc2_ccnt; /* Clock Counter */
212  uint32_t xsc2_inten; /* Interrupt Enable */
213  uint32_t xsc2_flag; /* Overflow Flag Register */
214  uint32_t xsc2_evtsel; /* Event Selection Register */
215  uint32_t xsc2_pmn0; /* Perf. Counter Reg. 0 */
216  uint32_t xsc2_pmn1; /* Perf. Counter Reg. 1 */
217  uint32_t xsc2_pmn2; /* Perf. Counter Reg. 2 */
218  uint32_t xsc2_pmn3; /* Perf. Counter Reg. 3 */
219 
220  /* For caching the host address of the L1 translation table: */
221  unsigned char *translation_table;
222  uint32_t last_ttb;
223 
224  /*
225  * Interrupts:
226  */
228 
229 
230  /*
231  * Instruction translation cache, and 32-bit virtual -> physical ->
232  * host address translation:
233  */
234  DYNTRANS_ITC(arm)
235  VPH_TLBS(arm,ARM)
236  VPH32_16BITVPHENTRIES(arm,ARM)
237 
238  /* ARM specific: */
239  uint32_t is_userpage[N_VPH32_ENTRIES/32];
240 };
241 
242 
243 /* System Control Coprocessor, control bits: */
244 #define ARM_CONTROL_MMU 0x0001
245 #define ARM_CONTROL_ALIGN 0x0002
246 #define ARM_CONTROL_CACHE 0x0004
247 #define ARM_CONTROL_WBUFFER 0x0008
248 #define ARM_CONTROL_PROG32 0x0010
249 #define ARM_CONTROL_DATA32 0x0020
250 #define ARM_CONTROL_BIG 0x0080
251 #define ARM_CONTROL_S 0x0100
252 #define ARM_CONTROL_R 0x0200
253 #define ARM_CONTROL_F 0x0400
254 #define ARM_CONTROL_Z 0x0800
255 #define ARM_CONTROL_ICACHE 0x1000
256 #define ARM_CONTROL_V 0x2000
257 #define ARM_CONTROL_RR 0x4000
258 #define ARM_CONTROL_L4 0x8000
259 
260 /* Auxiliary Control Register bits: */
261 #define ARM_AUXCTRL_MD 0x30 /* MiniData Cache Attribute */
262 #define ARM_AUXCTRL_MD_SHIFT 4
263 #define ARM_AUXCTRL_P 0x02 /* Page Table Memory Attribute */
264 #define ARM_AUXCTRL_K 0x01 /* Write Buffer Coalescing Disable */
265 
266 /* Cache Type register bits: */
267 #define ARM_CACHETYPE_CLASS 0x1e000000
268 #define ARM_CACHETYPE_CLASS_SHIFT 25
269 #define ARM_CACHETYPE_HARVARD 0x01000000
270 #define ARM_CACHETYPE_HARVARD_SHIFT 24
271 #define ARM_CACHETYPE_DSIZE 0x001c0000
272 #define ARM_CACHETYPE_DSIZE_SHIFT 18
273 #define ARM_CACHETYPE_DASSOC 0x00038000
274 #define ARM_CACHETYPE_DASSOC_SHIFT 15
275 #define ARM_CACHETYPE_DLINE 0x00003000
276 #define ARM_CACHETYPE_DLINE_SHIFT 12
277 #define ARM_CACHETYPE_ISIZE 0x000001c0
278 #define ARM_CACHETYPE_ISIZE_SHIFT 6
279 #define ARM_CACHETYPE_IASSOC 0x00000038
280 #define ARM_CACHETYPE_IASSOC_SHIFT 3
281 #define ARM_CACHETYPE_ILINE 0x00000003
282 #define ARM_CACHETYPE_ILINE_SHIFT 0
283 
284 /* cpu_arm.c: */
285 void arm_setup_initial_translation_table(struct cpu *cpu, uint32_t ttb_addr);
286 void arm_translation_table_set_l1(struct cpu *cpu, uint32_t vaddr,
287  uint32_t paddr);
288 void arm_translation_table_set_l1_b(struct cpu *cpu, uint32_t vaddr,
289  uint32_t paddr);
290 void arm_exception(struct cpu *, int);
291 int arm_run_instr(struct cpu *cpu);
292 void arm_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
293  unsigned char *host_page, int writeflag, uint64_t paddr_page);
294 void arm_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
295 void arm_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
296 void arm_load_register_bank(struct cpu *cpu);
297 void arm_save_register_bank(struct cpu *cpu);
298 int arm_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
299  unsigned char *data, size_t len, int writeflag, int cache_flags);
300 int arm_cpu_family_init(struct cpu_family *);
301 
302 /* cpu_arm_coproc.c: */
303 void arm_coproc_15(struct cpu *cpu, int opcode1, int opcode2, int l_bit,
304  int crn, int crm, int rd);
305 void arm_coproc_i80321_6(struct cpu *cpu, int opcode1, int opcode2, int l_bit,
306  int crn, int crm, int rd);
307 void arm_coproc_xscale_14(struct cpu *cpu, int opcode1, int opcode2, int l_bit,
308  int crn, int crm, int rd);
309 
310 /* memory_arm.c: */
311 int arm_translate_v2p(struct cpu *cpu, uint64_t vaddr,
312  uint64_t *return_addr, int flags);
313 int arm_translate_v2p_mmu(struct cpu *cpu, uint64_t vaddr,
314  uint64_t *return_addr, int flags);
315 
316 #endif /* CPU_ARM_H */
#define N_ARM_REGS
Definition: cpu_arm.h:57
#define DYNTRANS_MISC_DECLARATIONS(arch, ARCH, addrtype)
Definition: cpu.h:72
const char * name
Definition: cpu_arm.h:41
uint32_t spsr_irq
Definition: cpu_arm.h:171
uint32_t xsc2_pmn0
Definition: cpu_arm.h:215
uint32_t tisr
Definition: cpu_arm.h:200
#define N_VPH32_ENTRIES
Definition: cpu.h:188
uint32_t i80321_isrc
Definition: cpu_arm.h:191
int arm_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr, unsigned char *data, size_t len, int writeflag, int cache_flags)
uint32_t last_ttb
Definition: cpu_arm.h:222
uint32_t ttb
Definition: cpu_arm.h:181
uint32_t xsc2_flag
Definition: cpu_arm.h:213
void arm_invalidate_code_translation(struct cpu *cpu, uint64_t, int)
int icache_shift
Definition: cpu_arm.h:44
uint32_t far
Definition: cpu_arm.h:184
uint32_t auxctrl
Definition: cpu_arm.h:180
void arm_load_register_bank(struct cpu *cpu)
Definition: cpu_arm.cc:542
int dcache_shift
Definition: cpu_arm.h:46
void arm_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, unsigned char *host_page, int writeflag, uint64_t paddr_page)
uint32_t spsr_fiq
Definition: cpu_arm.h:172
uint32_t pid
Definition: cpu_arm.h:185
void arm_coproc_i80321_6(struct cpu *cpu, int opcode1, int opcode2, int l_bit, int crn, int crm, int rd)
uint32_t i80321_isteer
Definition: cpu_arm.h:190
uint32_t control
Definition: cpu_arm.h:179
uint32_t fsr
Definition: cpu_arm.h:183
uint32_t tmr0
Definition: cpu_arm.h:192
uint32_t xsc1_pmn1
Definition: cpu_arm.h:208
uint32_t trr1
Definition: cpu_arm.h:199
void arm_setup_initial_translation_table(struct cpu *cpu, uint32_t ttb_addr)
Definition: cpu_arm.cc:204
int arm_run_instr(struct cpu *cpu)
uint32_t tmr1
Definition: cpu_arm.h:193
u_short data
Definition: siireg.h:79
uint32_t xsc2_pmn1
Definition: cpu_arm.h:216
#define DYNTRANS_ITC(arch)
Definition: cpu.h:143
uint32_t xsc2_pmn2
Definition: cpu_arm.h:217
void arm_coproc_xscale_14(struct cpu *cpu, int opcode1, int opcode2, int l_bit, int crn, int crm, int rd)
uint32_t tmp_pc
Definition: cpu_arm.h:157
uint32_t spsr_und
Definition: cpu_arm.h:170
int arm_cpu_family_init(struct cpu_family *)
uint32_t xsc2_inten
Definition: cpu_arm.h:212
uint32_t i80321_inten
Definition: cpu_arm.h:189
uint32_t xsc1_ccnt
Definition: cpu_arm.h:206
uint32_t xsc2_evtsel
Definition: cpu_arm.h:214
int irq_asserted
Definition: cpu_arm.h:227
uint32_t tcr0
Definition: cpu_arm.h:196
uint32_t dacr
Definition: cpu_arm.h:182
uint32_t tcr1
Definition: cpu_arm.h:197
Definition: cpu.h:326
uint32_t wdtcr
Definition: cpu_arm.h:201
#define VPH32_16BITVPHENTRIES(arch, ARCH)
Definition: cpu.h:195
uint32_t spsr_abt
Definition: cpu_arm.h:169
int arm_translate_v2p_mmu(struct cpu *cpu, uint64_t vaddr, uint64_t *return_addr, int flags)
Definition: memory_arm.cc:112
void arm_translation_table_set_l1(struct cpu *cpu, uint32_t vaddr, uint32_t paddr)
Definition: cpu_arm.cc:240
uint32_t xsc2_pmnc
Definition: cpu_arm.h:210
uint32_t spsr_svc
Definition: cpu_arm.h:168
uint32_t xsc2_ccnt
Definition: cpu_arm.h:211
void arm_save_register_bank(struct cpu *cpu)
Definition: cpu_arm.cc:495
size_t flags
Definition: cpu_arm.h:166
uint32_t xsc2_pmn3
Definition: cpu_arm.h:218
#define VPH_TLBS(arch, ARCH)
Definition: cpu.h:157
void arm_exception(struct cpu *, int)
Definition: cpu_arm.cc:589
Definition: memory.h:75
uint32_t of_emul_addr
Definition: cpu_arm.h:134
void arm_translation_table_set_l1_b(struct cpu *cpu, uint32_t vaddr, uint32_t paddr)
Definition: cpu_arm.cc:268
void arm_coproc_15(struct cpu *cpu, int opcode1, int opcode2, int l_bit, int crn, int crm, int rd)
uint32_t cpsr
Definition: cpu_arm.h:167
uint32_t xsc1_pmn0
Definition: cpu_arm.h:207
uint32_t cachetype
Definition: cpu_arm.h:178
uint32_t xsc1_pmnc
Definition: cpu_arm.h:205
uint32_t cpu_id
Definition: cpu_arm.h:42
uint32_t cpar
Definition: cpu_arm.h:186
void arm_invalidate_translation_caches(struct cpu *cpu, uint64_t, int)
unsigned char * translation_table
Definition: cpu_arm.h:221
uint32_t trr0
Definition: cpu_arm.h:198
int arm_translate_v2p(struct cpu *cpu, uint64_t vaddr, uint64_t *return_addr, int flags)
Definition: memory_arm.cc:52

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