sh4_bscreg.h Source File

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sh4_bscreg.h
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1 /* $NetBSD: bscreg.h,v 1.6 2005/12/11 12:18:58 christos Exp $ */
2 
3 /* This file has been extended with useful bitfield definitions from
4  the SH7750 manual. */
5 
6 #ifndef _SH3_BSCREG_H_
7 #define _SH3_BSCREG_H_
8 
9 /*-
10  * Copyright (C) 1999 SAITOH Masanobu. All rights reserved.
11  *
12  * Redistribution and use in source and binary forms, with or without
13  * modification, are permitted provided that the following conditions
14  * are met:
15  * 1. Redistributions of source code must retain the above copyright
16  * notice, this list of conditions and the following disclaimer.
17  * 2. Redistributions in binary form must reproduce the above copyright
18  * notice, this list of conditions and the following disclaimer in the
19  * documentation and/or other materials provided with the distribution.
20  * 3. The name of the author may not be used to endorse or promote products
21  * derived from this software without specific prior written permission.
22  *
23  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
24  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
25  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
27  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33  */
34 
35 /* #include <sh3/devreg.h> */
36 
37 /*
38  * Bus State Controller
39  */
40 
41 #define SH3_BCR1 0xffffff60 /* 16bit */
42 #define SH3_BCR2 0xffffff62 /* 16bit */
43 #define SH3_WCR1 0xffffff64 /* 16bit */
44 #define SH3_WCR2 0xffffff66 /* 16bit */
45 #define SH3_MCR 0xffffff68 /* 16bit */
46 #define SH3_DCR 0xffffff6a /* 16bit */
47 #define SH3_PCR 0xffffff6c /* 16bit */
48 #define SH3_RTCSR 0xffffff6e /* 16bit */
49 #define SH3_RTCNT 0xffffff70 /* 16bit */
50 #define SH3_RTCOR 0xffffff72 /* 16bit */
51 #define SH3_RFCR 0xffffff74 /* 16bit */
52 #define SH3_BCR3 0xffffff7e /* 16bit */
53 
54 #define SH4_BCR1 0xff800000 /* 32bit */
55 #define SH4_BCR2 0xff800004 /* 16bit */
56 #define SH4_WCR1 0xff800008 /* 32bit */
57 #define SH4_WCR2 0xff80000c /* 32bit */
58 #define SH4_WCR3 0xff800010 /* 32bit */
59 #define SH4_MCR 0xff800014 /* 32bit */
60 #define SH4_PCR 0xff800018 /* 16bit */
61 #define SH4_RTCSR 0xff80001c /* 16bit */
62 #define SH4_RTCNT 0xff800020 /* 16bit */
63 #define SH4_RTCOR 0xff800024 /* 16bit */
64 #define SH4_RFCR 0xff800028 /* 16bit */
65 #define SH4_PCTRA 0xff80002c /* ??? */
66 #define SH4_PDTRA 0xff800030 /* ??? */
67 #define SH4_PCTRB 0xff800040 /* ??? */
68 #define SH4_PDTRB 0xff800044 /* ??? */
69 #define SH4_GPIOIC 0xff800048 /* ??? */
70 #define SH4_BCR3 0xff800050 /* 16bit: SH7751R */
71 #define SH4_BCR4 0xfe0a00f0 /* 32bit: SH7751R */
72 
73 #define BCR1_LITTLE_ENDIAN (1 << 31)
74 #define BCR1_MASTER (1 << 30)
75 #define BCR1_BREQEN (1 << 19)
76 
77 #define BCR2_PORTEN (1 << 0)
78 
79 #define RTCSR_CMF (1 << 7)
80 #define RTCSR_CMIE (1 << 6)
81 #define RTCSR_CKS 0x0038
82 #define RTCSR_OVF (1 << 2)
83 #define RTCSR_OVIE (1 << 1)
84 #define RTCSR_LMTS (1 << 0)
85 
86 #endif /* !_SH3_BSCREG_H_ */

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