sh4_dmacreg.h Source File

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sh4_dmacreg.h
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1 #ifndef SH4_DMACREG_H
2 #define SH4_DMACREG_H
3 
4 /*
5  * Copyright (C) 2006-2011 Anders Gavare. All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions are met:
9  *
10  * 1. Redistributions of source code must retain the above copyright
11  * notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  * notice, this list of conditions and the following disclaimer in the
14  * documentation and/or other materials provided with the distribution.
15  * 3. The name of the author may not be used to endorse or promote products
16  * derived from this software without specific prior written permission.
17  *
18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28  * SUCH DAMAGE.
29  *
30  *
31  * SH4 DMAC (DMA Controller) registers, as listed in the SH-7750 and
32  * SH-7760 manuals.
33  */
34 
35 #define N_SH4_DMA_CHANNELS 8 /* 4 on 7750, 8 on 7760 */
36 
37 #define SH4_SAR0 0xffa00000 /* Source Address Register */
38 #define SH4_DAR0 0xffa00004 /* Destination Address Register */
39 #define SH4_DMATCR0 0xffa00008 /* Transfer Count Register */
40 #define SH4_CHCR0 0xffa0000c /* Channel Control Register */
41 
42 #define SH4_SAR1 0xffa00010
43 #define SH4_DAR1 0xffa00014
44 #define SH4_DMATCR1 0xffa00018
45 #define SH4_CHCR1 0xffa0001c
46 
47 #define SH4_SAR2 0xffa00020
48 #define SH4_DAR2 0xffa00024
49 #define SH4_DMATCR2 0xffa00028
50 #define SH4_CHCR2 0xffa0002c
51 
52 #define SH4_SAR3 0xffa00030
53 #define SH4_DAR3 0xffa00034
54 #define SH4_DMATCR3 0xffa00038
55 #define SH4_CHCR3 0xffa0003c
56 
57 #define SH4_DMAOR 0xffa00040 /* DMA operation register */
58 #define DMAOR_DDT 0x00008000 /* On-Demand Data Transfer */
59 #define DMAOR_PR1 0x00000200 /* Priority Mode 1 */
60 #define DMAOR_PR0 0x00000100 /* Priority Mode 0 */
61 #define DMAOR_AE 0x00000004 /* Address Error flag */
62 #define DMAOR_NMIF 0x00000002 /* NMI flag */
63 #define DMAOR_DME 0x00000001 /* DMAC master enable */
64 
65 /* NOTE: Channel 4 doesn't start at 0xffa00040, but 0xffa00050! */
66 
67 #define SH4_SAR4 0xffa00050
68 #define SH4_DAR4 0xffa00054
69 #define SH4_DMATCR4 0xffa00058
70 #define SH4_CHCR4 0xffa0005c
71 
72 #define SH4_SAR5 0xffa00060
73 #define SH4_DAR5 0xffa00064
74 #define SH4_DMATCR5 0xffa00068
75 #define SH4_CHCR5 0xffa0006c
76 
77 #define SH4_SAR6 0xffa00070
78 #define SH4_DAR6 0xffa00074
79 #define SH4_DMATCR6 0xffa00078
80 #define SH4_CHCR6 0xffa0007c
81 
82 #define SH4_SAR7 0xffa00080
83 #define SH4_DAR7 0xffa00084
84 #define SH4_DMATCR7 0xffa00088
85 #define SH4_CHCR7 0xffa0008c
86 
87 
88 /*
89  * CHCR (Channel Control Register) bit definitions:
90  */
91 
92 #define CHCR_SSA_MASK 0xe0000000 /* Source Address Space Attribute Specification */
93  /* (Only valid for PCMCIA access, in areas 5 and 6.) */
94 #define CHCR_SSA_RESERVED (0 << 29)
95 #define CHCR_SSA_DYNAMIC_BUS_SIZING (1 << 29)
96 #define CHCR_SSA_8BIT_IO_SPACE (2 << 29)
97 #define CHCR_SSA_16BIT_IO_SPACE (3 << 29)
98 #define CHCR_SSA_8BIT_COMMON_MEMORY_SPACE (4 << 29)
99 #define CHCR_SSA_16BIT_COMMON_MEMORY_SPACE (5 << 29)
100 #define CHCR_SSA_8BIT_ATTRIBUTE_MEMORY_SPACE (6 << 29)
101 #define CHCR_SSA_16BIT_ATTRIBUTE_MEMORY_SPACE (7 << 29)
102 #define CHCR_STC 0x10000000 /* Source Address Wait Control Select */
103 #define CHCR_DSA_MASK 0x0e000000 /* Destination Address Space Attribute Specification */
104 #define CHCR_DSA_RESERVED (0 << 25)
105 #define CHCR_DSA_DYNAMIC_BUS_SIZING (1 << 25)
106 #define CHCR_DSA_8BIT_IO_SPACE (2 << 25)
107 #define CHCR_DSA_16BIT_IO_SPACE (3 << 25)
108 #define CHCR_DSA_8BIT_COMMON_MEMORY_SPACE (4 << 25)
109 #define CHCR_DSA_16BIT_COMMON_MEMORY_SPACE (5 << 25)
110 #define CHCR_DSA_8BIT_ATTRIBUTE_MEMORY_SPACE (6 << 25)
111 #define CHCR_DSA_16BIT_ATTRIBUTE_MEMORY_SPACE (7 << 25)
112 #define CHCR_DTC 0x01000000 /* Destination Address Wait Control Select */
113 #define CHCR_DS 0x00080000 /* DREQ Select */
114 #define CHCR_RL 0x00040000 /* Request Check Level */
115 #define CHCR_AM 0x00020000 /* Acknowledge Mode */
116 #define CHCR_AL 0x00010000 /* Acknowledge Level */
117 #define CHCR_DM 0x0000c000 /* Destination Address Mode 1 and 0 */
118 #define CHCR_DM_FIXED (0 << 14) /* Destination Address Fixed */
119 #define CHCR_DM_INCREMENTED (1 << 14) /* Destination Address Incremented */
120 #define CHCR_DM_DECREMENTED (2 << 14) /* Destination Address Decremented */
121 #define CHCR_SM 0x00003000 /* Source Address Mode 1 and 0 */
122 #define CHCR_SM_FIXED (0 << 12) /* Source Address Fixed */
123 #define CHCR_SM_INCREMENTED (1 << 12) /* Source Address Incremented */
124 #define CHCR_SM_DECREMENTED (2 << 12) /* Source Address Decremented */
125 #define CHCR_RS 0x00000f00 /* Resource Select */
126 #define CHCR_TM 0x00000080 /* Transmit Mode (0=cycle steal, 1=burst) */
127 #define CHCR_TS 0x00000070 /* Transmit Size */
128 #define CHCR_TS_8BYTE (0 << 4)
129 #define CHCR_TS_1BYTE (1 << 4)
130 #define CHCR_TS_2BYTE (2 << 4)
131 #define CHCR_TS_4BYTE (3 << 4)
132 #define CHCR_TS_32BYTE (4 << 4)
133 #define CHCR_CHSET 0x00000008 /* Channel Setting */
134 #define CHCR_IE 0x00000004 /* Interrupt Enable */
135 #define CHCR_TE 0x00000002 /* Transfer End */
136 #define CHCR_TD 0x00000001 /* DMAC Enable */
137 
138 #endif /* SH4_DMACREG_H */

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