ps2_dmacreg.h Source File

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ps2_dmacreg.h
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1 #ifndef PS2_DMACREG_H
2 #define PS2_DMACREG_H
3 
4 /* gxemul: MIPS_PHYS_TO_KSEG1 has been changed to PS2_PHYS_TO_KSEG1. */
5 #define PS2_PHYS_TO_KSEG1(x) (x - 0x10008000)
6 
7 /* $NetBSD: dmacreg.h,v 1.1 2001/10/16 15:38:36 uch Exp $ */
8 
9 /*-
10  * Copyright (c) 2001 The NetBSD Foundation, Inc.
11  * All rights reserved.
12  *
13  * This code is derived from software contributed to The NetBSD Foundation
14  * by UCHIYAMA Yasushi.
15  *
16  * Redistribution and use in source and binary forms, with or without
17  * modification, are permitted provided that the following conditions
18  * are met:
19  * 1. Redistributions of source code must retain the above copyright
20  * notice, this list of conditions and the following disclaimer.
21  * 2. Redistributions in binary form must reproduce the above copyright
22  * notice, this list of conditions and the following disclaimer in the
23  * documentation and/or other materials provided with the distribution.
24  * 3. All advertising materials mentioning features or use of this software
25  * must display the following acknowledgement:
26  * This product includes software developed by the NetBSD
27  * Foundation, Inc. and its contributors.
28  * 4. Neither the name of The NetBSD Foundation nor the names of its
29  * contributors may be used to endorse or promote products derived
30  * from this software without specific prior written permission.
31  *
32  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
33  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
34  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
35  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
36  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
37  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
38  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
39  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
40  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
41  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
42  * POSSIBILITY OF SUCH DAMAGE.
43  */
44 
45 typedef uint64_t dmatag_t;
46 
47 #define DMAC_BLOCK_SIZE 16
48 #define DMAC_SLICE_SIZE 128
49 #define DMAC_TRANSFER_QWCMAX 0xffff
50 
51 /* all register length are 32bit */
52 #define DMAC_REGBASE PS2_PHYS_TO_KSEG1(0x10008000)
53 #define DMAC_REGSIZE 0x00010000
54 
55 /*
56  * DMAC common registers.
57  */
58 #define D_CTRL_REG PS2_PHYS_TO_KSEG1(0x1000e000) /* DMA control */
59 #define D_STAT_REG PS2_PHYS_TO_KSEG1(0x1000e010) /* interrupt status */
60 #define D_PCR_REG PS2_PHYS_TO_KSEG1(0x1000e020) /* priority control */
61 #define D_SQWC_REG PS2_PHYS_TO_KSEG1(0x1000e030) /* interleave size */
62 #define D_RBOR_REG PS2_PHYS_TO_KSEG1(0x1000e040) /* ring buffer addr */
63 #define D_RBSR_REG PS2_PHYS_TO_KSEG1(0x1000e050) /* ring buffer size */
64 #define D_STADR_REG PS2_PHYS_TO_KSEG1(0x1000e060) /* stall address */
65 #define D_ENABLER_REG PS2_PHYS_TO_KSEG1(0x1000f520) /* DMA enable (r) */
66 #define D_ENABLEW_REG PS2_PHYS_TO_KSEG1(0x1000f590) /* DMA enable (w) */
67 
68 /*
69  * Channel registers. (10ch)
70  */
71 #define DMA_CH_VIF0 0 /* to (priority 0) */
72 #define DMA_CH_VIF1 1 /* both */
73 #define DMA_CH_GIF 2 /* to */
74 #define DMA_CH_FROMIPU 3
75 #define DMA_CH_TOIPU 4
76 #define DMA_CH_SIF0 5 /* from */
77 #define DMA_CH_SIF1 6 /* to */
78 #define DMA_CH_SIF2 7 /* both (priority 1) */
79 #define DMA_CH_FROMSPR 8 /* burst channel */
80 #define DMA_CH_TOSPR 9 /* burst channel */
81 #define DMA_CH_VALID(x) (((x) >= 0) && ((x) <= 9))
82 
83 #define D_CHCR_OFS 0x00
84 #define D_MADR_OFS 0x10
85 #define D_QWC_OFS 0x20
86 #define D_TADR_OFS 0x30
87 #define D_ASR0_OFS 0x40
88 #define D_ASR1_OFS 0x50
89 #define D_SADR_OFS 0x80
90 
91 #define D0_REGBASE PS2_PHYS_TO_KSEG1(0x10008000)
92 #define D1_REGBASE PS2_PHYS_TO_KSEG1(0x10009000)
93 #define D2_REGBASE PS2_PHYS_TO_KSEG1(0x1000a000)
94 #define D3_REGBASE PS2_PHYS_TO_KSEG1(0x1000b000)
95 #define D4_REGBASE PS2_PHYS_TO_KSEG1(0x1000b400)
96 #define D5_REGBASE PS2_PHYS_TO_KSEG1(0x1000c000)
97 #define D6_REGBASE PS2_PHYS_TO_KSEG1(0x1000c400)
98 #define D7_REGBASE PS2_PHYS_TO_KSEG1(0x1000c800)
99 #define D8_REGBASE PS2_PHYS_TO_KSEG1(0x1000d000)
100 #define D9_REGBASE PS2_PHYS_TO_KSEG1(0x1000d400)
101 
102 #define D_CHCR_REG(base) (base)
103 #define D_MADR_REG(base) (base + D_MADR_OFS)
104 #define D_QWC_REG(base) (base + D_QWC_OFS)
105 #define D_TADR_REG(base) (base + D_TADR_OFS)
106 #define D_ASR0_REG(base) (base + D_ASR0_OFS)
107 #define D_ASR1_REG(base) (base + D_ASR1_OFS)
108 #define D_SADR_REG(base) (base + D_SADR_OFS)
109 
110 #define D0_CHCR_REG PS2_PHYS_TO_KSEG1(0x10008000)
111 #define D0_MADR_REG PS2_PHYS_TO_KSEG1(0x10008010)
112 #define D0_QWC_REG PS2_PHYS_TO_KSEG1(0x10008020)
113 #define D0_TADR_REG PS2_PHYS_TO_KSEG1(0x10008030)
114 #define D0_ASR0_REG PS2_PHYS_TO_KSEG1(0x10008040)
115 #define D0_ASR1_REG PS2_PHYS_TO_KSEG1(0x10008050)
116 
117 #define D1_CHCR_REG PS2_PHYS_TO_KSEG1(0x10009000)
118 #define D1_MADR_REG PS2_PHYS_TO_KSEG1(0x10009010)
119 #define D1_QWC_REG PS2_PHYS_TO_KSEG1(0x10009020)
120 #define D1_TADR_REG PS2_PHYS_TO_KSEG1(0x10009030)
121 #define D1_ASR0_REG PS2_PHYS_TO_KSEG1(0x10009040)
122 #define D1_ASR1_REG PS2_PHYS_TO_KSEG1(0x10009050)
123 
124 #define D2_CHCR_REG PS2_PHYS_TO_KSEG1(0x1000a000)
125 #define D2_MADR_REG PS2_PHYS_TO_KSEG1(0x1000a010)
126 #define D2_QWC_REG PS2_PHYS_TO_KSEG1(0x1000a020)
127 #define D2_TADR_REG PS2_PHYS_TO_KSEG1(0x1000a030)
128 #define D2_ASR0_REG PS2_PHYS_TO_KSEG1(0x1000a040)
129 #define D2_ASR1_REG PS2_PHYS_TO_KSEG1(0x1000a050)
130 
131 #define D3_CHCR_REG PS2_PHYS_TO_KSEG1(0x1000b000)
132 #define D3_MADR_REG PS2_PHYS_TO_KSEG1(0x1000b010)
133 #define D3_QWC_REG PS2_PHYS_TO_KSEG1(0x1000b020)
134 
135 #define D4_CHCR_REG PS2_PHYS_TO_KSEG1(0x1000b400)
136 #define D4_MADR_REG PS2_PHYS_TO_KSEG1(0x1000b410)
137 #define D4_QWC_REG PS2_PHYS_TO_KSEG1(0x1000b420)
138 #define D4_TADR_REG PS2_PHYS_TO_KSEG1(0x1000b430)
139 
140 #define D5_CHCR_REG PS2_PHYS_TO_KSEG1(0x1000c000)
141 #define D5_MADR_REG PS2_PHYS_TO_KSEG1(0x1000c010)
142 #define D5_QWC_REG PS2_PHYS_TO_KSEG1(0x1000c020)
143 
144 #define D6_CHCR_REG PS2_PHYS_TO_KSEG1(0x1000c400)
145 #define D6_MADR_REG PS2_PHYS_TO_KSEG1(0x1000c410)
146 #define D6_QWC_REG PS2_PHYS_TO_KSEG1(0x1000c420)
147 #define D6_TADR_REG PS2_PHYS_TO_KSEG1(0x1000c430)
148 
149 #define D7_CHCR_REG PS2_PHYS_TO_KSEG1(0x1000c800)
150 #define D7_MADR_REG PS2_PHYS_TO_KSEG1(0x1000c810)
151 #define D7_QWC_REG PS2_PHYS_TO_KSEG1(0x1000c820)
152 
153 #define D8_CHCR_REG PS2_PHYS_TO_KSEG1(0x1000d000)
154 #define D8_MADR_REG PS2_PHYS_TO_KSEG1(0x1000d010)
155 #define D8_QWC_REG PS2_PHYS_TO_KSEG1(0x1000d020)
156 #define D8_SADR_REG PS2_PHYS_TO_KSEG1(0x1000d080)
157 
158 #define D9_CHCR_REG PS2_PHYS_TO_KSEG1(0x1000d400)
159 #define D9_MADR_REG PS2_PHYS_TO_KSEG1(0x1000d410)
160 #define D9_QWC_REG PS2_PHYS_TO_KSEG1(0x1000d420)
161 #define D9_TADR_REG PS2_PHYS_TO_KSEG1(0x1000d430)
162 #define D9_SADR_REG PS2_PHYS_TO_KSEG1(0x1000d480)
163 
164 /*
165  * DMA control
166  */
167 #define D_CTRL_DMAE 0x00000001 /* all DMA enable/disable */
168 #define D_CTRL_RELE 0x00000002 /* Cycle stealing on/off */
169 /* Memory FIFO drain control */
170 #define D_CTRL_MFD_MASK 0x3
171 #define D_CTRL_MFD_SHIFT 2
172 #define D_CTRL_MFD(x) \
173  (((x) >> D_CTRL_MFD_SHIFT) & D_CTRL_MFD_MASK)
174 #define D_CTRL_MFD_CLR(x) \
175  ((x) & ~(D_CTRL_MFD_MASK << D_CTRL_MFD_SHIFT))
176 #define D_CTRL_MFD_SET(x, val) \
177  ((x) | (((val) << D_CTRL_MFD_SHIFT) & \
178  (D_CTRL_MFD_MASK << D_CTRL_MFD_SHIFT)))
179 #define D_CTRL_MFD_DISABLE 0
180 #define D_CTRL_MFD_VIF1 2
181 #define D_CTRL_MFD_GIF 3
182 
183 /* Stall control source channel */
184 #define D_CTRL_STS_MASK 0x3
185 #define D_CTRL_STS_SHIFT 4
186 #define D_CTRL_STS(x) \
187  (((x) >> D_CTRL_STS_SHIFT) & D_CTRL_STS_MASK)
188 #define D_CTRL_STS_CLR(x) \
189  ((x) & ~(D_CTRL_STS_MASK << D_CTRL_STS_SHIFT))
190 #define D_CTRL_STS_SET(x, val) \
191  ((x) | (((val) << D_CTRL_STS_SHIFT) & \
192  (D_CTRL_STS_MASK << D_CTRL_STS_SHIFT)))
193 #define D_CTRL_STS_NONE 0
194 #define D_CTRL_STS_SIF0 1
195 #define D_CTRL_STS_FROMSPR 2
196 #define D_CTRL_STS_FROMIPU 3
197 
198 /* Stall control drain channel */
199 #define D_CTRL_STD_MASK 0x3
200 #define D_CTRL_STD_SHIFT 6
201 #define D_CTRL_STD(x) \
202  (((x) >> D_CTRL_STD_SHIFT) & D_CTRL_STD_MASK)
203 #define D_CTRL_STD_CLR(x) \
204  ((x) & ~(D_CTRL_STD_MASK << D_CTRL_STD_SHIFT))
205 #define D_CTRL_STD_SET(x, val) \
206  ((x) | (((val) << D_CTRL_STD_SHIFT) & \
207  (D_CTRL_STD_MASK << D_CTRL_STD_SHIFT)))
208 #define D_CTRL_STD_NONE 0
209 #define D_CTRL_STD_VIF1 1
210 #define D_CTRL_STD_GIF 2
211 #define D_CTRL_STD_SIF1 3
212 
213 /*
214  * Release cycle
215  * for burst channel Cycle steanling on mode only.
216  */
217 #define D_CTRL_RCYC_MASK 0x7
218 #define D_CTRL_RCYC_SHIFT 8
219 #define D_CTRL_RCYC(x) \
220  (((x) >> D_CTRL_RCYC_SHIFT) & D_CTRL_RCYC_MASK)
221 #define D_CTRL_RCYC_CLR(x) \
222  ((x) & ~(D_CTRL_RCYC_MASK << D_CTRL_RCYC_SHIFT))
223 #define D_CTRL_RCYC_SET(x, val) \
224  ((x) | (((val) << D_CTRL_RCYC_SHIFT) & \
225  (D_CTRL_RCYC_MASK << D_CTRL_RCYC_SHIFT)))
226 #define D_CTRL_RCYC_CYCLE(x) (8 << (x))
227 
228 /*
229  * Interrupt status register (write clear/invert)
230  * DMAC interrupt line connected to MIPS HwINT1
231  */
232 /* MFIFO empty interrupt enable */
233 #define D_STAT_MEIM 0x40000000
234 /* DMA stall interrupt enable */
235 #define D_STAT_SIM 0x20000000
236 /* Channel interrupt enable */
237 #define D_STAT_CIM_MASK 0x3ff
238 #define D_STAT_CIM_SHIFT 16
239 #define D_STAT_CIM(x) (((x) >> D_STAT_CIM_SHIFT) & D_STAT_CIM_MASK)
240 #define D_STAT_CIM_BIT(x) ((1 << (x)) << D_STAT_CIM_SHIFT)
241 #define D_STAT_CIM9 0x02000000
242 #define D_STAT_CIM8 0x01000000
243 #define D_STAT_CIM7 0x00800000
244 #define D_STAT_CIM6 0x00400000
245 #define D_STAT_CIM5 0x00200000
246 #define D_STAT_CIM4 0x00100000
247 #define D_STAT_CIM3 0x00080000
248 #define D_STAT_CIM2 0x00040000
249 #define D_STAT_CIM1 0x00020000
250 #define D_STAT_CIM0 0x00010000
251 /* BUSERR interrupt status */
252 #define D_STAT_BEIS 0x00008000
253 /* MFIFO empty interrupt status */
254 #define D_STAT_MEIS 0x00004000
255 /* DMA stall interrupt status */
256 #define D_STAT_SIS 0x00002000
257 /* Channel interrupt status */
258 #define D_STAT_CIS_MASK 0x3ff
259 #define D_STAT_CIS_SHIFT 0
260 #define D_STAT_CIS_BIT(x) (1 << (x))
261 #define D_STAT_CIS9 0x00000200
262 #define D_STAT_CIS8 0x00000100
263 #define D_STAT_CIS7 0x00000080
264 #define D_STAT_CIS6 0x00000040
265 #define D_STAT_CIS5 0x00000020
266 #define D_STAT_CIS4 0x00000010
267 #define D_STAT_CIS3 0x00000008
268 #define D_STAT_CIS2 0x00000004
269 #define D_STAT_CIS1 0x00000002
270 #define D_STAT_CIS0 0x00000001
271 
272 /*
273  * Priority control register.
274  */
275 /* Priority control enable */
276 #define D_PCR_PCE 0x80000000
277 /* Channel DMA enable (packet priority control enable) */
278 #define D_PCR_CDE_MASK 0x3ff
279 #define D_PCR_CDE_SHIFT 16
280 #define D_PCR_CDE(x) \
281  (((x) >> D_PCR_CDE_SHIFT) & D_PCR_CDE_MASK)
282 #define D_PCR_CDE_CLR(x) \
283  ((x) & ~(D_PCR_CDE_MASK << D_PCR_CDE_SHIFT))
284 #define D_PCR_CDE_SET(x, val) \
285  ((x) | (((val) << D_PCR_CDE_SHIFT) & \
286  (D_PCR_CDE_MASK << D_PCR_CDE_SHIFT)))
287 #define D_PCR_CDE9 0x02000000
288 #define D_PCR_CDE8 0x01000000
289 #define D_PCR_CDE7 0x00800000
290 #define D_PCR_CDE6 0x00400000
291 #define D_PCR_CDE5 0x00200000
292 #define D_PCR_CDE4 0x00100000
293 #define D_PCR_CDE3 0x00080000
294 #define D_PCR_CDE2 0x00040000
295 #define D_PCR_CDE1 0x00020000
296 #define D_PCR_CDE0 0x00010000
297 /* COP control (interrupt status connect to CPCOND[0] or not) */
298 #define D_PCR_CPC_MASK 0x3ff
299 #define D_PCR_CPC_SHIFT 0
300 #define D_PCR_CPC(x) ((x) & D_PCR_CPC_MASK)
301 #define D_PCR_CPC_CLR(x) ((x) & ~D_PCR_CPC_MASK)
302 #define D_PCR_CPC_SET(x, val) ((x) | ((val) & D_PCR_CPC_MASK))
303 #define D_PCR_CPC_BIT(x) (1 << (x))
304 #define D_PCR_CPC9 0x00000200
305 #define D_PCR_CPC8 0x00000100
306 #define D_PCR_CPC7 0x00000080
307 #define D_PCR_CPC6 0x00000040
308 #define D_PCR_CPC5 0x00000020
309 #define D_PCR_CPC4 0x00000010
310 #define D_PCR_CPC3 0x00000008
311 #define D_PCR_CPC2 0x00000004
312 #define D_PCR_CPC1 0x00000002
313 #define D_PCR_CPC0 0x00000001
314 
315 /*
316  * Interleave size register
317  */
318 /* Transfer quadword counter */
319 #define D_SQWC_TQWC_MASK 0xff
320 #define D_SQWC_TQWC_SHIFT 16
321 #define D_SQWC_TQWC(x) \
322  (((x) >> D_SQWC_TQWC_SHIFT) & D_SQWC_TQWC_MASK)
323 #define D_SQWC_TQWC_CLR(x) \
324  ((x) & ~(D_SQWC_TQWC_MASK << D_SQWC_TQWC_SHIFT))
325 #define D_SQWC_TQWC_SET(x, val) \
326  ((x) | (((val) << D_SQWC_TQWC_SHIFT) & \
327  (D_SQWC_TQWC_MASK << D_SQWC_TQWC_SHIFT)))
328 /* Skip quadword counter */
329 #define D_SQWC_SQWC_MASK 0xff
330 #define D_SQWC_SQWC_SHIFT 0
331 #define D_SQWC_SQWC(x) \
332  (((x) >> D_SQWC_SQWC_SHIFT) & D_SQWC_SQWC_MASK)
333 #define D_SQWC_SQWC_CLR(x) \
334  ((x) & ~(D_SQWC_SQWC_MASK << D_SQWC_SQWC_SHIFT))
335 #define D_SQWC_SQWC_SET(x, val) \
336  ((x) | (((val) << D_SQWC_SQWC_SHIFT) & \
337  (D_SQWC_SQWC_MASK << D_SQWC_SQWC_SHIFT)))
338 
339 /*
340  * Ring buffer address register
341  * 16byte alignment address [30:4]
342  */
343 
344 /*
345  * Ring buffer size register
346  * must be 2 ** n qword. [30:4]
347  */
348 
349 /*
350  * Stall address register
351  * [30:0] (qword alignment)
352  */
353 
354 /*
355  * DMA suspend register
356  */
357 #define D_ENABLE_SUSPEND 0x00010000
358 
359 
360 /*
361  * Channel specific register.
362  */
363 
364 /* CHANNEL CONTROL REGISTER */
365 /* upper 16bit of DMA tag last read. */
366 #define D_CHCR_TAG_MASK 0xff
367 #define D_CHCR_TAG_SHIFT 16
368 #define D_CHCR_TAG(x) \
369  (((x) >> D_CHCR_TAG_SHIFT) & D_CHCR_TAG_MASK)
370 #define D_CHCR_TAG_CLR(x) \
371  ((x) & ~(D_CHCR_TAG_MASK << D_CHCR_TAG_SHIFT))
372 #define D_CHCR_TAG_SET(x, val) \
373  ((x) | (((val) << D_CHCR_TAG_SHIFT) & \
374  (D_CHCR_TAG_MASK << D_CHCR_TAG_SHIFT)))
375 /* DMA start */
376 #define D_CHCR_STR 0x00000100
377 /* Tag interrupt enable (IRQ bit of DMAtag) */
378 #define D_CHCR_TIE 0x00000080
379 /* Tag transfer enable (Source chain mode only) */
380 #define D_CHCR_TTE 0x00000040
381 /* Address stack pointer */
382 #define D_CHCR_ASP_MASK 0x3
383 #define D_CHCR_ASP_SHIFT 4
384 #define D_CHCR_ASP(x) \
385  (((x) >> D_CHCR_ASP_SHIFT) & D_CHCR_ASP_MASK)
386 #define D_CHCR_ASP_CLR(x) \
387  ((x) & ~(D_CHCR_ASP_MASK << D_CHCR_ASP_SHIFT))
388 #define D_CHCR_ASP_SET(x, val) \
389  ((x) | (((val) << D_CHCR_ASP_SHIFT) & \
390  (D_CHCR_ASP_MASK << D_CHCR_ASP_SHIFT)))
391 #define D_CHCR_ASP_PUSHED_NONE 0
392 #define D_CHCR_ASP_PUSHED_1 1
393 #define D_CHCR_ASP_PUSHED_2 2
394 /* Logical transfer mode */
395 #define D_CHCR_MOD_MASK 0x3
396 #define D_CHCR_MOD_SHIFT 2
397 #define D_CHCR_MOD(x) \
398  (((x) >> D_CHCR_MOD_SHIFT) & D_CHCR_MOD_MASK)
399 #define D_CHCR_MOD_CLR(x) \
400  ((x) & ~(D_CHCR_MOD_MASK << D_CHCR_MOD_SHIFT))
401 #define D_CHCR_MOD_SET(x, val) \
402  ((x) | (((val) << D_CHCR_MOD_SHIFT) & \
403  (D_CHCR_MOD_MASK << D_CHCR_MOD_SHIFT)))
404 #define D_CHCR_MOD_NORMAL 0
405 #define D_CHCR_MOD_CHAIN 1
406 #define D_CHCR_MOD_INTERLEAVE 2
407 /*
408  * DMA transfer direction (1 ... from Memory, 0 ... to Memory)
409  * (VIF1, SIF2 only. i.e. `both'-direction channel requires this)
410  */
411 #define D_CHCR_DIR 0x00000001
412 
413 /*
414  * TRANSFER ADDRESS REGISTER (D-RAM address)
415  * 16 byte alignment. In FROMSPR, TOSPR channel, D_MADR_SPR always 0
416  */
417 #define D_MADR_SPR 0x80000000
418 
419 /*
420  * TAG ADDRESS REGISTER (next tag address)
421  * 16 byte alignment.
422  */
423 #define D_TADR_SPR 0x80000000
424 
425 /*
426  * TAG ADDRESS STACK REGISTER (2 stage)
427  * 16 byte alignment.
428  */
429 #define D_ASR_SPR 0x80000000
430 
431 /*
432  * SPR TRANSFER ADDRESS REGISTER (SPR address)
433  * 16 byte alignment. FROMSPR, TOSPR only.
434  */
435 #define D_SADR_MASK 0x3fff
436 #define D_SADR_SHIFT 0
437 #define D_SADR(x) \
438  ((uint32_t)(x) & D_SADR_MASK)
439 /*
440  * TRANSFER SIZE REGISTER
441  * min 16 byte to max 1 Mbyte.
442  */
443 #define D_QWC_MASK 0xffff
444 #define D_QWC_SHIFT 0
445 #define D_QWC(x) (((x) >> D_QWC_SHIFT) & D_QWC_MASK)
446 #define D_QWC_CLR(x) ((x) & ~(D_QWC_MASK << D_QWC_SHIFT))
447 #define D_QWC_SET(x, val) \
448  ((x) | (((val) << D_QWC_SHIFT) & D_QWC_MASK << D_QWC_SHIFT))
449 
450 /*
451  * Source/Destination Chain Tag definition.
452  * SC ... VIF0, VIF1, GIF, toIPU, SIF1, toSPR
453  * DC ... SIF0, fromSPR
454  */
455 /*
456  * DMA address
457  * At least, 16byte align.
458  * but 64byte align is recommended. because EE D-cash line size is 64byte.
459  * To gain maximum DMA speed, use 128 byte align.
460  */
461 #define DMATAG_ADDR_MASK 0xffffffff
462 #define DMATAG_ADDR_SHIFT 32
463 #define DMATAG_ADDR(x) \
464  ((uint32_t)(((x) >> DMATAG_ADDR_SHIFT) & DMATAG_ADDR_MASK))
465 #define DMATAG_ADDR_SET(x, val) \
466  ((dmatag_t)(x) | (((dmatag_t)(val)) << DMATAG_ADDR_SHIFT))
467 
468 #define DMATAG_ADDR32_INVALID(x) ((x) & 0xf) /* 16byte alignment */
469 
470 /*
471  * DMA controller command
472  */
473 #define DMATAG_CMD_MASK 0xffffffff
474 #define DMATAG_CMD_SHIFT 0
475 #define DMATAG_CMD(x) \
476  ((uint32_t)((x) & DMATAG_CMD_MASK))
477 
478 #define DMATAG_CMD_IRQ 0x80000000
479 
480 #define DMATAG_CMD_ID_MASK 0x7
481 #define DMATAG_CMD_ID_SHIFT 28
482 #define DMATAG_CMD_ID(x) \
483  (((x) >> DMATAG_CMD_ID_SHIFT) & DMATAG_CMD_ID_MASK)
484 #define DMATAG_CMD_ID_CLR(x) \
485  ((x) & ~(DMATAG_CMD_ID_MASK << DMATAG_CMD_ID_SHIFT))
486 #define DMATAG_CMD_ID_SET(x, val) \
487  ((x) | (((val) << DMATAG_CMD_ID_SHIFT) & \
488  (DMATAG_CMD_ID_MASK << DMATAG_CMD_ID_SHIFT)))
489 #define DMATAG_CMD_SCID_REFE 0
490 #define DMATAG_CMD_SCID_CNT 1
491 #define DMATAG_CMD_SCID_NEXT 2
492 #define DMATAG_CMD_SCID_REF 3
493 #define DMATAG_CMD_SCID_REFS 4 /* VIF1, GIF, SIF1 only */
494 #define DMATAG_CMD_SCID_CALL 5 /* VIF0, VIF1, GIF only */
495 #define DMATAG_CMD_SCID_RET 6 /* VIF0, VIF1, GIF only */
496 #define DMATAG_CMD_SCID_END 7
497 
498 #define DMATAG_CMD_DCID_CNTS 0 /* SIF0, fromSPR only */
499 #define DMATAG_CMD_DCID_CNT 1
500 #define DMATAG_CMD_DCID_END 7
501 
502 #define DMATAG_CMD_PCE_MASK 0x3
503 #define DMATAG_CMD_PCE_SHIFT 26
504 #define DMATAG_CMD_PCE(x) \
505  (((x) >> DMATAG_CMD_PCE_SHIFT) & DMATAG_CMD_PCE_MASK)
506 #define DMATAG_CMD_PCE_CLR(x) \
507  ((x) & ~(DMATAG_CMD_PCE_MASK << DMATAG_CMD_PCE_SHIFT))
508 #define DMATAG_CMD_PCE_SET(x, val) \
509  ((x) | (((val) << DMATAG_CMD_PCE_SHIFT) & \
510  (DMATAG_CMD_PCE_MASK << DMATAG_CMD_PCE_SHIFT)))
511 #define DMATAG_CMD_PCE_NONE 0
512 #define DMATAG_CMD_PCE_DISABLE 2
513 #define DMATAG_CMD_PCE_ENABLE 3
514 
515 #define DMATAG_CMD_QWC_MASK 0xffff
516 #define DMATAG_CMD_QWC_SHIFT 0
517 #define DMATAG_CMD_QWC(x) \
518  (((x) >> DMATAG_CMD_QWC_SHIFT) & DMATAG_CMD_QWC_MASK)
519 #define DMATAG_CMD_QWC_CLR(x) \
520  ((x) & ~(DMATAG_CMD_QWC_MASK << DMATAG_CMD_QWC_SHIFT))
521 #define DMATAG_CMD_QWC_SET(x, val) \
522  ((x) | (((val) << DMATAG_CMD_QWC_SHIFT) & \
523  (DMATAG_CMD_QWC_MASK << DMATAG_CMD_QWC_SHIFT)))
524 
525 #endif /* PS2_DMACREG_H */
uint64_t dmatag_t
Definition: ps2_dmacreg.h:45

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