cpu_arm_coproc.cc Source File

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cpu_arm_coproc.cc
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1 /*
2  * Copyright (C) 2005-2009 Anders Gavare. All rights reserved.
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions are met:
6  *
7  * 1. Redistributions of source code must retain the above copyright
8  * notice, this list of conditions and the following disclaimer.
9  * 2. Redistributions in binary form must reproduce the above copyright
10  * notice, this list of conditions and the following disclaimer in the
11  * documentation and/or other materials provided with the distribution.
12  * 3. The name of the author may not be used to endorse or promote products
13  * derived from this software without specific prior written permission.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25  * SUCH DAMAGE.
26  *
27  *
28  * ARM coprocessor emulation.
29  */
30 
31 #include <stdio.h>
32 #include <stdlib.h>
33 #include <string.h>
34 #include <unistd.h>
35 #include <ctype.h>
36 
37 #include "cpu.h"
38 #include "machine.h"
39 #include "misc.h"
40 #include "symbol.h"
41 
42 #include "thirdparty/i80321reg.h"
43 
44 
45 /*
46  * arm_coproc_15():
47  *
48  * The system control coprocessor.
49  */
50 void arm_coproc_15(struct cpu *cpu, int opcode1, int opcode2, int l_bit,
51  int crn, int crm, int rd)
52 {
53  uint32_t old_control;
54 
55  /* Some sanity checks: */
56  if (opcode1 != 0) {
57  fatal("arm_coproc_15: opcode1 = %i, should be 0\n", opcode1);
58  exit(1);
59  }
60  if (rd == ARM_PC) {
61  fatal("arm_coproc_15: rd = PC\n");
62  exit(1);
63  }
64 
65  switch (crn) {
66 
67  case 0: /*
68  * Main ID register (and Cache Type register, on XScale)
69  *
70  * Writes are supposed to be ignored, according to Intel docs.
71  */
72  switch (opcode2) {
73  case 0: if (l_bit)
74  cpu->cd.arm.r[rd] = cpu->cd.arm.cpu_type.cpu_id;
75  else
76  fatal("[ arm_coproc_15: attempt to write "
77  "to the Main ID register? ]\n");
78  break;
79  case 1: if (l_bit)
80  cpu->cd.arm.r[rd] = cpu->cd.arm.cachetype;
81  else
82  fatal("[ arm_coproc_15: attempt to write "
83  "to the Cache Type register? ]\n");
84  break;
85  default:fatal("[ arm_coproc_15: TODO: cr0, opcode2=%i ]\n",
86  opcode2);
87  exit(1);
88  }
89  break;
90 
91  case 1: /* Control Register: */
92  if (l_bit) {
93  /* Load from the normal/aux control register: */
94  switch (opcode2) {
95  case 0: cpu->cd.arm.r[rd] = cpu->cd.arm.control;
96  break;
97  case 1: cpu->cd.arm.r[rd] = cpu->cd.arm.auxctrl;
98  break;
99  default:fatal("Unimplemented opcode2 = %i\n", opcode2);
100  fatal("(opcode1=%i crn=%i crm=%i rd=%i l=%i)\n",
101  opcode1, crn, crm, rd, l_bit);
102  exit(1);
103  }
104  return;
105  }
106 
107  if (opcode2 == 1) {
108  /* Write to auxctrl: */
109  old_control = cpu->cd.arm.auxctrl;
110  cpu->cd.arm.auxctrl = cpu->cd.arm.r[rd];
111  if ((old_control & ARM_AUXCTRL_MD) !=
112  (cpu->cd.arm.auxctrl & ARM_AUXCTRL_MD)) {
113  debug("[ setting the minidata cache attribute"
114  " to 0x%x ]\n", (cpu->cd.arm.auxctrl &
115  ARM_AUXCTRL_MD) >> ARM_AUXCTRL_MD_SHIFT);
116  }
117  if ((old_control & ARM_AUXCTRL_K) !=
118  (cpu->cd.arm.auxctrl & ARM_AUXCTRL_K)) {
119  debug("[ %s write buffer coalescing ]\n",
120  cpu->cd.arm.auxctrl & ARM_AUXCTRL_K?
121  "Disabling" : "Enabling");
122  }
123  return;
124  } else if (opcode2 != 0) {
125  fatal("Unimplemented write, opcode2 = %i\n", opcode2);
126  fatal("(opcode1=%i crn=%i crm=%i rd=%i l=%i)\n",
127  opcode1, crn, crm, rd, l_bit);
128  exit(1);
129  }
130 
131  /*
132  * Write to control: Check each bit individually:
133  */
134  old_control = cpu->cd.arm.control;
135  cpu->cd.arm.control = cpu->cd.arm.r[rd];
136  if ((old_control & ARM_CONTROL_MMU) !=
137  (cpu->cd.arm.control & ARM_CONTROL_MMU)) {
138  debug("[ %s the MMU ]\n", cpu->cd.arm.control &
139  ARM_CONTROL_MMU? "enabling" : "disabling");
140  cpu->translate_v2p =
141  cpu->cd.arm.control & ARM_CONTROL_MMU?
143  }
144  if ((old_control & ARM_CONTROL_ALIGN) !=
145  (cpu->cd.arm.control & ARM_CONTROL_ALIGN))
146  debug("[ %s alignment checks ]\n", cpu->cd.arm.control &
147  ARM_CONTROL_ALIGN? "enabling" : "disabling");
148  if ((old_control & ARM_CONTROL_CACHE) !=
149  (cpu->cd.arm.control & ARM_CONTROL_CACHE))
150  debug("[ %s the [data] cache ]\n", cpu->cd.arm.control &
151  ARM_CONTROL_CACHE? "enabling" : "disabling");
152  if ((old_control & ARM_CONTROL_WBUFFER) !=
153  (cpu->cd.arm.control & ARM_CONTROL_WBUFFER))
154  debug("[ %s the write buffer ]\n", cpu->cd.arm.control &
155  ARM_CONTROL_WBUFFER? "enabling" : "disabling");
156 
157  old_control &= ~ARM_CONTROL_BIG;
158  if (cpu->byte_order == EMUL_BIG_ENDIAN)
159  old_control |= ARM_CONTROL_BIG;
160 
161  if ((old_control & ARM_CONTROL_BIG) !=
162  (cpu->cd.arm.control & ARM_CONTROL_BIG)) {
163  fatal("ERROR: Trying to switch endianness. Not "
164  "supported yet.\n");
165  exit(1);
166  }
167  if ((old_control & ARM_CONTROL_ICACHE) !=
168  (cpu->cd.arm.control & ARM_CONTROL_ICACHE))
169  debug("[ %s the icache ]\n", cpu->cd.arm.control &
170  ARM_CONTROL_ICACHE? "enabling" : "disabling");
171  /* TODO: More bits. */
172  break;
173 
174  case 2: /* Translation Table Base register: */
175  /* NOTE: 16 KB aligned. */
176  if (l_bit)
177  cpu->cd.arm.r[rd] = cpu->cd.arm.ttb & 0xffffc000;
178  else {
179  cpu->cd.arm.ttb = cpu->cd.arm.r[rd];
180  if (cpu->cd.arm.ttb & 0x3fff)
181  fatal("[ WARNING! low bits of new TTB non-"
182  "zero? 0x%08x ]\n", cpu->cd.arm.ttb);
183  cpu->cd.arm.ttb &= 0xffffc000;
184  }
185  break;
186 
187  case 3: /* Domain Access Control Register: */
188  if (l_bit)
189  cpu->cd.arm.r[rd] = cpu->cd.arm.dacr;
190  else
191  cpu->cd.arm.dacr = cpu->cd.arm.r[rd];
192  break;
193 
194  case 5: /* Fault Status Register: */
195  /* Note: Only the lowest 8 bits are defined. */
196  if (l_bit)
197  cpu->cd.arm.r[rd] = cpu->cd.arm.fsr & 0xff;
198  else
199  cpu->cd.arm.fsr = cpu->cd.arm.r[rd] & 0xff;
200  break;
201 
202  case 6: /* Fault Address Register: */
203  if (l_bit)
204  cpu->cd.arm.r[rd] = cpu->cd.arm.far;
205  else
206  cpu->cd.arm.far = cpu->cd.arm.r[rd];
207  break;
208 
209  case 7: /* Cache functions: */
210  if (l_bit) {
211  fatal("[ arm_coproc_15: attempt to read cr7? ]\n");
212  return;
213  }
214  /* debug("[ arm_coproc_15: cache op: TODO ]\n"); */
215  /* TODO: */
216  break;
217 
218  case 8: /* TLB functions: */
219  if (l_bit) {
220  fatal("[ arm_coproc_15: attempt to read cr8? ]\n");
221  return;
222  }
223  /* fatal("[ arm_coproc_15: TLB: op2=%i crm=%i rd=0x%08x ]\n",
224  opcode2, crm, cpu->cd.arm.r[rd]); */
225  if (opcode2 == 0)
226  cpu->invalidate_translation_caches(cpu, 0,
228  else
230  cpu->cd.arm.r[rd], INVALIDATE_VADDR);
231  break;
232 
233  case 9: /* Cache lockdown: */
234  fatal("[ arm_coproc_15: cache lockdown: TODO ]\n");
235  /* TODO */
236  break;
237 
238  case 13:/* Process ID Register: */
239  if (opcode2 != 0)
240  fatal("[ arm_coproc_15: PID access, but opcode2 "
241  "= %i? (should be 0) ]\n", opcode2);
242  if (crm != 0)
243  fatal("[ arm_coproc_15: PID access, but crm "
244  "= %i? (should be 0) ]\n", crm);
245  if (l_bit)
246  cpu->cd.arm.r[rd] = cpu->cd.arm.pid;
247  else
248  cpu->cd.arm.pid = cpu->cd.arm.r[rd];
249  if (cpu->cd.arm.pid != 0) {
250  fatal("ARM TODO: pid!=0. Fast Context Switch"
251  " Extension not implemented yet\n");
252  exit(1);
253  }
254  break;
255 
256  /* case 14: */
257  /* Breakpoint registers on XScale (possibly others?) */
258  /* TODO */
259  /* break; */
260 
261  case 15:/* IMPLEMENTATION DEPENDENT! */
262  switch (crm) {
263  case 1: /*
264  * On XScale (and others? TODO), this is the
265  * CoProcessor Access Register. Note/TODO: This isn't
266  * really used throughout the rest of the code yet.
267  */
268  if (l_bit)
269  cpu->cd.arm.r[rd] = cpu->cd.arm.cpar;
270  else
271  cpu->cd.arm.cpar = cpu->cd.arm.r[rd];
272  break;
273  default:fatal("[ arm_coproc_15: TODO: IMPLEMENTATION "
274  "DEPENDENT! ]\n");
275  exit(1);
276  }
277  break;
278 
279  default:fatal("arm_coproc_15: unimplemented crn = %i\n", crn);
280  fatal("(opcode1=%i opcode2=%i crm=%i rd=%i l=%i)\n",
281  opcode1, opcode2, crm, rd, l_bit);
282  exit(1);
283  }
284 }
285 
286 
287 /*
288  * arm_coproc_i80321_6():
289  *
290  * Intel 80321 coprocessor 6.
291  */
292 void arm_coproc_i80321_6(struct cpu *cpu, int opcode1, int opcode2, int l_bit,
293  int crn, int crm, int rd)
294 {
295  switch (crm) {
296 
297  case 0: switch (crn) {
298  case 0: if (l_bit) {
299  cpu->cd.arm.r[rd] = cpu->cd.arm.i80321_inten;
300  fatal("TODO: XScale read from inten?\n");
301  exit(1);
302  } else
303  cpu->cd.arm.i80321_inten = cpu->cd.arm.r[rd];
304  break;
305  case 4: if (l_bit)
306  cpu->cd.arm.r[rd] = cpu->cd.arm.i80321_isteer;
307  else {
308  cpu->cd.arm.i80321_isteer = cpu->cd.arm.r[rd];
309  if (cpu->cd.arm.r[rd] != 0) {
310  fatal("ARM xscale interrupt steering"
311  " is not yet implemented\n");
312  exit(1);
313  }
314  }
315  break;
316  case 8: if (l_bit)
317  cpu->cd.arm.r[rd] = cpu->cd.arm.i80321_isrc;
318  else {
319  cpu->cd.arm.i80321_isrc = cpu->cd.arm.r[rd];
320  fatal("TODO: XScale int ack?\n");
321  exit(1);
322  }
323  break;
324  default:goto unknown;
325  }
326  break;
327 
328  case 1: /* fatal("TIMER opcode1=%i opcode2=%i crn="
329  "%i crm=%i rd=%i l=%i)\n", opcode1, opcode2, crn, crm, rd, l_bit); */
330 
331  switch (crn) {
332  case 0: /* tmr0: */
333  if (l_bit)
334  cpu->cd.arm.r[rd] = cpu->cd.arm.tmr0;
335  else
336  cpu->cd.arm.tmr0 = cpu->cd.arm.r[rd];
337  break;
338  case 1: /* tmr1: */
339  if (l_bit)
340  cpu->cd.arm.r[rd] = cpu->cd.arm.tmr1;
341  else
342  cpu->cd.arm.tmr1 = cpu->cd.arm.r[rd];
343  break;
344  case 2: /* tcr0: */
345  if (l_bit) {
346  /* NOTE/TODO: Ugly hack: timer increment */
347  cpu->cd.arm.tcr0 ++;
348  cpu->cd.arm.r[rd] = cpu->cd.arm.tcr0;
349  } else {
350  cpu->cd.arm.tcr0 = cpu->cd.arm.r[rd];
351  }
352  break;
353  case 3: /* tcr1: */
354  if (l_bit) {
355  /* NOTE/TODO: Ugly hack: timer increment */
356  cpu->cd.arm.tcr1 ++;
357  cpu->cd.arm.r[rd] = cpu->cd.arm.tcr1;
358  } else {
359  cpu->cd.arm.tcr1 = cpu->cd.arm.r[rd];
360  }
361  break;
362  case 4: /* trr0: */
363  if (l_bit)
364  cpu->cd.arm.r[rd] = cpu->cd.arm.trr0;
365  else
366  cpu->cd.arm.trr0 = cpu->cd.arm.r[rd];
367  break;
368  case 5: /* trr1: */
369  if (l_bit)
370  cpu->cd.arm.r[rd] = cpu->cd.arm.trr1;
371  else
372  cpu->cd.arm.trr1 = cpu->cd.arm.r[rd];
373  break;
374  case 6: /* tisr: */
375  if (l_bit)
376  cpu->cd.arm.r[rd] = cpu->cd.arm.tisr;
377  else {
378  /* Writing clears interrupts: */
379  cpu->cd.arm.tisr &= ~cpu->cd.arm.r[rd];
380 
381  if (!(cpu->cd.arm.tisr & TISR_TMR0))
383  cpu->cd.arm.tmr0_irq);
384  if (!(cpu->cd.arm.tisr & TISR_TMR1))
386  cpu->cd.arm.tmr1_irq);
387  }
388  break;
389  case 7: /* wdtcr: */
390  if (l_bit)
391  cpu->cd.arm.r[rd] = cpu->cd.arm.wdtcr;
392  else
393  cpu->cd.arm.wdtcr = cpu->cd.arm.r[rd];
394  break;
395  default:goto unknown;
396  }
397  break;
398 
399  default:goto unknown;
400  }
401 
402  return;
403 
404 unknown:
405  fatal("arm_coproc_i80321_6: unimplemented opcode1=%i opcode2=%i crn="
406  "%i crm=%i rd=%i l=%i)\n", opcode1, opcode2, crn, crm, rd, l_bit);
407  exit(1);
408 }
409 
410 
411 /*
412  * arm_coproc_xscale_14():
413  *
414  * XScale coprocessor 14, Performance Monitoring Unit.
415  */
416 void arm_coproc_xscale_14(struct cpu *cpu, int opcode1, int opcode2, int l_bit,
417  int crn, int crm, int rd)
418 {
419  if (opcode2 != 0) {
420  fatal("TODO: opcode2 = %i\n", opcode2);
421  goto unknown;
422  }
423 
424  switch (crm) {
425 
426  case 0: switch (crn) {
427  case 0: if (l_bit)
428  cpu->cd.arm.r[rd] = cpu->cd.arm.xsc1_pmnc;
429  else
430  cpu->cd.arm.xsc1_pmnc = cpu->cd.arm.r[rd];
431  break;
432  case 1: if (l_bit)
433  cpu->cd.arm.r[rd] = cpu->cd.arm.xsc1_ccnt;
434  else
435  cpu->cd.arm.xsc1_ccnt = cpu->cd.arm.r[rd];
436  break;
437  case 2: if (l_bit)
438  cpu->cd.arm.r[rd] = cpu->cd.arm.xsc1_pmn0;
439  else
440  cpu->cd.arm.xsc1_pmn0 = cpu->cd.arm.r[rd];
441  break;
442  case 3: if (l_bit)
443  cpu->cd.arm.r[rd] = cpu->cd.arm.xsc1_pmn1;
444  else
445  cpu->cd.arm.xsc1_pmn1 = cpu->cd.arm.r[rd];
446  break;
447  case 7: /* UNIMPLEMENTED!!! TODO */
448  /* Possibly some kind of idle or sleep function. */
449  break;
450  default:goto unknown;
451  }
452  break;
453 
454  case 1: switch (crn) {
455  case 0: if (l_bit)
456  cpu->cd.arm.r[rd] = cpu->cd.arm.xsc2_pmnc;
457  else
458  cpu->cd.arm.xsc2_pmnc = cpu->cd.arm.r[rd];
459  break;
460  case 1: if (l_bit)
461  cpu->cd.arm.r[rd] = cpu->cd.arm.xsc2_ccnt;
462  else
463  cpu->cd.arm.xsc2_ccnt = cpu->cd.arm.r[rd];
464  break;
465  case 4: if (l_bit)
466  cpu->cd.arm.r[rd] = cpu->cd.arm.xsc2_inten;
467  else
468  cpu->cd.arm.xsc2_inten = cpu->cd.arm.r[rd];
469  break;
470  case 5: if (l_bit)
471  cpu->cd.arm.r[rd] = cpu->cd.arm.xsc2_flag;
472  else
473  cpu->cd.arm.xsc2_flag = cpu->cd.arm.r[rd];
474  break;
475  case 8: if (l_bit)
476  cpu->cd.arm.r[rd] = cpu->cd.arm.xsc2_evtsel;
477  else
478  cpu->cd.arm.xsc2_evtsel = cpu->cd.arm.r[rd];
479  break;
480  default:goto unknown;
481  }
482  break;
483 
484  case 2: switch (crn) {
485  case 0: if (l_bit)
486  cpu->cd.arm.r[rd] = cpu->cd.arm.xsc2_pmn0;
487  else
488  cpu->cd.arm.xsc2_pmn0 = cpu->cd.arm.r[rd];
489  break;
490  case 1: if (l_bit)
491  cpu->cd.arm.r[rd] = cpu->cd.arm.xsc2_pmn1;
492  else
493  cpu->cd.arm.xsc2_pmn1 = cpu->cd.arm.r[rd];
494  break;
495  case 2: if (l_bit)
496  cpu->cd.arm.r[rd] = cpu->cd.arm.xsc2_pmn2;
497  else
498  cpu->cd.arm.xsc2_pmn2 = cpu->cd.arm.r[rd];
499  break;
500  case 3: if (l_bit)
501  cpu->cd.arm.r[rd] = cpu->cd.arm.xsc2_pmn3;
502  else
503  cpu->cd.arm.xsc2_pmn3 = cpu->cd.arm.r[rd];
504  break;
505  default:goto unknown;
506  }
507  break;
508 
509  default:goto unknown;
510  }
511 
512  return;
513 
514 unknown:
515  fatal("arm_coproc_xscale_14: unimplemented opcode1=%i opcode2="
516  "%i crn=%i crm=%i rd=%i l=%i)\n", opcode1, opcode2, crn,
517  crm, rd, l_bit);
518  exit(1);
519 }
520 
#define ARM_CONTROL_ALIGN
Definition: cpu_arm.h:245
uint32_t xsc2_pmn0
Definition: cpu_arm.h:215
void fatal(const char *fmt,...)
Definition: main.cc:152
uint32_t tisr
Definition: cpu_arm.h:200
int(* translate_v2p)(struct cpu *, uint64_t vaddr, uint64_t *return_paddr, int flags)
Definition: cpu.h:369
uint32_t i80321_isrc
Definition: cpu_arm.h:191
#define INVALIDATE_VADDR
Definition: cpu.h:480
uint32_t ttb
Definition: cpu_arm.h:181
int arm_translate_v2p_mmu(struct cpu *cpu, uint64_t vaddr64, uint64_t *return_paddr, int flags)
Definition: memory_arm.cc:112
uint32_t xsc2_flag
Definition: cpu_arm.h:213
struct arm_cpu_type_def cpu_type
Definition: cpu_arm.h:133
#define ARM_PC
Definition: cpu_arm.h:56
#define ARM_AUXCTRL_MD_SHIFT
Definition: cpu_arm.h:262
#define INVALIDATE_ALL
Definition: cpu.h:478
#define TISR_TMR1
Definition: i80321reg.h:308
uint32_t far
Definition: cpu_arm.h:184
uint32_t auxctrl
Definition: cpu_arm.h:180
union cpu::@1 cd
void arm_coproc_i80321_6(struct cpu *cpu, int opcode1, int opcode2, int l_bit, int crn, int crm, int rd)
uint32_t pid
Definition: cpu_arm.h:185
void arm_coproc_15(struct cpu *cpu, int opcode1, int opcode2, int l_bit, int crn, int crm, int rd)
#define ARM_CONTROL_BIG
Definition: cpu_arm.h:250
struct arm_cpu arm
Definition: cpu.h:441
uint32_t i80321_isteer
Definition: cpu_arm.h:190
uint32_t control
Definition: cpu_arm.h:179
struct interrupt tmr0_irq
Definition: cpu_arm.h:194
uint32_t fsr
Definition: cpu_arm.h:183
uint32_t tmr0
Definition: cpu_arm.h:192
uint32_t xsc1_pmn1
Definition: cpu_arm.h:208
uint32_t trr1
Definition: cpu_arm.h:199
#define ARM_CONTROL_ICACHE
Definition: cpu_arm.h:255
uint32_t tmr1
Definition: cpu_arm.h:193
int arm_translate_v2p(struct cpu *cpu, uint64_t vaddr64, uint64_t *return_paddr, int flags)
Definition: memory_arm.cc:52
uint32_t xsc2_pmn1
Definition: cpu_arm.h:216
uint32_t xsc2_pmn2
Definition: cpu_arm.h:217
#define ARM_AUXCTRL_MD
Definition: cpu_arm.h:261
#define ARM_CONTROL_MMU
Definition: cpu_arm.h:244
#define ARM_CONTROL_WBUFFER
Definition: cpu_arm.h:247
uint32_t xsc2_inten
Definition: cpu_arm.h:212
uint32_t i80321_inten
Definition: cpu_arm.h:189
#define TISR_TMR0
Definition: i80321reg.h:307
uint32_t xsc1_ccnt
Definition: cpu_arm.h:206
uint32_t xsc2_evtsel
Definition: cpu_arm.h:214
#define debug
Definition: dev_adb.cc:57
uint32_t tcr0
Definition: cpu_arm.h:196
uint32_t dacr
Definition: cpu_arm.h:182
uint32_t tcr1
Definition: cpu_arm.h:197
Definition: cpu.h:326
uint32_t wdtcr
Definition: cpu_arm.h:201
struct interrupt tmr1_irq
Definition: cpu_arm.h:195
uint32_t xsc2_pmnc
Definition: cpu_arm.h:210
uint32_t xsc2_ccnt
Definition: cpu_arm.h:211
uint32_t xsc2_pmn3
Definition: cpu_arm.h:218
#define ARM_AUXCTRL_K
Definition: cpu_arm.h:264
uint8_t byte_order
Definition: cpu.h:347
#define ARM_CONTROL_CACHE
Definition: cpu_arm.h:246
uint32_t xsc1_pmn0
Definition: cpu_arm.h:207
uint32_t cachetype
Definition: cpu_arm.h:178
uint32_t xsc1_pmnc
Definition: cpu_arm.h:205
void arm_coproc_xscale_14(struct cpu *cpu, int opcode1, int opcode2, int l_bit, int crn, int crm, int rd)
uint32_t cpu_id
Definition: cpu_arm.h:42
uint32_t cpar
Definition: cpu_arm.h:186
uint32_t r[N_ARM_REGS]
Definition: cpu_arm.h:148
uint32_t trr0
Definition: cpu_arm.h:198
void(* invalidate_translation_caches)(struct cpu *, uint64_t paddr, int flags)
Definition: cpu.h:374
#define INTERRUPT_DEASSERT(istruct)
Definition: interrupt.h:75
#define EMUL_BIG_ENDIAN
Definition: misc.h:165

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