vripreg.h Source File
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Go to the documentation of this file. 41 #define VRIP_NO_ADDR 0x00000000 45 #define VR4181_BCU_ADDR 0x0a000000 46 #define VR4181_DMAAU_ADDR VRIP_NO_ADDR 47 #define VR4181_DCU_ADDR VRIP_NO_ADDR 48 #define VR4181_CMU_ADDR 0x0a000004 49 #define VR4181_ICU_ADDR 0x0a000080 50 #define VR4181_PMU_ADDR 0x0a0000a0 51 #define VR4181_RTC_ADDR 0x0a0000c0 52 #define VR4181_DSU_ADDR 0x0a0000e0 53 #define VR4181_GIU_ADDR VRIP_NO_ADDR 54 #define VR4181_PIU_ADDR 0x0a000122 55 #define VR4181_AIU_ADDR 0x0a000160 56 #define VR4181_KIU_ADDR 0x0a000180 57 #define VR4181_DSIU_ADDR 0x0a0001a0 58 #define VR4181_LED_ADDR 0x0a000240 59 #define VR4181_SIU_ADDR 0x0c000010 60 #define VR4181_HSP_ADDR 0x0a000020 61 #define VR4181_FIR_ADDR 0x0a000000 62 #define VR4181_MEMCON_ADDR 0x0a000300 63 #define VR4181_ISABRG_ADDR 0x0b0002c0 64 #define VR4181_ECU_ADDR 0x0b0008e0 65 #define VR4181_DCU81_ADDR 0x0a000020 66 #define VR4181_CSI81_ADDR 0x0b000900 67 #define VR4181_GIU81_ADDR 0x0b000300 68 #define VR4181_LCD_ADDR 0x0a000400 69 #define VR4181_SIU1_ADDR 0x0c000000 70 #define VR4181_SCU_ARR VRIP_NO_ADDR 71 #define VR4181_SDRAMU_ADDR VRIP_NO_ADDR 72 #define VR4181_PCI_ADDR VRIP_NO_ADDR 73 #define VR4181_PCICONF_ADDR VRIP_NO_ADDR 74 #define VR4181_CSI_ADDR VRIP_NO_ADDR 79 #define VR4102_BCU_ADDR 0x0b000000 80 #define VR4102_DMAAU_ADDR 0x0b000020 81 #define VR4102_DCU_ADDR 0x0b000040 82 #define VR4102_CMU_ADDR 0x0b000060 83 #define VR4102_ICU_ADDR 0x0b000080 84 #define VR4102_PMU_ADDR 0x0b0000a0 85 #define VR4102_RTC_ADDR 0x0b0000c0 86 #define VR4102_DSU_ADDR 0x0b0000e0 87 #define VR4102_GIU_ADDR 0x0b000100 88 #define VR4102_PIU_ADDR 0x0b000120 89 #define VR4102_AIU_ADDR 0x0b000160 90 #define VR4102_KIU_ADDR 0x0b000180 91 #define VR4102_DSIU_ADDR 0x0b0001a0 92 #define VR4102_LED_ADDR 0x0b000240 93 #define VR4102_SIU_ADDR 0x0c000000 94 #define VR4102_HSP_ADDR 0x0c000020 95 #define VR4102_FIR_ADDR 0x0b000000 96 #define VR4102_MEMCON_ADDR VRIP_NO_ADDR 97 #define VR4102_ISABRG_ADDR VRIP_NO_ADDR 98 #define VR4102_ECU_ADDR VRIP_NO_ADDR 99 #define VR4102_DCU81_ADDR VRIP_NO_ADDR 100 #define VR4102_CSI81_ADDR VRIP_NO_ADDR 101 #define VR4102_GIU81_ADDR VRIP_NO_ADDR 102 #define VR4102_SIU1_ADDR VRIP_NO_ADDR 103 #define VR4102_SCU_ARR VRIP_NO_ADDR 104 #define VR4102_SDRAMU_ADDR VRIP_NO_ADDR 105 #define VR4102_PCI_ADDR VRIP_NO_ADDR 106 #define VR4102_PCICONF_ADDR VRIP_NO_ADDR 107 #define VR4102_CSI_ADDR VRIP_NO_ADDR 111 #define VR4122_BCU_ADDR 0x0f000000 112 #define VR4122_DMAAU_ADDR 0x0f000020 113 #define VR4122_DCU_ADDR 0x0f000040 114 #define VR4122_CMU_ADDR 0x0f000060 115 #define VR4122_ICU_ADDR 0x0f000080 116 #define VR4122_PMU_ADDR 0x0f0000c0 117 #define VR4122_RTC_ADDR 0x0f000100 118 #define VR4122_DSU_ADDR VRIP_NO_ADDR 119 #define VR4122_GIU_ADDR 0x0f000140 120 #define VR4122_PIU_ADDR VRIP_NO_ADDR 121 #define VR4122_AIU_ADDR VRIP_NO_ADDR 122 #define VR4122_KIU_ADDR VRIP_NO_ADDR 123 #define VR4122_DSIU_ADDR 0x0f000820 124 #define VR4122_LED_ADDR 0x0f000180 125 #define VR4122_SIU_ADDR 0x0f000800 126 #define VR4122_HSP_ADDR VRIP_NO_ADDR 127 #define VR4122_FIR_ADDR 0x0f000840 128 #define VR4122_MEMCON_ADDR VRIP_NO_ADDR 129 #define VR4122_ISABRG_ADDR VRIP_NO_ADDR 130 #define VR4122_ECU_ADDR VRIP_NO_ADDR 131 #define VR4122_DCU81_ADDR VRIP_NO_ADDR 132 #define VR4122_CSI81_ADDR VRIP_NO_ADDR 133 #define VR4122_GIU81_ADDR VRIP_NO_ADDR 134 #define VR4122_SIU1_ADDR VRIP_NO_ADDR 135 #define VR4122_SCU_ARR 0x0f001000 136 #define VR4122_SDRAMU_ADDR 0x0f000400 137 #define VR4122_PCI_ADDR 0x0f000c00 138 #define VR4122_PCICONF_ADDR 0x0f000d00 139 #define VR4122_CSI_ADDR 0x0f0001a0 147 #include "opt_vr41xx.h" 148 #include <hpcmips/vr/vrcpudef.h> 151 #if defined SINGLE_VRIP_BASE 153 #if defined VRGROUP_4181 154 #define VRIP_BASE_ADDR 0x0a000000 156 #define VRIP_BCU_ADDR VR4181_BCU_ADDR 157 #define VRIP_DMAAU_ADDR VR4181_DMAAU_ADDR 158 #define VRIP_DCU_ADDR VR4181_DCU_ADDR 159 #define VRIP_CMU_ADDR VR4181_CMU_ADDR 160 #define VRIP_ICU_ADDR VR4181_ICU_ADDR 161 #define VRIP_PMU_ADDR VR4181_PMU_ADDR 162 #define VRIP_RTC_ADDR VR4181_RTC_ADDR 163 #define VRIP_DSU_ADDR VR4181_DSU_ADDR 164 #define VRIP_GIU_ADDR VR4181_GIU_ADDR 165 #define VRIP_PIU_ADDR VR4181_PIU_ADDR 166 #define VRIP_AIU_ADDR VR4181_AIU_ADDR 167 #define VRIP_KIU_ADDR VR4181_KIU_ADDR 168 #define VRIP_DSIU_ADDR VR4181_DSIU_ADDR 169 #define VRIP_LED_ADDR VR4181_LED_ADDR 170 #define VRIP_SIU_ADDR VR4181_SIU_ADDR 171 #define VRIP_HSP_ADDR VR4181_HSP_ADDR 172 #define VRIP_FIR_ADDR VR4181_FIR_ADDR 173 #define VRIP_MEMCON_ADDR VR4181_MEMCON_ADDR 174 #define VRIP_ISABRG_ADDR VR4181_ISABRG_ADDR 175 #define VRIP_ECU_ADDR VR4181_ECU_ADDR 176 #define VRIP_DCU81_ADDR VR4181_DCU81_ADDR 177 #define VRIP_CSI81_ADDR VR4181_CSI81_ADDR 178 #define VRIP_GIU81_ADDR VR4181_GIU81_ADDR 179 #define VRIP_LCD_ADDR VR4181_LCD_ADDR 180 #define VRIP_SIU1_ADDR VR4181_SIU1_ADDR 181 #define VRIP_SCU_ARR VR4181_SCU_ARR 182 #define VRIP_SDRAMU_ADDR VR4181_SDRAMU_ADDR 183 #define VRIP_PCI_ADDR VR4181_PCI_ADDR 184 #define VRIP_PCICONF_ADDR VR4181_PCICONF_ADDR 185 #define VRIP_CSI_ADDR VR4181_CSI_ADDR 189 #if defined VRGROUP_4122_4131 190 #define VRIP_BASE_ADDR 0x0f000000 192 #define VRIP_BCU_ADDR VR4122_BCU_ADDR 193 #define VRIP_DMAAU_ADDR VR4122_DMAAU_ADDR 194 #define VRIP_DCU_ADDR VR4122_DCU_ADDR 195 #define VRIP_CMU_ADDR VR4122_CMU_ADDR 196 #define VRIP_ICU_ADDR VR4122_ICU_ADDR 197 #define VRIP_PMU_ADDR VR4122_PMU_ADDR 198 #define VRIP_RTC_ADDR VR4122_RTC_ADDR 199 #define VRIP_DSU_ADDR VR4122_DSU_ADDR 200 #define VRIP_GIU_ADDR VR4122_GIU_ADDR 201 #define VRIP_PIU_ADDR VR4122_PIU_ADDR 202 #define VRIP_AIU_ADDR VR4122_AIU_ADDR 203 #define VRIP_KIU_ADDR VR4122_KIU_ADDR 204 #define VRIP_DSIU_ADDR VR4122_DSIU_ADDR 205 #define VRIP_LED_ADDR VR4122_LED_ADDR 206 #define VRIP_SIU_ADDR VR4122_SIU_ADDR 207 #define VRIP_HSP_ADDR VR4122_HSP_ADDR 208 #define VRIP_FIR_ADDR VR4122_FIR_ADDR 209 #define VRIP_MEMCON_ADDR VR4122_MEMCON_ADDR 210 #define VRIP_ISABRG_ADDR VR4122_ISABRG_ADDR 211 #define VRIP_ECU_ADDR VR4122_ECU_ADDR 212 #define VRIP_DCU81_ADDR VR4122_DCU81_ADDR 213 #define VRIP_CSI81_ADDR VR4122_CSI81_ADDR 214 #define VRIP_GIU81_ADDR VR4122_CSI81_ADDR 215 #define VRIP_SIU1_ADDR VR4122_SIU1_ADDR 216 #define VRIP_SCU_ARR VR4122_SCU_ARR 217 #define VRIP_SDRAMU_ADDR VR4122_SDRAMU_ADDR 218 #define VRIP_PCI_ADDR VR4122_PCI_ADDR 219 #define VRIP_PCICONF_ADDR VR4122_PCICONF_ADDR 220 #define VRIP_CSI_ADDR VR4122_CSI_ADDR 224 #if defined VRGROUP_4102_4121 225 #define VRIP_BASE_ADDR 0x0b000000 227 #define VRIP_BCU_ADDR VR4102_BCU_ADDR 228 #define VRIP_DMAAU_ADDR VR4102_DMAAU_ADDR 229 #define VRIP_DCU_ADDR VR4102_DCU_ADDR 230 #define VRIP_CMU_ADDR VR4102_CMU_ADDR 231 #define VRIP_ICU_ADDR VR4102_ICU_ADDR 232 #define VRIP_PMU_ADDR VR4102_PMU_ADDR 233 #define VRIP_RTC_ADDR VR4102_RTC_ADDR 234 #define VRIP_DSU_ADDR VR4102_DSU_ADDR 235 #define VRIP_GIU_ADDR VR4102_GIU_ADDR 236 #define VRIP_PIU_ADDR VR4102_PIU_ADDR 237 #define VRIP_AIU_ADDR VR4102_AIU_ADDR 238 #define VRIP_KIU_ADDR VR4102_KIU_ADDR 239 #define VRIP_DSIU_ADDR VR4102_DSIU_ADDR 240 #define VRIP_LED_ADDR VR4102_LED_ADDR 241 #define VRIP_SIU_ADDR VR4102_SIU_ADDR 242 #define VRIP_HSP_ADDR VR4102_HSP_ADDR 243 #define VRIP_FIR_ADDR VR4102_FIR_ADDR 244 #define VRIP_MEMCON_ADDR VR4102_MEMCON_ADDR 245 #define VRIP_ISABRG_ADDR VR4102_ISABRG_ADDR 246 #define VRIP_ECU_ADDR VR4102_ECU_ADDR 247 #define VRIP_DCU81_ADDR VR4102_DCU81_ADDR 248 #define VRIP_CSI81_ADDR VR4102_CSI81_ADDR 249 #define VRIP_GIU81_ADDR VR4102_GIU81_ADDR 250 #define VRIP_SIU1_ADDR VR4102_SIU1_ADDR 251 #define VRIP_SCU_ARR VR4102_SCU_ARR 252 #define VRIP_SDRAMU_ADDR VR4102_SDRAMU_ADDR 253 #define VRIP_PCI_ADDR VR4102_PCI_ADDR 254 #define VRIP_PCICONF_ADDR VR4102_PCICONF_ADDR 255 #define VRIP_CSI_ADDR VR4102_CSI_ADDR 265 #define VRIP_INTR_BCU 25 266 #define VRIP_INTR_CSI 24 267 #define VRIP_INTR_SCU 23 268 #define VRIP_INTR_PCI 22 269 #define VRIP_INTR_LCD 22 270 #define VRIP_INTR_DSIU 21 271 #define VRIP_INTR_DCU81 21 272 #define VRIP_INTR_FIR 20 273 #define VRIP_INTR_TCLK 19 274 #define VRIP_INTR_CSI81 19 275 #define VRIP_INTR_HSP 18 276 #define VRIP_INTR_ECU 18 277 #define VRIP_INTR_LED 17 278 #define VRIP_INTR_RTCL2 16 280 #define VRIP_INTR_DOZEPIU 13 281 #define VRIP_INTR_CLKRUN 12 282 #define VRIP_INTR_SOFT 11 283 #define VRIP_INTR_WRBERR 10 284 #define VRIP_INTR_SIU 9 285 #define VRIP_INTR_GIU 8 286 #define VRIP_INTR_KIU 7 287 #define VRIP_INTR_AIU 6 288 #define VRIP_INTR_PIU 5 290 #define VRIP_INTR_ETIMER 3 291 #define VRIP_INTR_RTCL1 2 292 #define VRIP_INTR_POWER 1 293 #define VRIP_INTR_BAT 0
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