bus_pci.cc Source File

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1 /*
2  * Copyright (C) 2004-2018 Anders Gavare. All rights reserved.
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions are met:
6  *
7  * 1. Redistributions of source code must retain the above copyright
8  * notice, this list of conditions and the following disclaimer.
9  * 2. Redistributions in binary form must reproduce the above copyright
10  * notice, this list of conditions and the following disclaimer in the
11  * documentation and/or other materials provided with the distribution.
12  * 3. The name of the author may not be used to endorse or promote products
13  * derived from this software without specific prior written permission.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25  * SUCH DAMAGE.
26  *
27  *
28  * COMMENT: Generic PCI bus framework
29  *
30  * This is not a normal "device", but is used by individual PCI controllers
31  * and devices.
32  *
33  * See NetBSD's pcidevs.h for more PCI vendor and device identifiers.
34  *
35  * TODO:
36  *
37  * x) Allow guest OSes to do runtime address fixups (i.e. actually
38  * move a device from one address to another).
39  *
40  * x) Generalize the PCI and legacy ISA interrupt routing stuff.
41  *
42  * x) Make sure that pci_little_endian is used correctly everywhere.
43  */
44 
45 #include <stdio.h>
46 #include <stdlib.h>
47 #include <string.h>
48 
49 #define BUS_PCI_C
50 
51 #include "bus_isa.h"
52 #include "bus_pci.h"
53 #include "cpu.h"
54 #include "device.h"
55 #include "devices.h"
56 #include "diskimage.h"
57 #include "machine.h"
58 #include "memory.h"
59 #include "misc.h"
60 #include "wdc.h"
61 
62 #include "thirdparty/cpc700reg.h"
63 
64 extern int verbose;
65 
66 
67 #ifdef UNSTABLE_DEVEL
68 #define debug fatal
69 #endif
70 
71 
72 /*
73  * bus_pci_decompose_1():
74  *
75  * Helper function for decomposing Mechanism 1 tags.
76  */
77 void bus_pci_decompose_1(uint32_t t, int *bus, int *dev, int *func, int *reg)
78 {
79  *bus = (t >> 16) & 0xff;
80  *dev = (t >> 11) & 0x1f;
81  *func = (t >> 8) & 0x7;
82  *reg = t & 0xff;
83 
84  /* Warn about unaligned register access: */
85  if (t & 3)
86  fatal("[ bus_pci_decompose_1: WARNING: reg = 0x%02x ]\n",
87  t & 0xff);
88 }
89 
90 
91 /*
92  * bus_pci_data_access():
93  *
94  * Reads from or writes to the PCI configuration registers of a device.
95  */
96 void bus_pci_data_access(struct cpu *cpu, struct pci_data *pci_data,
97  uint64_t *data, int len, int writeflag)
98 {
99  struct pci_device *dev;
100  unsigned char *cfg_base;
101  uint64_t x, idata = *data;
102  int i;
103 
104  /* Scan through the list of pci_device entries. */
105  dev = pci_data->first_device;
106  while (dev != NULL) {
107  if (dev->bus == pci_data->cur_bus &&
108  dev->function == pci_data->cur_func &&
109  dev->device == pci_data->cur_device)
110  break;
111  dev = dev->next;
112  }
113 
114  /* No device? Then return emptiness. */
115  if (dev == NULL) {
116  if (writeflag == MEM_READ) {
117  if (pci_data->cur_reg == 0)
118  *data = (uint64_t) -1;
119  else
120  *data = 0;
121  } else {
122  fatal("[ bus_pci_data_access(): write to non-existant"
123  " device, bus %i func %i device %i ]\n",
124  pci_data->cur_bus, pci_data->cur_func,
125  pci_data->cur_device);
126  }
127  return;
128  }
129 
130  /* Return normal config data, or length data? */
131  if (pci_data->last_was_write_ffffffff &&
132  pci_data->cur_reg >= PCI_MAPREG_START &&
133  pci_data->cur_reg <= PCI_MAPREG_END - 4)
134  cfg_base = dev->cfg_mem_size;
135  else
136  cfg_base = dev->cfg_mem;
137 
138  /* Read data as little-endian: */
139  x = 0;
140  for (i=len-1; i>=0; i--) {
141  int ofs = pci_data->cur_reg + i;
142  x <<= 8;
143  x |= cfg_base[ofs & (PCI_CFG_MEM_SIZE - 1)];
144  }
145 
146  /* Register write: */
147  if (writeflag == MEM_WRITE) {
148  debug("[ bus_pci: write to PCI DATA: data = 0x%08llx ]\n",
149  (long long)idata);
150  if (idata == 0xffffffffULL &&
151  pci_data->cur_reg >= PCI_MAPREG_START &&
152  pci_data->cur_reg <= PCI_MAPREG_END - 4) {
153  pci_data->last_was_write_ffffffff = 1;
154  return;
155  }
156 
157  if (dev->cfg_reg_write == NULL ||
158  dev->cfg_reg_write(dev, pci_data->cur_reg, *data) == 0) {
159  /* Print a warning for unhandled writes: */
160  debug("[ bus_pci: write to PCI DATA: data = 0x%08llx"
161  " (current value = 0x%08llx); NOT YET"
162  " SUPPORTED. bus %i, device %i, function %i (%s)"
163  " register 0x%02x ]\n", (long long)idata,
164  (long long)x, pci_data->cur_bus,
165  pci_data->cur_device, pci_data->cur_func,
166  dev->name, pci_data->cur_reg);
167 
168  /* Special warning, to detect if NetBSD's special
169  detection of PCI devices fails: */
170  if (pci_data->cur_reg == PCI_COMMAND_STATUS_REG
171  && !((*data) & PCI_COMMAND_IO_ENABLE)) {
172  fatal("\n[ NetBSD PCI detection stuff not"
173  " yet implemented for device '%s' ]\n",
174  dev->name);
175  }
176  }
177  return;
178  }
179 
180  /* Register read: */
181  *data = x;
182 
183  pci_data->last_was_write_ffffffff = 0;
184 
185  debug("[ bus_pci: read from PCI DATA, bus %i, device "
186  "%i, function %i (%s) register 0x%02x: (len=%i) 0x%08lx ]\n",
187  pci_data->cur_bus, pci_data->cur_device, pci_data->cur_func,
188  dev->name, pci_data->cur_reg, len, (long)*data);
189 }
190 
191 
192 /*
193  * bus_pci_setaddr():
194  *
195  * Sets the address in preparation for a PCI register transfer.
196  */
197 void bus_pci_setaddr(struct cpu *cpu, struct pci_data *pci_data,
198  int bus, int device, int function, int reg)
199 {
200  if (cpu == NULL || pci_data == NULL) {
201  fatal("bus_pci_setaddr(): NULL ptr\n");
202  exit(1);
203  }
204 
205  pci_data->cur_bus = bus;
206  pci_data->cur_device = device;
207  pci_data->cur_func = function;
208  pci_data->cur_reg = reg;
209 }
210 
211 
212 /*
213  * bus_pci_add():
214  *
215  * Add a PCI device to a bus_pci device.
216  */
217 void bus_pci_add(struct machine *machine, struct pci_data *pci_data,
218  struct memory *mem, int bus, int device, int function,
219  const char *name)
220 {
221  struct pci_device *pd;
222  int ofs;
223  void (*init)(struct machine *, struct memory *, struct pci_device *);
224 
225  if (pci_data == NULL) {
226  fatal("bus_pci_add(): pci_data == NULL!\n");
227  abort();
228  }
229 
230  /* Find the PCI device: */
231  init = pci_lookup_initf(name);
232 
233  /* Make sure this bus/device/function number isn't already in use: */
234  pd = pci_data->first_device;
235  while (pd != NULL) {
236  if (pd->bus == bus && pd->device == device &&
237  pd->function == function) {
238  fatal("bus_pci_add(): (bus %i, device %i, function"
239  " %i) already in use\n", bus, device, function);
240  exit(1);
241  }
242  pd = pd->next;
243  }
244 
245  CHECK_ALLOCATION(pd = (struct pci_device *) malloc(sizeof(struct pci_device)));
246  memset(pd, 0, sizeof(struct pci_device));
247 
248  /* Add the new device first in the PCI bus' chain: */
249  pd->next = pci_data->first_device;
250  pci_data->first_device = pd;
251 
252  CHECK_ALLOCATION(pd->name = strdup(name));
253  pd->pcibus = pci_data;
254  pd->bus = bus;
255  pd->device = device;
256  pd->function = function;
257 
258  /*
259  * Initialize with some default values:
260  *
261  * TODO: The command status register is best to set up per device.
262  * The size registers should also be set up on a per-device basis.
263  */
264  PCI_SET_DATA(PCI_COMMAND_STATUS_REG,
266  for (ofs = PCI_MAPREG_START; ofs < PCI_MAPREG_END; ofs += 4)
267  PCI_SET_DATA_SIZE(ofs, 0x00100000 - 1);
268 
269  if (init == NULL) {
270  fatal("No init function for PCI device \"%s\"?\n", name);
271  exit(1);
272  }
273 
274  /* Call the PCI device' init function: */
275  init(machine, mem, pd);
276 }
277 
278 
279 /*
280  * allocate_device_space():
281  *
282  * Used by glue code (see below) to allocate space for a PCI device.
283  *
284  * The returned values in portp and memp are the actual (emulated) addresses
285  * that the device should use. (Normally only one of these is actually used.)
286  *
287  * TODO: PCI irqs?
288  */
289 static void allocate_device_space(struct pci_device *pd,
290  uint64_t portsize, uint64_t memsize,
291  uint64_t *portp, uint64_t *memp)
292 {
293  uint64_t port, mem;
294 
295  /* Calculate an aligned starting port: */
296  port = pd->pcibus->cur_pci_portbase;
297  if (portsize != 0) {
298  port = ((port - 1) | (portsize - 1)) + 1;
299  pd->pcibus->cur_pci_portbase = port;
300  PCI_SET_DATA(PCI_MAPREG_START + pd->cur_mapreg_offset,
301  port | PCI_MAPREG_TYPE_IO);
302  PCI_SET_DATA_SIZE(PCI_MAPREG_START + pd->cur_mapreg_offset,
303  ((portsize - 1) & ~0xf) | 0xd);
304  pd->cur_mapreg_offset += sizeof(uint32_t);
305  }
306 
307  /* Calculate an aligned starting memory location: */
308  mem = pd->pcibus->cur_pci_membase;
309  if (memsize != 0) {
310  mem = ((mem - 1) | (memsize - 1)) + 1;
311  pd->pcibus->cur_pci_membase = mem;
312  PCI_SET_DATA(PCI_MAPREG_START + pd->cur_mapreg_offset, mem);
313  PCI_SET_DATA_SIZE(PCI_MAPREG_START + pd->cur_mapreg_offset,
314  ((memsize - 1) & ~0xf) | 0x0);
315  pd->cur_mapreg_offset += sizeof(uint32_t);
316  }
317 
318  *portp = port + pd->pcibus->pci_actual_io_offset;
319  *memp = mem + pd->pcibus->pci_actual_mem_offset;
320 
321  if (verbose >= 2) {
322  debug("pci device '%s' at", pd->name);
323  if (portsize != 0)
324  debug(" port 0x%llx-0x%llx", (long long)pd->pcibus->
325  cur_pci_portbase, (long long)(pd->pcibus->
326  cur_pci_portbase + portsize - 1));
327  if (memsize != 0)
328  debug(" mem 0x%llx-0x%llx", (long long)pd->pcibus->
329  cur_pci_membase, (long long)(pd->pcibus->
330  cur_pci_membase + memsize - 1));
331  debug("\n");
332  }
333 
334  pd->pcibus->cur_pci_portbase += portsize;
335  pd->pcibus->cur_pci_membase += memsize;
336 }
337 
338 
339 /*
340  * bus_pci_init():
341  *
342  * This doesn't register a device, but instead returns a pointer to a struct
343  * which should be passed to other bus_pci functions when accessing the bus.
344  *
345  * irq_path is the interrupt path to the PCI controller.
346  *
347  * pci_portbase, pci_membase, and pci_irqbase are the port, memory, and
348  * interrupt bases for PCI devices (as found in the configuration registers).
349  *
350  * pci_actual_io_offset and pci_actual_mem_offset are the offset from
351  * the values in the configuration registers to the actual (emulated) device.
352  *
353  * isa_portbase, isa_membase, and isa_irqbase are the port, memory, and
354  * interrupt bases for legacy ISA devices.
355  */
356 struct pci_data *bus_pci_init(struct machine *machine, const char *irq_path,
357  uint64_t pci_actual_io_offset, uint64_t pci_actual_mem_offset,
358  uint64_t pci_portbase, uint64_t pci_membase, const char *pci_irqbase,
359  uint64_t isa_portbase, uint64_t isa_membase, const char *isa_irqbase)
360 {
361  struct pci_data *d;
362 
363  CHECK_ALLOCATION(d = (struct pci_data *) malloc(sizeof(struct pci_data)));
364  memset(d, 0, sizeof(struct pci_data));
365 
366  CHECK_ALLOCATION(d->irq_path = strdup(irq_path));
367  CHECK_ALLOCATION(d->irq_path_isa = strdup(isa_irqbase));
368  CHECK_ALLOCATION(d->irq_path_pci = strdup(pci_irqbase));
369 
370  d->pci_actual_io_offset = pci_actual_io_offset;
371  d->pci_actual_mem_offset = pci_actual_mem_offset;
372  d->pci_portbase = pci_portbase;
373  d->pci_membase = pci_membase;
374  d->isa_portbase = isa_portbase;
375  d->isa_membase = isa_membase;
376 
377  d->cur_pci_portbase = d->pci_portbase;
378  d->cur_pci_membase = d->pci_membase;
379 
380  /* Assume that the first 64KB could be used by legacy ISA devices: */
381  if (d->isa_portbase != 0 || d->isa_membase != 0) {
382  d->cur_pci_portbase += 0x10000;
383  d->cur_pci_membase += 0x10000;
384  }
385 
386  return d;
387 }
388 
389 
390 
391 /******************************************************************************
392  * *
393  * The following is glue code for PCI controllers and devices. The glue *
394  * code does the minimal stuff necessary to get an emulated OS to detect *
395  * the device (i.e. set up PCI configuration registers), and then if *
396  * necessary adds a "normal" device. *
397  * *
398  ******************************************************************************/
399 
400 
401 
402 /*
403  * Integraphics Systems "igsfb" Framebuffer (graphics) card, used in at
404  * least the NetWinder.
405  */
406 
407 #define PCI_VENDOR_INTEGRAPHICS 0x10ea
408 
409 PCIINIT(igsfb)
410 {
411  char tmpstr[200];
412 
413  PCI_SET_DATA(PCI_ID_REG,
415 
416  PCI_SET_DATA(PCI_CLASS_REG,
418  PCI_SUBCLASS_DISPLAY_VGA, 0) + 0x01);
419 
420  /* TODO */
421  PCI_SET_DATA(0x10, 0x08000000);
422 
423  snprintf(tmpstr, sizeof(tmpstr), "igsfb addr=0x%llx",
424  (long long)(pd->pcibus->isa_membase + 0x08000000));
425  device_add(machine, tmpstr);
426 }
427 
428 
429 
430 /*
431  * S3 ViRGE graphics.
432  *
433  * TODO: Only emulates a standard VGA card, so far.
434  */
435 
436 #define PCI_VENDOR_S3 0x5333
437 #define PCI_PRODUCT_S3_VIRGE 0x5631
438 #define PCI_PRODUCT_S3_VIRGE_DX 0x8a01
439 
440 PCIINIT(s3_virge)
441 {
442  PCI_SET_DATA(PCI_ID_REG,
444 
445  PCI_SET_DATA(PCI_CLASS_REG,
447  PCI_SUBCLASS_DISPLAY_VGA, 0) + 0x01);
448 
449  dev_vga_init(machine, mem, pd->pcibus->isa_membase + 0xa0000,
450  pd->pcibus->isa_portbase + 0x3c0, machine->machine_name);
451 }
452 
453 
454 
455 /*
456  * Acer Labs M5229 PCI-IDE (UDMA) controller.
457  * Acer Labs M1543 PCI->ISA bridge.
458  */
459 
460 #define PCI_VENDOR_ALI 0x10b9
461 #define PCI_PRODUCT_ALI_M1543 0x1533 /* NOTE: not 1543 */
462 #define PCI_PRODUCT_ALI_M5229 0x5229
463 
464 PCIINIT(ali_m1543)
465 {
466  PCI_SET_DATA(PCI_ID_REG,
468 
470  PCI_SUBCLASS_BRIDGE_ISA, 0) + 0xc3);
471 
472  PCI_SET_DATA(PCI_BHLC_REG,
473  PCI_BHLC_CODE(0,0, 1 /* multi-function */, 0x40,0));
474 
475  /* Linux uses these to detect which IRQ the IDE controller uses: */
476  PCI_SET_DATA(0x44, 0x0000000e);
477  PCI_SET_DATA(0x58, 0x00000003);
478 
479  switch (machine->machine_type) {
480  case MACHINE_CATS:
481  bus_isa_init(machine, pd->pcibus->irq_path_isa,
483  0x7c000000, 0x80000000);
484  break;
485  default:fatal("ali_m1543 init: unimplemented machine type\n");
486  exit(1);
487  }
488 }
489 
490 PCIINIT(ali_m5229)
491 {
492  char tmpstr[300], irqstr[300];
493 
494  PCI_SET_DATA(PCI_ID_REG,
496 
498  PCI_SUBCLASS_MASS_STORAGE_IDE, 0x60) + 0xc1);
499 
500  switch (machine->machine_type) {
501  case MACHINE_CATS:
502  /* CATS ISA interrupts are at footbridge irq 10: */
503  snprintf(irqstr, sizeof(irqstr), "%s.10.isa",
504  pd->pcibus->irq_path);
505  break;
506  default:fatal("ali_m5229 init: unimplemented machine type\n");
507  exit(1);
508  }
509 
512  snprintf(tmpstr, sizeof(tmpstr), "wdc addr=0x%llx irq=%s.%i",
513  (long long)(pd->pcibus->isa_portbase + 0x1f0),
514  irqstr, 14);
515  device_add(machine, tmpstr);
516  }
517 
518  /* The secondary channel is disabled. TODO: fix this. */
519 }
520 
521 
522 
523 /*
524  * Adaptec AHC SCSI controller.
525  */
526 
527 #define PCI_VENDOR_ADP 0x9004 /* Adaptec */
528 #define PCI_VENDOR_ADP2 0x9005 /* Adaptec (2nd PCI Vendor ID) */
529 #define PCI_PRODUCT_ADP_2940U 0x8178 /* AHA-2940 Ultra */
530 #define PCI_PRODUCT_ADP_2940UP 0x8778 /* AHA-2940 Ultra Pro */
531 
533 {
534  /* Numbers taken from a Adaptec 2940U: */
535  /* http://mail-index.netbsd.org/netbsd-bugs/2000/04/29/0000.html */
536 
537  PCI_SET_DATA(PCI_ID_REG, PCI_ID_CODE(PCI_VENDOR_ADP,
539 
540  PCI_SET_DATA(PCI_COMMAND_STATUS_REG, 0x02900007);
541 
543  PCI_SUBCLASS_MASS_STORAGE_SCSI, 0) + 0x01);
544 
545  PCI_SET_DATA(PCI_BHLC_REG, 0x00004008);
546 
547  /* 1 = type i/o. 0x0000e801; address? */
548  /* second address reg = 0xf1002000? */
549  PCI_SET_DATA(PCI_MAPREG_START + 0x00, 0x00000001);
550  PCI_SET_DATA(PCI_MAPREG_START + 0x04, 0x00000000);
551 
552  PCI_SET_DATA(PCI_MAPREG_START + 0x08, 0x00000000);
553  PCI_SET_DATA(PCI_MAPREG_START + 0x0c, 0x00000000);
554  PCI_SET_DATA(PCI_MAPREG_START + 0x10, 0x00000000);
555  PCI_SET_DATA(PCI_MAPREG_START + 0x14, 0x00000000);
556  PCI_SET_DATA(PCI_MAPREG_START + 0x18, 0x00000000);
557 
558  /* Subsystem vendor ID? 0x78819004? */
559  PCI_SET_DATA(PCI_MAPREG_START + 0x1c, 0x00000000);
560 
561  PCI_SET_DATA(0x30, 0xef000000);
562  PCI_SET_DATA(PCI_CAPLISTPTR_REG, 0x000000dc);
563  PCI_SET_DATA(0x38, 0x00000000);
564  PCI_SET_DATA(PCI_INTERRUPT_REG, 0x08080109); /* interrupt pin A */
565 
566  /*
567  * TODO: this address is based on what NetBSD/sgimips uses
568  * on SGI IP32 (O2). Fix this!
569  */
570 
571  device_add(machine, "ahc addr=0x18000000");
572 
573  /* OpenBSD/sgi snapshots sometime between 2005-03-11 and
574  2005-04-04 changed to using 0x1a000000: */
575  dev_ram_init(machine, 0x1a000000, 0x2000000, DEV_RAM_MIRROR,
576  0x18000000);
577 }
578 
579 
580 
581 /*
582  * Galileo Technology GT-64xxx PCI controller.
583  *
584  * GT-64011 Used in Cobalt machines.
585  * GT-64120 Used in evbmips machines (Malta).
586  *
587  * NOTE: This works in the opposite way compared to other devices; the PCI
588  * device is added from the normal device instead of the other way around.
589  */
590 
591 #define PCI_VENDOR_GALILEO 0x11ab /* Galileo Technology */
592 #define PCI_PRODUCT_GALILEO_GT64011 0x4146 /* GT-64011 System Controller */
593 #define PCI_PRODUCT_GALILEO_GT64120 0x4620 /* GT-64120 */
594 #define PCI_PRODUCT_GALILEO_GT64260 0x6430 /* GT-64260 */
595 
596 PCIINIT(gt64011)
597 {
600 
602  PCI_SUBCLASS_BRIDGE_HOST, 0) + 0x01); /* Revision 1 */
603 }
604 
605 PCIINIT(gt64120)
606 {
609 
611  PCI_SUBCLASS_BRIDGE_HOST, 0) + 0x02); /* Revision 2? */
612 
613  switch (machine->machine_type) {
614  case MACHINE_EVBMIPS:
615  PCI_SET_DATA(PCI_MAPREG_START + 0x10, 0x1be00000);
616  break;
617  }
618 }
619 
620 PCIINIT(gt64260)
621 {
624 
626  PCI_SUBCLASS_BRIDGE_HOST, 0) + 0x01); /* Revision 1? */
627 }
628 
629 
630 
631 /*
632  * AMD PCnet Ethernet card.
633  *
634  * "Am79c970A PCnet-PCI II rev 0" or similar.
635  */
636 
637 #define PCI_VENDOR_AMD 0x1022 /* Advanced Micro Devices */
638 #define PCI_PRODUCT_AMD_PCNET_PCI 0x2000 /* PCnet-PCI Ethernet */
639 
641 {
642  int irq;
643 
644  PCI_SET_DATA(PCI_ID_REG, PCI_ID_CODE(PCI_VENDOR_AMD,
646 
648  PCI_SUBCLASS_NETWORK_ETHERNET, 0) + 0x00); /* Revision 0 */
649 
650  switch (machine->machine_type) {
651 
652  case MACHINE_EVBMIPS:
653  irq = (1 << 8) + 10; /* TODO */
654  break;
655 
656  default:fatal("pcn in non-implemented machine type %i\n",
658  exit(1);
659  }
660 
661  PCI_SET_DATA(PCI_INTERRUPT_REG, 0x01100000 | irq);
662 
663  /*
664  * TODO: Add the pcn device here. The pcn device will need to work as
665  * a wrapper for dev_le + all the DMA magic and whatever is required.
666  * It's too much to implement right now.
667  */
668 }
669 
670 
671 
672 /*
673  * Intel 31244 Serial ATA Controller
674  * Intel 82371SB PIIX3 PCI-ISA bridge
675  * Intel 82371AB PIIX4 PCI-ISA bridge
676  * Intel 82371SB IDE controller
677  * Intel 82371AB IDE controller
678  * Intel 82378ZB System I/O controller.
679  */
680 
681 #define PCI_VENDOR_INTEL 0x8086
682 #define PCI_PRODUCT_INTEL_31244 0x3200
683 #define PCI_PRODUCT_INTEL_82371SB_ISA 0x7000
684 #define PCI_PRODUCT_INTEL_82371SB_IDE 0x7010
685 #define PCI_PRODUCT_INTEL_82371AB_ISA 0x7110
686 #define PCI_PRODUCT_INTEL_82371AB_IDE 0x7111
687 #define PCI_PRODUCT_INTEL_SIO 0x0484
688 
689 PCIINIT(i31244)
690 {
691  uint64_t port, memaddr;
692  int irq = 0;
693 
696 
698  PCI_SUBCLASS_MASS_STORAGE_IDE, 0x33) + 0x00);
699 
700  switch (machine->machine_type) {
701  case MACHINE_IQ80321:
702  /* S-PCI-X slot uses PCI IRQ A, int 29 */
703  irq = (1 << 8) + 29;
704  break;
705  default:fatal("i31244 in non-implemented machine type %i\n",
707  exit(1);
708  }
709 
710  PCI_SET_DATA(PCI_INTERRUPT_REG, 0x01100000 | irq);
711 
712  allocate_device_space(pd, 0x1000, 0, &port, &memaddr);
713  allocate_device_space(pd, 0x1000, 0, &port, &memaddr);
714 
715  /* PCI IDE using dev_wdc: */
718  char tmpstr[150];
719  snprintf(tmpstr, sizeof(tmpstr), "wdc addr=0x%llx irq=%s.%i",
720  (long long)(pd->pcibus->pci_actual_io_offset + 0),
721  pd->pcibus->irq_path_pci, irq & 255);
722  device_add(machine, tmpstr);
723  }
724 }
725 
726 int piix_isa_cfg_reg_write(struct pci_device *pd, int reg, uint32_t value)
727 {
728  switch (reg) {
729  case PCI_MAPREG_START:
730  case PCI_MAPREG_START + 4:
731  case PCI_MAPREG_START + 8:
732  case PCI_MAPREG_START + 12:
733  case PCI_MAPREG_START + 16:
734  case PCI_MAPREG_START + 20:
735  PCI_SET_DATA(reg, value);
736  return 1;
737  }
738 
739  return 0;
740 }
741 
742 PCIINIT(piix3_isa)
743 {
746 
748  PCI_SUBCLASS_BRIDGE_ISA, 0) + 0x01); /* Rev 1 */
749 
750  PCI_SET_DATA(PCI_BHLC_REG,
751  PCI_BHLC_CODE(0,0, 1 /* multi-function */, 0x40,0));
752 }
753 
754 PCIINIT(piix4_isa)
755 {
758 
760  PCI_SUBCLASS_BRIDGE_ISA, 0) + 0x01); /* Rev 1 */
761 
762  PCI_SET_DATA(PCI_BHLC_REG,
763  PCI_BHLC_CODE(0,0, 1 /* multi-function */, 0x40,0));
764 
765  pd->cfg_reg_write = piix_isa_cfg_reg_write;
766 }
767 
768 PCIINIT(i82378zb)
769 {
772 
774  PCI_SUBCLASS_BRIDGE_ISA, 0) + 0x43);
775 
776  PCI_SET_DATA(PCI_BHLC_REG,
777  PCI_BHLC_CODE(0,0, 1 /* multi-function */, 0x40,0));
778 
779  PCI_SET_DATA(0x40, 0x20);
780 
781  /* PIRQ[0]=10 PIRQ[1]=11 PIRQ[2]=14 PIRQ[3]=15 */
782  PCI_SET_DATA(0x60, 0x0f0e0b0a);
783 }
784 
786  void *wdc0;
787  void *wdc1;
788 };
789 
790 int piix_ide_cfg_reg_write(struct pci_device *pd, int reg, uint32_t value)
791 {
792  void *wdc0 = ((struct piix_ide_extra *)pd->extra)->wdc0;
793  void *wdc1 = ((struct piix_ide_extra *)pd->extra)->wdc1;
794  int enabled = 0;
795 
796  PCI_SET_DATA(reg, value);
797 
798  switch (reg) {
800  if (value & PCI_COMMAND_IO_ENABLE)
801  enabled = 1;
802  if (wdc0 != NULL)
803  wdc_set_io_enabled((struct wdc_data *) wdc0, enabled);
804  if (wdc1 != NULL)
805  wdc_set_io_enabled((struct wdc_data *) wdc1, enabled);
806  return 1;
807  case PCI_MAPREG_START:
808  case PCI_MAPREG_START + 4:
809  case PCI_MAPREG_START + 8:
810  case PCI_MAPREG_START + 12:
811  case PCI_MAPREG_START + 16:
812  case PCI_MAPREG_START + 20:
813  return 1;
814  }
815 
816  return 0;
817 }
818 
819 PCIINIT(piix3_ide)
820 {
821  char tmpstr[100];
822 
825 
826  /* Possibly not correct: */
828  PCI_SUBCLASS_MASS_STORAGE_IDE, 0x00) + 0x00);
829 
830  /* PIIX_IDETIM (see NetBSD's pciide_piix_reg.h) */
831  /* channel 0 and 1 enabled as IDE */
832  PCI_SET_DATA(0x40, 0x80008000);
833 
834  CHECK_ALLOCATION(pd->extra = malloc(sizeof(struct piix_ide_extra)));
835  ((struct piix_ide_extra *)pd->extra)->wdc0 = NULL;
836  ((struct piix_ide_extra *)pd->extra)->wdc1 = NULL;
837 
840  snprintf(tmpstr, sizeof(tmpstr), "wdc addr=0x%llx "
841  "irq=%s.isa.%i", (long long)(pd->pcibus->isa_portbase +
842  0x1f0), pd->pcibus->irq_path_isa, 14);
843  ((struct piix_ide_extra *)pd->extra)->wdc0 =
844  device_add(machine, tmpstr);
845  }
846 
849  snprintf(tmpstr, sizeof(tmpstr), "wdc addr=0x%llx "
850  "irq=%s.isa.%i", (long long)(pd->pcibus->isa_portbase +
851  0x170), pd->pcibus->irq_path_isa, 15);
852  ((struct piix_ide_extra *)pd->extra)->wdc1 =
853  device_add(machine, tmpstr);
854  }
855 
856  pd->cfg_reg_write = piix_ide_cfg_reg_write;
857 }
858 
859 PCIINIT(piix4_ide)
860 {
861  char tmpstr[100];
862 
865 
866  /* Possibly not correct: */
868  PCI_SUBCLASS_MASS_STORAGE_IDE, 0x80) + 0x01);
869 
870  /* PIIX_BMIBA (see NetBSD's pciide_piix_reg.h) */
871  /* 2009-05-18: Needs to have the lowest bit set, or Linux/Malta
872  crashes. */
873  PCI_SET_DATA(0x20, 1);
874 
875  /* PIIX_IDETIM (see NetBSD's pciide_piix_reg.h) */
876  /* channel 0 and 1 enabled as IDE */
877  PCI_SET_DATA(0x40, 0x80008000);
878 
879  CHECK_ALLOCATION(pd->extra = malloc(sizeof(struct piix_ide_extra)));
880  ((struct piix_ide_extra *)pd->extra)->wdc0 = NULL;
881  ((struct piix_ide_extra *)pd->extra)->wdc1 = NULL;
882 
885  snprintf(tmpstr, sizeof(tmpstr), "wdc addr=0x%llx irq=%s."
886  "isa.%i", (long long)(pd->pcibus->isa_portbase + 0x1f0),
887  pd->pcibus->irq_path_isa, 14);
888  ((struct piix_ide_extra *)pd->extra)->wdc0 =
889  device_add(machine, tmpstr);
890  }
891 
894  snprintf(tmpstr, sizeof(tmpstr), "wdc addr=0x%llx irq=%s."
895  "isa.%i", (long long)(pd->pcibus->isa_portbase + 0x170),
896  pd->pcibus->irq_path_isa, 15);
897  ((struct piix_ide_extra *)pd->extra)->wdc1 =
898  device_add(machine, tmpstr);
899  }
900 
901  pd->cfg_reg_write = piix_ide_cfg_reg_write;
902 }
903 
904 
905 
906 /*
907  * IBM ISA bridge (used by at least one PReP machine).
908  */
909 
910 #define PCI_VENDOR_IBM 0x1014
911 #define PCI_PRODUCT_IBM_ISABRIDGE 0x000a
912 
913 PCIINIT(ibm_isa)
914 {
915  PCI_SET_DATA(PCI_ID_REG, PCI_ID_CODE(PCI_VENDOR_IBM,
917 
919  PCI_SUBCLASS_BRIDGE_ISA, 0) + 0x02);
920 
921  PCI_SET_DATA(PCI_BHLC_REG,
922  PCI_BHLC_CODE(0,0, 1 /* multi-function */, 0x40,0));
923 }
924 
925 
926 
927 /*
928  * Heuricon PCI host bridge for PM/PPC.
929  */
930 
931 #define PCI_VENDOR_HEURICON 0x1223
932 #define PCI_PRODUCT_HEURICON_PMPPC 0x000e
933 
934 PCIINIT(heuricon_pmppc)
935 {
938 
940  PCI_SUBCLASS_BRIDGE_HOST, 0) + 0x00); /* Revision? */
941 
942  PCI_SET_DATA(PCI_BHLC_REG,
943  PCI_BHLC_CODE(0,0, 1 /* multi-function */, 0x40,0));
944 }
945 
946 
947 
948 /*
949  * VIATECH VT82C586 devices:
950  *
951  * vt82c586_isa PCI->ISA bridge
952  * vt82c586_ide IDE controller
953  *
954  * TODO: This more or less just a dummy device, so far.
955  */
956 
957 #define PCI_VENDOR_VIATECH 0x1106 /* VIA Technologies */
958 #define PCI_PRODUCT_VIATECH_VT82C586_IDE 0x1571 /* VT82C586 (Apollo VP)
959  IDE Controller */
960 #define PCI_PRODUCT_VIATECH_VT82C586_ISA 0x0586 /* VT82C586 (Apollo VP)
961  PCI-ISA Bridge */
962 
963 PCIINIT(vt82c586_isa)
964 {
967 
969  PCI_SUBCLASS_BRIDGE_ISA, 0) + 0x39); /* Revision 37 or 39 */
970 
971  PCI_SET_DATA(PCI_BHLC_REG,
972  PCI_BHLC_CODE(0,0, 1 /* multi-function */, 0x40,0));
973 
974  /*
975  * NetBSD/cobalt specific: bits 7..4 are the "model id". See
976  * netbsd/usr/src/sys/arch/cobalt/cobalt/machdep.c read_board_id()
977  * for details.
978  */
980 #define COBALT_PCIB_BOARD_ID_REG 0x94
981 #define COBALT_QUBE2_ID 5
982  PCI_SET_DATA(COBALT_PCIB_BOARD_ID_REG, COBALT_QUBE2_ID << 4);
983  }
984 }
985 
987  void *wdc0;
988  void *wdc1;
989 };
990 
991 int vt82c586_ide_cfg_reg_write(struct pci_device *pd, int reg, uint32_t value)
992 {
993  void *wdc0 = ((struct vt82c586_ide_extra *)pd->extra)->wdc0;
994  void *wdc1 = ((struct vt82c586_ide_extra *)pd->extra)->wdc1;
995  int enabled = 0;
996 
997  switch (reg) {
999  if (value & PCI_COMMAND_IO_ENABLE)
1000  enabled = 1;
1001  if (wdc0 != NULL)
1002  wdc_set_io_enabled((struct wdc_data *) wdc0, enabled);
1003  if (wdc1 != NULL)
1004  wdc_set_io_enabled((struct wdc_data *) wdc1, enabled);
1005  return 1;
1006  }
1007 
1008  return 0;
1009 }
1010 
1011 PCIINIT(vt82c586_ide)
1012 {
1013  char tmpstr[100];
1014 
1017 
1018  /* Possibly not correct: */
1020  PCI_SUBCLASS_MASS_STORAGE_IDE, 0x00) + 0x01);
1021 
1022  /* APO_IDECONF */
1023  /* channel 0 and 1 enabled */
1024  PCI_SET_DATA(0x40, 0x00000003);
1025 
1026  CHECK_ALLOCATION(pd->extra = malloc(sizeof(struct vt82c586_ide_extra)));
1027  ((struct vt82c586_ide_extra *)pd->extra)->wdc0 = NULL;
1028  ((struct vt82c586_ide_extra *)pd->extra)->wdc1 = NULL;
1029 
1032  snprintf(tmpstr, sizeof(tmpstr), "wdc addr=0x%llx irq=%s."
1033  "isa.%i", (long long)(pd->pcibus->isa_portbase + 0x1f0),
1034  pd->pcibus->irq_path_isa, 14);
1035  ((struct vt82c586_ide_extra *)pd->extra)->wdc0 =
1036  device_add(machine, tmpstr);
1037  }
1038 
1041  snprintf(tmpstr, sizeof(tmpstr), "wdc addr=0x%llx irq=%s."
1042  "isa.%i", (long long)(pd->pcibus->isa_portbase + 0x170),
1043  pd->pcibus->irq_path_isa, 15);
1044  ((struct vt82c586_ide_extra *)pd->extra)->wdc1 =
1045  device_add(machine, tmpstr);
1046  }
1047 
1048  pd->cfg_reg_write = vt82c586_ide_cfg_reg_write;
1049 }
1050 
1051 
1052 
1053 /*
1054  * Symphony Labs 83C553 PCI->ISA bridge.
1055  * Symphony Labs 82C105 PCIIDE controller.
1056  */
1057 
1058 #define PCI_VENDOR_SYMPHONY 0x10ad
1059 #define PCI_PRODUCT_SYMPHONY_83C553 0x0565
1060 #define PCI_PRODUCT_SYMPHONY_82C105 0x0105
1061 
1062 PCIINIT(symphony_83c553)
1063 {
1066 
1068  PCI_SUBCLASS_BRIDGE_ISA, 0) + 0x10);
1069 
1070  PCI_SET_DATA(PCI_BHLC_REG,
1071  PCI_BHLC_CODE(0,0, 1 /* multi-function */, 0x40,0));
1072 
1073  switch (machine->machine_type) {
1074  case MACHINE_NETWINDER:
1075  bus_isa_init(machine, pd->pcibus->irq_path_isa,
1076  0, 0x7c000000, 0x80000000);
1077  break;
1078  default:fatal("symphony_83c553 init: unimplemented machine type\n");
1079  exit(1);
1080  }
1081 }
1082 
1084  void *wdc0;
1085  void *wdc1;
1086 };
1087 
1088 int symphony_82c105_cfg_reg_write(struct pci_device *pd, int reg,
1089  uint32_t value)
1090 {
1091  void *wdc0 = ((struct symphony_82c105_extra *)pd->extra)->wdc0;
1092  void *wdc1 = ((struct symphony_82c105_extra *)pd->extra)->wdc1;
1093  int enabled = 0;
1094 
1095 printf("reg = 0x%x\n", reg);
1096  switch (reg) {
1098  if (value & PCI_COMMAND_IO_ENABLE)
1099  enabled = 1;
1100 printf(" value = 0x%" PRIx32"\n", value);
1101  if (wdc0 != NULL)
1102  wdc_set_io_enabled((struct wdc_data *) wdc0, enabled);
1103  if (wdc1 != NULL)
1104  wdc_set_io_enabled((struct wdc_data *) wdc1, enabled);
1105  /* Set all bits: */
1106  PCI_SET_DATA(reg, value);
1107  return 1;
1108  case PCI_MAPREG_START:
1109  case PCI_MAPREG_START + 4:
1110  case PCI_MAPREG_START + 8:
1111  case PCI_MAPREG_START + 12:
1112  case PCI_MAPREG_START + 16:
1113  case PCI_MAPREG_START + 20:
1114  PCI_SET_DATA(reg, value);
1115  return 1;
1116  }
1117 
1118  return 0;
1119 }
1120 
1121 PCIINIT(symphony_82c105)
1122 {
1123  char tmpstr[100];
1124 
1127 
1128  /* Possibly not correct: */
1130  PCI_SUBCLASS_MASS_STORAGE_IDE, 0x00) + 0x05);
1131 
1132  /* TODO: Interrupt line: */
1133  /* PCI_SET_DATA(PCI_INTERRUPT_REG, 0x28140000); */
1134 
1135  /* APO_IDECONF */
1136  /* channel 0 and 1 enabled */
1137  PCI_SET_DATA(0x40, 0x00000003);
1138 
1139  CHECK_ALLOCATION(pd->extra =
1140  malloc(sizeof(struct symphony_82c105_extra)));
1141  ((struct symphony_82c105_extra *)pd->extra)->wdc0 = NULL;
1142  ((struct symphony_82c105_extra *)pd->extra)->wdc1 = NULL;
1143 
1146  snprintf(tmpstr, sizeof(tmpstr), "wdc addr=0x%llx irq=%s."
1147  "isa.%i", (long long)(pd->pcibus->isa_portbase + 0x1f0),
1148  pd->pcibus->irq_path_isa, 14);
1149  ((struct symphony_82c105_extra *)pd->extra)->wdc0 =
1150  device_add(machine, tmpstr);
1151  }
1152 
1155  snprintf(tmpstr, sizeof(tmpstr), "wdc addr=0x%llx irq=%s."
1156  "isa.%i", (long long)(pd->pcibus->isa_portbase + 0x170),
1157  pd->pcibus->irq_path_isa, 15);
1158  ((struct symphony_82c105_extra *)pd->extra)->wdc1 =
1159  device_add(machine, tmpstr);
1160  }
1161 
1162  pd->cfg_reg_write = symphony_82c105_cfg_reg_write;
1163 }
1164 
1165 
1166 
1167 /*
1168  * Realtek 8139C+ PCI ethernet.
1169  */
1170 
1171 #define PCI_VENDOR_REALTEK 0x10ec
1172 #define PCI_PRODUCT_REALTEK_RT8139 0x8139
1173 
1174 PCIINIT(rtl8139c)
1175 {
1176  uint64_t port, memaddr;
1177  int pci_int_line = 0x101, irq = 0;
1178  char irqstr[200];
1179  char tmpstr[200];
1180 
1183 
1185  PCI_SUBCLASS_NETWORK_ETHERNET, 0x00) + 0x20);
1186 
1187  switch (machine->machine_type) {
1188  case MACHINE_LANDISK:
1189  irq = 5;
1190  pci_int_line = 0x105;
1191  break;
1192  default:fatal("rtl8139c for this machine has not been "
1193  "implemented yet\n");
1194  exit(1);
1195  }
1196 
1197  PCI_SET_DATA(PCI_INTERRUPT_REG, 0x28140000 | pci_int_line);
1198 
1199  allocate_device_space(pd, 0x100, 0, &port, &memaddr);
1200 
1201  snprintf(irqstr, sizeof(irqstr), "%s.%i",
1202  pd->pcibus->irq_path_pci, irq);
1203 
1204  snprintf(tmpstr, sizeof(tmpstr), "rtl8139c addr=0x%llx "
1205  "irq=%s pci_little_endian=1", (long long)port, irqstr);
1206 
1207  device_add(machine, tmpstr);
1208 }
1209 
1210 
1211 
1212 /*
1213  * DEC 21143 ("Tulip") PCI ethernet.
1214  */
1215 
1216 #define PCI_VENDOR_DEC 0x1011 /* Digital Equipment */
1217 #define PCI_PRODUCT_DEC_21142 0x0019 /* DECchip 21142/21143 10/100 Ethernet */
1218 
1219 PCIINIT(dec21143)
1220 {
1221  uint64_t port, memaddr;
1222  int pci_int_line = 0x101, irq = 0, isa = 0;
1223  char irqstr[200];
1224  char tmpstr[200];
1225 
1226  PCI_SET_DATA(PCI_ID_REG, PCI_ID_CODE(PCI_VENDOR_DEC,
1228 
1229  PCI_SET_DATA(PCI_COMMAND_STATUS_REG, 0x02000017);
1230 
1232  PCI_SUBCLASS_NETWORK_ETHERNET, 0x00) + 0x41);
1233 
1234  PCI_SET_DATA(PCI_BHLC_REG, PCI_BHLC_CODE(0,0,0, 0x40,0));
1235 
1236  switch (machine->machine_type) {
1237  case MACHINE_CATS:
1238  /* CATS int 18 = PCI. */
1239  irq = 18;
1240  pci_int_line = 0x101;
1241  break;
1242  case MACHINE_COBALT:
1243  /* On Cobalt, IRQ 7 = PCI. */
1244  irq = 8 + 7;
1245  pci_int_line = 0x407;
1246  break;
1247  case MACHINE_PREP:
1248  irq = 10;
1249  isa = 1;
1250  pci_int_line = 0x20a;
1251  break;
1252  case MACHINE_MVMEPPC:
1253  /* TODO */
1254  irq = 10;
1255  pci_int_line = 0x40a;
1256  break;
1257  case MACHINE_PMPPC:
1258  /* TODO, not working yet */
1259  irq = 31 - CPC_IB_EXT1;
1260  pci_int_line = 0x101;
1261  break;
1262  case MACHINE_MACPPC:
1263  /* TODO, not working yet */
1264  irq = 25;
1265  pci_int_line = 0x101;
1266  break;
1267  }
1268 
1269  PCI_SET_DATA(PCI_INTERRUPT_REG, 0x28140000 | pci_int_line);
1270 
1271  allocate_device_space(pd, 0x100, 0x100, &port, &memaddr);
1272 
1273  if (isa)
1274  snprintf(irqstr, sizeof(irqstr), "%s.isa.%i",
1275  pd->pcibus->irq_path_isa, irq);
1276  else
1277  snprintf(irqstr, sizeof(irqstr), "%s.%i",
1278  pd->pcibus->irq_path_pci, irq);
1279 
1280  snprintf(tmpstr, sizeof(tmpstr), "dec21143 addr=0x%llx addr2=0x%llx "
1281  "irq=%s pci_little_endian=1", (long long)port,
1282  (long long)memaddr, irqstr);
1283 
1284  device_add(machine, tmpstr);
1285 }
1286 
1287 
1288 
1289 /*
1290  * DEC 21030 "tga" graphics.
1291  */
1292 
1293 #define PCI_PRODUCT_DEC_21030 0x0004 /* DECchip 21030 ("TGA") */
1294 
1295 PCIINIT(dec21030)
1296 {
1297  uint64_t base = 0;
1298  char tmpstr[200];
1299 
1300  PCI_SET_DATA(PCI_ID_REG, PCI_ID_CODE(PCI_VENDOR_DEC,
1302 
1303  PCI_SET_DATA(PCI_COMMAND_STATUS_REG, 0x02800087); /* TODO */
1304 
1306  PCI_SUBCLASS_DISPLAY_VGA, 0x00) + 0x03);
1307 
1308  /*
1309  * See http://mail-index.netbsd.org/port-arc/2001/08/13/0000.html
1310  * for more info.
1311  */
1312 
1313  PCI_SET_DATA(PCI_BHLC_REG, 0x0000ff00);
1314 
1315  /* 8 = prefetchable */
1316  PCI_SET_DATA(0x10, 0x00000008);
1317  PCI_SET_DATA(0x30, 0x08000001);
1318  PCI_SET_DATA(PCI_INTERRUPT_REG, 0x00000100); /* interrupt pin A? */
1319 
1320  /*
1321  * Experimental:
1322  *
1323  * TODO: Base address, pci_little_endian, ...
1324  */
1325 
1326  switch (machine->machine_type) {
1327  case MACHINE_ARC:
1328  base = 0x100000000ULL;
1329  break;
1330  default:fatal("dec21030 in non-implemented machine type %i\n",
1332  exit(1);
1333  }
1334 
1335  snprintf(tmpstr, sizeof(tmpstr), "dec21030 addr=0x%llx",
1336  (long long)(base));
1337  device_add(machine, tmpstr);
1338 }
1339 
1340 
1341 
1342 /*
1343  * Motorola MPC105 "Eagle" Host Bridge
1344  *
1345  * Used in at least PReP and BeBox.
1346  */
1347 
1348 #define PCI_VENDOR_MOT 0x1057
1349 #define PCI_PRODUCT_MOT_MPC105 0x0001
1350 
1351 PCIINIT(eagle)
1352 {
1353  PCI_SET_DATA(PCI_ID_REG, PCI_ID_CODE(PCI_VENDOR_MOT,
1355 
1357  PCI_SUBCLASS_BRIDGE_HOST, 0) + 0x24);
1358 
1359  PCI_SET_DATA(PCI_BHLC_REG,
1360  PCI_BHLC_CODE(0,0, 1 /* multi-function */, 0x40,0));
1361 }
1362 
1363 
1364 
1365 /*
1366  * Apple (MacPPC) stuff:
1367  *
1368  * Grand Central (I/O controller)
1369  * Uni-North (PCI controller)
1370  */
1371 
1372 #define PCI_VENDOR_APPLE 0x106b
1373 #define PCI_PRODUCT_APPLE_GC 0x0002
1374 #define PCI_PRODUCT_APPLE_UNINORTH1 0x001e
1375 
1376 PCIINIT(gc_obio)
1377 {
1378  uint64_t port, memaddr;
1379 
1380  PCI_SET_DATA(PCI_ID_REG, PCI_ID_CODE(PCI_VENDOR_APPLE,
1382 
1383  /* TODO: */
1385  PCI_SUBCLASS_SYSTEM_PIC, 0) + 0x00);
1386 
1387  PCI_SET_DATA(PCI_BHLC_REG,
1388  PCI_BHLC_CODE(0,0, 1 /* multi-function */, 0x40,0));
1389 
1390  /* TODO */
1391  allocate_device_space(pd, 0x10000, 0x10000, &port, &memaddr);
1392 }
1393 
1394 PCIINIT(uninorth)
1395 {
1396  uint64_t port, memaddr;
1397 
1398  PCI_SET_DATA(PCI_ID_REG, PCI_ID_CODE(PCI_VENDOR_APPLE,
1400 
1402  PCI_SUBCLASS_BRIDGE_HOST, 0) + 0xff);
1403 
1404  PCI_SET_DATA(PCI_BHLC_REG,
1405  PCI_BHLC_CODE(0,0, 1 /* multi-function */, 0x40,0));
1406 
1407  /* TODO */
1408  allocate_device_space(pd, 0x10000, 0x10000, &port, &memaddr);
1409 }
1410 
1411 
1412 
1413 /*
1414  * ATI graphics cards
1415  */
1416 
1417 #define PCI_VENDOR_ATI 0x1002
1418 #define PCI_PRODUCT_ATI_RADEON_9200_2 0x5962
1419 
1420 PCIINIT(ati_radeon_9200_2)
1421 {
1422  uint64_t port, memaddr;
1423 
1424  PCI_SET_DATA(PCI_ID_REG, PCI_ID_CODE(PCI_VENDOR_ATI,
1426 
1427  /* TODO: other subclass? */
1429  PCI_SUBCLASS_DISPLAY_VGA, 0) + 0x03);
1430 
1431  /* TODO */
1432  allocate_device_space(pd, 0x1000, 0x400000, &port, &memaddr);
1433 }
1434 
#define PCI_VENDOR_ADP
Definition: bus_pci.cc:527
#define PCI_PRODUCT_INTEL_82371SB_IDE
Definition: bus_pci.cc:684
#define PCI_PRODUCT_VIATECH_VT82C586_ISA
Definition: bus_pci.cc:960
void fatal(const char *fmt,...)
Definition: main.cc:152
#define MACHINE_COBALT
Definition: machine.h:214
#define PCI_VENDOR_S3
Definition: bus_pci.cc:436
#define PCI_PRODUCT_INTEL_82371AB_ISA
Definition: bus_pci.cc:685
#define COBALT_PCIB_BOARD_ID_REG
int diskimage_exist(struct machine *machine, int id, int type)
Definition: diskimage.cc:106
#define PCI_SUBCLASS_SYSTEM_PIC
Definition: pcireg.h:236
int wdc_set_io_enabled(struct wdc_data *d, int io_enabled)
Definition: dev_wdc.cc:119
#define PCI_MAPREG_TYPE_IO
Definition: pcireg.h:357
#define PCI_VENDOR_SYMPHONY
Definition: bus_pci.cc:1058
int machine_type
Definition: machine.h:111
void dev_vga_init(struct machine *machine, struct memory *mem, uint64_t videomem_base, uint64_t control_base, const char *name)
Definition: dev_vga.cc:1187
#define PCI_INTERRUPT_REG
Definition: pcireg.h:445
PCIINIT(igsfb)
Definition: bus_pci.cc:409
#define PCI_PRODUCT_DEC_21030
Definition: bus_pci.cc:1293
#define PCI_PRODUCT_ALI_M5229
Definition: bus_pci.cc:462
#define MEM_READ
Definition: memory.h:116
void bus_pci_add(struct machine *machine, struct pci_data *pci_data, struct memory *mem, int bus, int device, int function, const char *name)
Definition: bus_pci.cc:217
#define PCI_VENDOR_INTEL
Definition: bus_pci.cc:681
#define PCI_SUBCLASS_BRIDGE_HOST
Definition: pcireg.h:213
#define PCI_PRODUCT_ALI_M1543
Definition: bus_pci.cc:461
#define MACHINE_NETWINDER
Definition: machine.h:242
#define PCI_ID_CODE(vid, pid)
Definition: pcireg.h:73
#define PCI_PRODUCT_MOT_MPC105
Definition: bus_pci.cc:1349
#define reg(x)
#define PCI_VENDOR_REALTEK
Definition: bus_pci.cc:1171
#define PCI_PRODUCT_INTEL_82371SB_ISA
Definition: bus_pci.cc:683
#define PCI_VENDOR_VIATECH
Definition: bus_pci.cc:957
#define BUS_ISA_PCKBC_FORCE_USE
Definition: bus_isa.h:63
#define PCI_PRODUCT_VIATECH_VT82C586_IDE
Definition: bus_pci.cc:958
#define PCI_PRODUCT_INTEL_SIO
Definition: bus_pci.cc:687
void * device_add(struct machine *machine, const char *name_and_params)
Definition: device.cc:252
#define MACHINE_ARC
Definition: machine.h:218
#define PCI_ID_REG
Definition: pcireg.h:58
#define PCI_CAPLISTPTR_REG
Definition: pcireg.h:412
#define DEV_RAM_MIRROR
Definition: devices.h:365
#define PCI_SUBCLASS_MASS_STORAGE_SCSI
Definition: pcireg.h:177
#define MACHINE_MVMEPPC
Definition: machine.h:230
#define MACHINE_CATS
Definition: machine.h:240
#define PCI_MAPREG_END
Definition: pcireg.h:347
#define PCI_PRODUCT_DEC_21142
Definition: bus_pci.cc:1217
#define PCI_PRODUCT_INTEL_31244
Definition: bus_pci.cc:682
#define CHECK_ALLOCATION(ptr)
Definition: misc.h:239
#define PCI_VENDOR_HEURICON
Definition: bus_pci.cc:931
int symphony_82c105_cfg_reg_write(struct pci_device *pd, int reg, uint32_t value)
Definition: bus_pci.cc:1088
#define PCI_COMMAND_STATUS_REG
Definition: pcireg.h:80
#define PCI_VENDOR_IBM
Definition: bus_pci.cc:910
#define DISKIMAGE_IDE
Definition: diskimage.h:41
#define PCI_VENDOR_MOT
Definition: bus_pci.cc:1348
int verbose
Definition: main.cc:77
#define PCI_PRODUCT_S3_VIRGE_DX
Definition: bus_pci.cc:438
void bus_pci_setaddr(struct cpu *cpu, struct pci_data *pci_data, int bus, int device, int function, int reg)
Definition: bus_pci.cc:197
u_short data
Definition: siireg.h:79
#define PCI_PRODUCT_GALILEO_GT64011
Definition: bus_pci.cc:592
#define PCI_CLASS_NETWORK
Definition: pcireg.h:154
#define PCI_MAPREG_START
Definition: pcireg.h:346
void dev_ram_init(struct machine *machine, uint64_t baseaddr, uint64_t length, int mode, uint64_t otheraddress, const char *name)
Definition: dev_ram.cc:134
#define MACHINE_LANDISK
Definition: machine.h:253
#define MACHINE_PREP
Definition: machine.h:228
#define PCI_CLASS_REG
Definition: pcireg.h:119
#define PCI_PRODUCT_GALILEO_GT64260
Definition: bus_pci.cc:594
#define MEM_WRITE
Definition: memory.h:117
#define PCI_PRODUCT_HEURICON_PMPPC
Definition: bus_pci.cc:932
void(*)(struct machine *machine, struct memory *mem, struct pci_device *pd) pci_lookup_initf(const char *name)
Definition: device.cc:136
void * wdc0
Definition: bus_pci.cc:786
#define PCI_SUBCLASS_DISPLAY_VGA
Definition: pcireg.h:196
#define PCI_CLASS_CODE(mainclass, subclass, interface)
Definition: pcireg.h:146
#define PCI_VENDOR_INTEGRAPHICS
Definition: bus_pci.cc:407
#define PCI_PRODUCT_SYMPHONY_82C105
Definition: bus_pci.cc:1060
#define debug
Definition: dev_adb.cc:57
#define PCI_COMMAND_MEM_ENABLE
Definition: pcireg.h:91
#define PCI_PRODUCT_APPLE_UNINORTH1
Definition: bus_pci.cc:1374
Definition: cpu.h:326
#define MACHINE_EVBMIPS
Definition: machine.h:219
int vt82c586_ide_cfg_reg_write(struct pci_device *pd, int reg, uint32_t value)
Definition: bus_pci.cc:991
#define PCI_VENDOR_ATI
Definition: bus_pci.cc:1417
#define PCI_CLASS_SYSTEM
Definition: pcireg.h:160
#define PCI_VENDOR_GALILEO
Definition: bus_pci.cc:591
struct bus_isa_data * bus_isa_init(struct machine *machine, char *interrupt_base_path, uint32_t bus_isa_flags, uint64_t isa_portbase, uint64_t isa_membase)
Definition: bus_isa.cc:174
#define PCI_PRODUCT_APPLE_GC
Definition: bus_pci.cc:1373
#define PCI_PRODUCT_SYMPHONY_83C553
Definition: bus_pci.cc:1059
#define PCI_VENDOR_ALI
Definition: bus_pci.cc:460
#define PCI_BHLC_REG
Definition: pcireg.h:309
#define CPC_IB_EXT1
Definition: cpc700reg.h:146
#define PCI_CLASS_DISPLAY
Definition: pcireg.h:155
#define PCI_PRODUCT_AMD_PCNET_PCI
Definition: bus_pci.cc:638
void bus_pci_decompose_1(uint32_t t, int *bus, int *dev, int *func, int *reg)
Definition: bus_pci.cc:77
#define PCI_PRODUCT_ADP_2940U
Definition: bus_pci.cc:529
#define PCI_VENDOR_APPLE
Definition: bus_pci.cc:1372
struct pci_data * bus_pci_init(struct machine *machine, const char *irq_path, uint64_t pci_actual_io_offset, uint64_t pci_actual_mem_offset, uint64_t pci_portbase, uint64_t pci_membase, const char *pci_irqbase, uint64_t isa_portbase, uint64_t isa_membase, const char *isa_irqbase)
Definition: bus_pci.cc:356
Definition: memory.h:75
#define PCI_SUBCLASS_NETWORK_ETHERNET
Definition: pcireg.h:186
#define PCI_PRODUCT_INTEL_82371AB_IDE
Definition: bus_pci.cc:686
#define PCI_SUBCLASS_BRIDGE_ISA
Definition: pcireg.h:214
#define PCI_SUBCLASS_MASS_STORAGE_IDE
Definition: pcireg.h:178
#define PCI_VENDOR_DEC
Definition: bus_pci.cc:1216
#define PCI_VENDOR_AMD
Definition: bus_pci.cc:637
#define MACHINE_PMPPC
Definition: machine.h:227
int piix_ide_cfg_reg_write(struct pci_device *pd, int reg, uint32_t value)
Definition: bus_pci.cc:790
#define MACHINE_IQ80321
Definition: machine.h:243
void bus_pci_data_access(struct cpu *cpu, struct pci_data *pci_data, uint64_t *data, int len, int writeflag)
Definition: bus_pci.cc:96
int piix_isa_cfg_reg_write(struct pci_device *pd, int reg, uint32_t value)
Definition: bus_pci.cc:726
#define PCI_PRODUCT_REALTEK_RT8139
Definition: bus_pci.cc:1172
#define PCI_PRODUCT_IBM_ISABRIDGE
Definition: bus_pci.cc:911
#define PCI_CLASS_MASS_STORAGE
Definition: pcireg.h:153
void * wdc1
Definition: bus_pci.cc:787
#define PCI_COMMAND_IO_ENABLE
Definition: pcireg.h:90
#define PCI_CLASS_BRIDGE
Definition: pcireg.h:158
#define BUS_ISA_PCKBC_NONPCSTYLE
Definition: bus_isa.h:64
#define COBALT_QUBE2_ID
const char * machine_name
Definition: machine.h:115
#define MACHINE_MACPPC
Definition: machine.h:229
#define PCI_PRODUCT_GALILEO_GT64120
Definition: bus_pci.cc:593
#define PCI_BHLC_CODE(bist, type, multi, latency, cacheline)
Definition: pcireg.h:336
#define PCI_PRODUCT_ATI_RADEON_9200_2
Definition: bus_pci.cc:1418

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