dev_sh4.cc Source File

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dev_sh4.cc
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1 /*
2  * Copyright (C) 2006-2011 Anders Gavare. All rights reserved.
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions are met:
6  *
7  * 1. Redistributions of source code must retain the above copyright
8  * notice, this list of conditions and the following disclaimer.
9  * 2. Redistributions in binary form must reproduce the above copyright
10  * notice, this list of conditions and the following disclaimer in the
11  * documentation and/or other materials provided with the distribution.
12  * 3. The name of the author may not be used to endorse or promote products
13  * derived from this software without specific prior written permission.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25  * SUCH DAMAGE.
26  *
27  *
28  * COMMENT: SH4-specific memory mapped registers (0xf0000000 - 0xffffffff)
29  *
30  * TODO: Among other things:
31  *
32  * x) Interrupt masks (msk register stuff). Are these really correct?
33  * x) BSC (Bus state controller).
34  * x) DMA: Right now there's a hack for Dreamcast emulation
35  * x) UBC (User Break Controller)
36  * x) ...
37  */
38 
39 #include <stdio.h>
40 #include <stdlib.h>
41 #include <string.h>
42 
43 #include "bus_pci.h"
44 #include "console.h"
45 #include "cpu.h"
46 #include "device.h"
47 #include "devices.h"
48 #include "interrupt.h"
49 #include "machine.h"
50 #include "memory.h"
51 #include "misc.h"
52 #include "sh4_dmacreg.h"
53 #include "timer.h"
54 
55 #include "thirdparty/sh4_bscreg.h"
56 #include "thirdparty/sh4_cache.h"
58 #include "thirdparty/sh4_intcreg.h"
59 #include "thirdparty/sh4_mmu.h"
60 #include "thirdparty/sh4_pcicreg.h"
61 #include "thirdparty/sh4_rtcreg.h"
62 #include "thirdparty/sh4_scifreg.h"
63 #include "thirdparty/sh4_scireg.h"
64 #include "thirdparty/sh4_tmureg.h"
65 
66 
67 #define SH4_REG_BASE 0xff000000
68 #define SH4_TICK_SHIFT 14
69 #define N_SH4_TIMERS 3
70 
71 /* PCI stuff: */
72 #define N_PCIC_REGS (0x224 / sizeof(uint32_t))
73 #define N_PCIC_IRQS 16
74 #define PCIC_REG(addr) ((addr - SH4_PCIC) / sizeof(uint32_t))
75 #define PCI_VENDOR_HITACHI 0x1054
76 #define PCI_PRODUCT_HITACHI_SH7751 0x3505
77 #define PCI_PRODUCT_HITACHI_SH7751R 0x350e
78 
79 #define SCIF_TX_FIFO_SIZE 16
80 #define SCIF_DELAYED_TX_VALUE 2 /* 2 to be safe, 1 = fast but buggy */
81 
82 #ifdef UNSTABLE_DEVEL
83 // #define SH4_DEBUG
84 /* #define debug fatal */
85 #endif
86 
87 // Clock/occilation related
88 #define SH4_CPG_FRQCR 0xffc00000 /* 16-bit */
89 #define SH4_CPG_STBCR 0xffc00004 /* 8-bit */
90 #define SH4_CPG_WTCNT 0xffc00008 /* 8/16-bit */
91 #define SH4_CPG_WTCSR 0xffc0000c /* 8/16-bit */
92 #define SH4_CPG_STBCR2 0xffc00010 /* 8-bit */
93 
94 
95 struct sh4_data {
96  /* Store Queues: */
97  uint8_t sq[32 * 2];
98 
99  /* SCIF (Serial controller): */
100  uint16_t scif_smr;
101  uint8_t scif_brr;
102  uint16_t scif_scr;
103  uint16_t scif_ssr;
104  uint16_t scif_fcr;
105  uint16_t scif_lsr;
114 
115  /* Bus State Controller: */
116  uint32_t bsc_bcr1;
117  uint16_t bsc_bcr2;
118  uint32_t bsc_wcr1;
119  uint32_t bsc_wcr2;
120  uint32_t bsc_wcr3;
121  uint32_t bsc_mcr;
122  uint16_t bsc_pcr;
123  uint16_t bsc_rtcsr;
124  uint16_t bsc_rtcor;
125  uint16_t bsc_rfcr;
126 
127  /* CPG: */
128  uint16_t cpg_frqcr;
129  uint8_t cpg_stbcr;
130  uint16_t cpg_wtcnt;
131  uint16_t cpg_wtcsr;
132  uint8_t cpg_stbcr2;
133 
134  /* GPIO: */
135  uint32_t pctra; /* Port Control Register A */
136  uint32_t pdtra; /* Port Data Register A */
137  uint32_t pctrb; /* Port Control Register B */
138  uint32_t pdtrb; /* Port Data Register B */
139  uint16_t bsc_gpioic;
140 
141  /* PCIC (PCI controller): */
145 
146  /* SCI (serial interface): */
149  uint8_t sci_scsptr;
150  uint8_t sci_curbyte;
151  uint8_t sci_cur_addr;
152 
153  /* SD-RAM: */
154  uint16_t sdmr2;
155  uint16_t sdmr3;
156 
157  /* Timer Management Unit: */
158  struct timer *sh4_timer;
159  struct interrupt timer_irq[4];
160  uint32_t tocr;
161  uint32_t tstr;
162  uint32_t tcnt[N_SH4_TIMERS];
163  uint32_t tcor[N_SH4_TIMERS];
164  uint32_t tcr[N_SH4_TIMERS];
167 
168  /* RTC: */
169  uint32_t rtc_reg[14]; /* Excluding rcr1 and rcr2 */
170  uint8_t rtc_rcr1;
171  uint8_t rtc_rcr2;
172 };
173 
174 
175 #define SH4_PSEUDO_TIMER_HZ 110.0
176 
177 
178 /*
179  * sh4_timer_tick():
180  *
181  * This function is called SH4_PSEUDO_TIMER_HZ times per real-world second.
182  * Its job is to update the SH4 timer counters, and if necessary, increase
183  * the number of pending interrupts.
184  *
185  * Also, RAM Refresh is also faked here.
186  */
187 static void sh4_timer_tick(struct timer *t, void *extra)
188 {
189  struct sh4_data *d = (struct sh4_data *) extra;
190  int i;
191 
192  /* Fake RAM refresh: */
193  d->bsc_rfcr ++;
194  if (d->bsc_rtcsr & (RTCSR_CMIE | RTCSR_OVIE)) {
195  fatal("sh4: RTCSR_CMIE | RTCSR_OVIE: TODO\n");
196  /* TODO: Implement refresh interrupts etc. */
197  exit(1);
198  }
199 
200  /* Timer interrupts: */
201  for (i=0; i<N_SH4_TIMERS; i++) {
202  int32_t old = d->tcnt[i];
203 
204  /* printf("tcnt[%i] = %08x tcor[%i] = %08x\n",
205  i, d->tcnt[i], i, d->tcor[i]); */
206 
207  /* Only update timers that are currently started: */
208  if (!(d->tstr & (TSTR_STR0 << i)))
209  continue;
210 
211  /* Update the current count: */
212  d->tcnt[i] -= (uint32_t) (d->timer_hz[i] / SH4_PSEUDO_TIMER_HZ);
213 
214  /* Has the timer underflowed? */
215  if ((int32_t)d->tcnt[i] < 0 && old >= 0) {
216  d->tcr[i] |= TCR_UNF;
217 
218  if (d->tcr[i] & TCR_UNIE)
219  d->timer_interrupts_pending[i] ++;
220 
221  /*
222  * Set tcnt[i] to tcor[i]. Note: Since this function
223  * is only called now and then, adding tcor[i] to
224  * tcnt[i] produces more correct values for long
225  * running timers.
226  */
227  d->tcnt[i] += d->tcor[i];
228 
229  /* At least make sure that tcnt is non-negative... */
230  if ((int32_t)d->tcnt[i] < 0)
231  d->tcnt[i] = 0;
232  }
233  }
234 }
235 
236 
237 static void sh4_pcic_interrupt_assert(struct interrupt *interrupt)
238 {
239  struct sh4_data *d = (struct sh4_data *) interrupt->extra;
240  INTERRUPT_ASSERT(d->cpu_pcic_interrupt[interrupt->line]);
241 }
242 static void sh4_pcic_interrupt_deassert(struct interrupt *interrupt)
243 {
244  struct sh4_data *d = (struct sh4_data *) interrupt->extra;
246 }
247 
248 
249 static void scif_reassert_interrupts(struct sh4_data *d)
250 {
251  int old_tx_asserted = d->scif_tx_irq_asserted;
252  int old_rx_asserted = d->scif_rx_irq_asserted;
253 
255  d->scif_scr & SCSCR2_RIE && d->scif_ssr & SCSSR2_DR;
256 
257  if (d->scif_rx_irq_asserted && !old_rx_asserted)
259  else if (!d->scif_rx_irq_asserted && old_rx_asserted)
261 
263  d->scif_scr & SCSCR2_TIE &&
265 
266  if (d->scif_tx_irq_asserted && !old_tx_asserted)
268  else if (!d->scif_tx_irq_asserted && old_tx_asserted)
270 }
271 
272 
274 {
275  struct sh4_data *d = (struct sh4_data *) extra;
276  unsigned int i;
277 
278  /*
279  * Serial controller interrupts:
280  *
281  * RX: Cause interrupt if any char is available.
282  * TX: Send entire TX FIFO contents, and interrupt.
283  */
285  d->scif_ssr |= SCSSR2_DR;
286  else
287  d->scif_ssr &= ~SCSSR2_DR;
288 
289  if (d->scif_delayed_tx) {
290  if (--d->scif_delayed_tx == 0) {
291  /* Send TX FIFO contents: */
292  for (i=0; i<d->scif_tx_fifo_cursize; i++)
294  d->scif_tx_fifo[i]);
295 
296  /* Clear FIFO: */
297  d->scif_tx_fifo_cursize = 0;
298 
299  /* Done sending; cause a transmit end interrupt: */
301  }
302  }
303 
304  scif_reassert_interrupts(d);
305 
306  /* Timer interrupts: */
307  for (i=0; i<N_SH4_TIMERS; i++)
308  if (d->timer_interrupts_pending[i] > 0) {
310  d->tcr[i] |= TCR_UNF;
311  }
312 }
313 
314 
315 /*
316  * sh4_dmac_transfer():
317  *
318  * Called whenever a DMA transfer is to be executed.
319  * Clears the lowest bit of the corresponding channel's CHCR when done.
320  */
321 void sh4_dmac_transfer(struct cpu *cpu, struct sh4_data *d, int channel)
322 {
323  /* According to the SH7760 manual, bits 31..29 are ignored in */
324  /* both the SAR and DAR. */
325  uint32_t sar = cpu->cd.sh.dmac_sar[channel] & 0x1fffffff;
326  uint32_t dar = cpu->cd.sh.dmac_dar[channel] & 0x1fffffff;
327  uint32_t count = cpu->cd.sh.dmac_tcr[channel] & 0x1fffffff;
328  uint32_t chcr = cpu->cd.sh.dmac_chcr[channel];
329  int transmit_size = 1;
330  int src_delta = 0, dst_delta = 0;
331  int cause_interrupt = chcr & CHCR_IE;
332 
333  /* DMAC not enabled? Then just return. */
334  if (!(chcr & CHCR_TD))
335  return;
336 
337  /* Transfer End already set? Then don't transfer again. */
338  if (chcr & CHCR_TE)
339  return;
340 
341  /* Special case: 0 means 16777216: */
342  if (count == 0)
343  count = 16777216;
344 
345  switch (chcr & CHCR_TS) {
346  case CHCR_TS_8BYTE: transmit_size = 8; break;
347  case CHCR_TS_1BYTE: transmit_size = 1; break;
348  case CHCR_TS_2BYTE: transmit_size = 2; break;
349  case CHCR_TS_4BYTE: transmit_size = 4; break;
350  case CHCR_TS_32BYTE: transmit_size = 32; break;
351  default: fatal("Unimplemented transmit size?! CHCR[%i] = 0x%08x\n",
352  channel, chcr);
353  exit(1);
354  }
355 
356  switch (chcr & CHCR_DM) {
357  case CHCR_DM_FIXED: dst_delta = 0; break;
358  case CHCR_DM_INCREMENTED: dst_delta = 1; break;
359  case CHCR_DM_DECREMENTED: dst_delta = -1; break;
360  default: fatal("Unimplemented destination delta?! CHCR[%i] = 0x%08x\n",
361  channel, chcr);
362  exit(1);
363  }
364 
365  switch (chcr & CHCR_SM) {
366  case CHCR_SM_FIXED: src_delta = 0; break;
367  case CHCR_SM_INCREMENTED: src_delta = 1; break;
368  case CHCR_SM_DECREMENTED: src_delta = -1; break;
369  default: fatal("Unimplemented source delta?! CHCR[%i] = 0x%08x\n",
370  channel, chcr);
371  exit(1);
372  }
373 
374  src_delta *= transmit_size;
375  dst_delta *= transmit_size;
376 
377 #ifdef SH4_DEBUG
378  fatal("|SH4 DMA transfer, channel %i\n", channel);
379  fatal("|Source addr: 0x%08x (delta %i)\n", (int) sar, src_delta);
380  fatal("|Destination addr: 0x%08x (delta %i)\n", (int) dar, dst_delta);
381  fatal("|Count: 0x%08x\n", (int) count);
382  fatal("|Transmit size: 0x%08x\n", (int) transmit_size);
383  fatal("|Interrupt: %s\n", cause_interrupt? "yes" : "no");
384 #endif
385 
386  switch (chcr & CHCR_RS) {
387  case 0x200:
388  /*
389  * Single Address Mode
390  * External Address Space => external device
391  */
392 
393  // Avoid compiler warnings about unused sar and dar.
394  (void)sar;
395  (void)dar;
396 
397  /* Note: No transfer is done here! It is up to the
398  external device to do the transfer itself! */
399  break;
400 
401  default:fatal("Unimplemented SH4 RS DMAC: 0x%08x\n",
402  (int) (chcr & CHCR_RS));
403  exit(1);
404  }
405 
406  if (cause_interrupt) {
407  fatal("TODO: sh4 dmac interrupt!\n");
408  exit(1);
409  }
410 }
411 
412 
413 /*
414  * sh4_sci_cmd():
415  *
416  * Handle a SCI command byte.
417  *
418  * Bit: Meaning:
419  * 7 Ignored (usually 1?)
420  * 6 0=Write, 1=Read
421  * 5 AD: Address transfer
422  * 4 DT: Data transfer
423  * 3..0 Data or address bits
424  */
425 static void sh4_sci_cmd(struct sh4_data *d, struct cpu *cpu)
426 {
427  uint8_t cmd = d->sci_curbyte;
428  int writeflag = cmd & 0x40? 0 : 1;
429  int address_transfer;
430 
431  /* fatal("[ CMD BYTE %02x ]\n", cmd); */
432 
433  if (!(cmd & 0x80)) {
434  fatal("SCI cmd bit 7 not set? TODO\n");
435  exit(1);
436  }
437 
438  if ((cmd & 0x30) == 0x20)
439  address_transfer = 1;
440  else if ((cmd & 0x30) == 0x10)
441  address_transfer = 0;
442  else {
443  fatal("SCI: Neither data nor address transfer? TODO\n");
444  exit(1);
445  }
446 
447  if (address_transfer)
448  d->sci_cur_addr = cmd & 0x0f;
449 
450  if (!writeflag) {
451  /* Read data from the current address: */
452  uint8_t data_byte;
453 
454  cpu->memory_rw(cpu, cpu->mem, SCI_DEVICE_BASE + d->sci_cur_addr,
455  &data_byte, 1, MEM_READ, PHYSICAL);
456 
457  debug("[ SCI: read addr=%x data=%x ]\n",
458  d->sci_cur_addr, data_byte);
459 
460  d->sci_curbyte = data_byte;
461 
462  /* Set bit 7 right away: */
463  d->sci_scsptr &= ~SCSPTR_SPB1DT;
464  if (data_byte & 0x80)
466  }
467 
468  if (writeflag && !address_transfer) {
469  /* Write the 4 data bits to the current address: */
470  uint8_t data_byte = cmd & 0x0f;
471 
472  debug("[ SCI: write addr=%x data=%x ]\n",
473  d->sci_cur_addr, data_byte);
474 
475  cpu->memory_rw(cpu, cpu->mem, SCI_DEVICE_BASE + d->sci_cur_addr,
476  &data_byte, 1, MEM_WRITE, PHYSICAL);
477  }
478 }
479 
480 
481 /*
482  * sh4_sci_access():
483  *
484  * Reads or writes a bit via the SH4's serial interface. If writeflag is
485  * non-zero, input is used. If writeflag is zero, a bit is outputed as
486  * the return value from this function.
487  */
488 static uint8_t sh4_sci_access(struct sh4_data *d, struct cpu *cpu,
489  int writeflag, uint8_t input)
490 {
491  if (writeflag) {
492  /* WRITE: */
493  int clockpulse;
494  uint8_t old = d->sci_scsptr;
495  d->sci_scsptr = input;
496 
497  /*
498  * Clock pulse (SCSPTR_SPB0DT going from 0 to 1,
499  * when SCSPTR_SPB0IO was already set):
500  */
501  clockpulse = old & SCSPTR_SPB0IO &&
502  d->sci_scsptr & SCSPTR_SPB0DT &&
503  !(old & SCSPTR_SPB0DT);
504 
505  if (!clockpulse)
506  return 0;
507 
508  /* Are we in output or input mode? */
509  if (d->sci_scsptr & SCSPTR_SPB1IO) {
510  /* Output: */
511  int bit = d->sci_scsptr & SCSPTR_SPB1DT? 1 : 0;
512  d->sci_curbyte <<= 1;
513  d->sci_curbyte |= bit;
514  d->sci_bits_outputed ++;
515  if (d->sci_bits_outputed == 8) {
516  /* 4 control bits and 4 address/data bits have
517  been written. */
518  sh4_sci_cmd(d, cpu);
519  d->sci_bits_outputed = 0;
520  }
521  } else {
522  /* Input: */
523  int bit;
524  d->sci_bits_read ++;
525  d->sci_bits_read &= 7;
526 
527  bit = d->sci_curbyte & (0x80 >> d->sci_bits_read);
528 
529  d->sci_scsptr &= ~SCSPTR_SPB1DT;
530  if (bit)
532  }
533 
534  /* Return (value doesn't matter). */
535  return 0;
536  } else {
537  /* READ: */
538  return d->sci_scsptr;
539  }
540 }
541 
542 
543 DEVICE_ACCESS(sh4_itlb_aa)
544 {
545  uint64_t idata = 0, odata = 0;
546  int e = (relative_addr & SH4_ITLB_E_MASK) >> SH4_ITLB_E_SHIFT;
547 
548  if (writeflag == MEM_WRITE) {
549  int safe_to_invalidate = 0;
550  uint32_t old_hi = cpu->cd.sh.itlb_hi[e];
551  if ((cpu->cd.sh.itlb_lo[e] & SH4_PTEL_SZ_MASK)==SH4_PTEL_SZ_4K)
552  safe_to_invalidate = 1;
553 
554  idata = memory_readmax64(cpu, data, len);
555  cpu->cd.sh.itlb_hi[e] &=
557  cpu->cd.sh.itlb_hi[e] |= (idata &
559  cpu->cd.sh.itlb_lo[e] &= ~SH4_PTEL_V;
560  if (idata & SH4_ITLB_AA_V)
561  cpu->cd.sh.itlb_lo[e] |= SH4_PTEL_V;
562 
563  /* Invalidate if this ITLB entry previously belonged to the
564  currently running process, or if it was shared: */
565  if (cpu->cd.sh.ptel & SH4_PTEL_SH ||
566  (old_hi & SH4_ITLB_AA_ASID_MASK) ==
567  (cpu->cd.sh.pteh & SH4_PTEH_ASID_MASK)) {
568  if (safe_to_invalidate)
570  old_hi & ~0xfff, INVALIDATE_VADDR);
571  else
573  0, INVALIDATE_ALL);
574  }
575  } else {
576  odata = cpu->cd.sh.itlb_hi[e] &
578  if (cpu->cd.sh.itlb_lo[e] & SH4_PTEL_V)
579  odata |= SH4_ITLB_AA_V;
580  memory_writemax64(cpu, data, len, odata);
581  }
582 
583  return 1;
584 }
585 
586 
587 DEVICE_ACCESS(sh4_itlb_da1)
588 {
589  uint32_t mask = SH4_PTEL_SH | SH4_PTEL_C | SH4_PTEL_SZ_MASK |
590  SH4_PTEL_PR_MASK | SH4_PTEL_V | 0x1ffffc00;
591  uint64_t idata = 0, odata = 0;
592  int e = (relative_addr & SH4_ITLB_E_MASK) >> SH4_ITLB_E_SHIFT;
593 
594  if (relative_addr & 0x800000) {
595  fatal("sh4_itlb_da1: TODO: da2 area\n");
596  exit(1);
597  }
598 
599  if (writeflag == MEM_WRITE) {
600  uint32_t old_lo = cpu->cd.sh.itlb_lo[e];
601  int safe_to_invalidate = 0;
602  if ((cpu->cd.sh.itlb_lo[e] & SH4_PTEL_SZ_MASK)==SH4_PTEL_SZ_4K)
603  safe_to_invalidate = 1;
604 
605  idata = memory_readmax64(cpu, data, len);
606  cpu->cd.sh.itlb_lo[e] &= ~mask;
607  cpu->cd.sh.itlb_lo[e] |= (idata & mask);
608 
609  /* Invalidate if this ITLB entry belongs to the
610  currently running process, or if it was shared: */
611  if (old_lo & SH4_PTEL_SH ||
612  (cpu->cd.sh.itlb_hi[e] & SH4_ITLB_AA_ASID_MASK) ==
613  (cpu->cd.sh.pteh & SH4_PTEH_ASID_MASK)) {
614  if (safe_to_invalidate)
616  cpu->cd.sh.itlb_hi[e] & ~0xfff,
618  else
620  0, INVALIDATE_ALL);
621  }
622  } else {
623  odata = cpu->cd.sh.itlb_lo[e] & mask;
624  memory_writemax64(cpu, data, len, odata);
625  }
626 
627  return 1;
628 }
629 
630 
631 DEVICE_ACCESS(sh4_utlb_aa)
632 {
633  uint64_t idata = 0, odata = 0;
634  int i, e = (relative_addr & SH4_UTLB_E_MASK) >> SH4_UTLB_E_SHIFT;
635  int a = relative_addr & SH4_UTLB_A;
636 
637  if (writeflag == MEM_WRITE) {
638  int n_hits = 0;
639  int safe_to_invalidate = 0;
640  uint32_t vaddr_to_invalidate = 0;
641 
642  idata = memory_readmax64(cpu, data, len);
643  if (a) {
644  for (i=-SH_N_ITLB_ENTRIES; i<SH_N_UTLB_ENTRIES; i++) {
645  uint32_t lo, hi;
646  uint32_t mask = 0xfffff000;
647  int sh;
648 
649  if (i < 0) {
650  lo = cpu->cd.sh.itlb_lo[
651  i + SH_N_ITLB_ENTRIES];
652  hi = cpu->cd.sh.itlb_hi[
653  i + SH_N_ITLB_ENTRIES];
654  } else {
655  lo = cpu->cd.sh.utlb_lo[i];
656  hi = cpu->cd.sh.utlb_hi[i];
657  }
658 
659  sh = lo & SH4_PTEL_SH;
660  if (!(lo & SH4_PTEL_V))
661  continue;
662 
663  switch (lo & SH4_PTEL_SZ_MASK) {
664  case SH4_PTEL_SZ_1K: mask = 0xfffffc00; break;
665  case SH4_PTEL_SZ_64K: mask = 0xffff0000; break;
666  case SH4_PTEL_SZ_1M: mask = 0xfff00000; break;
667  }
668 
669  if ((hi & mask) != (idata & mask))
670  continue;
671 
672  if ((lo & SH4_PTEL_SZ_MASK) ==
673  SH4_PTEL_SZ_4K) {
674  safe_to_invalidate = 1;
675  vaddr_to_invalidate = hi & mask;
676  }
677 
678  if (!sh && (hi & SH4_PTEH_ASID_MASK) !=
679  (cpu->cd.sh.pteh & SH4_PTEH_ASID_MASK))
680  continue;
681 
682  if (i < 0) {
683  cpu->cd.sh.itlb_lo[i +
684  SH_N_ITLB_ENTRIES] &= ~SH4_PTEL_V;
685  if (idata & SH4_UTLB_AA_V)
686  cpu->cd.sh.itlb_lo[
687  i+SH_N_ITLB_ENTRIES] |=
688  SH4_PTEL_V;
689  } else {
690  cpu->cd.sh.utlb_lo[i] &=
691  ~(SH4_PTEL_D | SH4_PTEL_V);
692  if (idata & SH4_UTLB_AA_D)
693  cpu->cd.sh.utlb_lo[i] |=
694  SH4_PTEL_D;
695  if (idata & SH4_UTLB_AA_V)
696  cpu->cd.sh.utlb_lo[i] |=
697  SH4_PTEL_V;
698  }
699 
700  if (i >= 0)
701  n_hits ++;
702  }
703 
704  if (n_hits > 1)
705  sh_exception(cpu,
707  } else {
708  if ((cpu->cd.sh.utlb_lo[e] & SH4_PTEL_SZ_MASK) ==
709  SH4_PTEL_SZ_4K) {
710  safe_to_invalidate = 1;
711  vaddr_to_invalidate =
712  cpu->cd.sh.utlb_hi[e] & ~0xfff;
713  }
714 
715  cpu->cd.sh.utlb_hi[e] &=
717  cpu->cd.sh.utlb_hi[e] |= (idata &
719 
720  cpu->cd.sh.utlb_lo[e] &= ~(SH4_PTEL_D | SH4_PTEL_V);
721  if (idata & SH4_UTLB_AA_D)
722  cpu->cd.sh.utlb_lo[e] |= SH4_PTEL_D;
723  if (idata & SH4_UTLB_AA_V)
724  cpu->cd.sh.utlb_lo[e] |= SH4_PTEL_V;
725  }
726 
727  if (safe_to_invalidate)
729  vaddr_to_invalidate, INVALIDATE_VADDR);
730  else
731  cpu->invalidate_translation_caches(cpu, 0,
733  } else {
734  odata = cpu->cd.sh.utlb_hi[e] &
736  if (cpu->cd.sh.utlb_lo[e] & SH4_PTEL_D)
737  odata |= SH4_UTLB_AA_D;
738  if (cpu->cd.sh.utlb_lo[e] & SH4_PTEL_V)
739  odata |= SH4_UTLB_AA_V;
740  memory_writemax64(cpu, data, len, odata);
741  }
742 
743  return 1;
744 }
745 
746 
747 DEVICE_ACCESS(sh4_utlb_da1)
748 {
749  uint32_t mask = SH4_PTEL_WT | SH4_PTEL_SH | SH4_PTEL_D | SH4_PTEL_C
750  | SH4_PTEL_SZ_MASK | SH4_PTEL_PR_MASK | SH4_PTEL_V | 0x1ffffc00;
751  uint64_t idata = 0, odata = 0;
752  int e = (relative_addr & SH4_UTLB_E_MASK) >> SH4_UTLB_E_SHIFT;
753 
754  if (relative_addr & 0x800000) {
755  fatal("sh4_utlb_da1: TODO: da2 area\n");
756  exit(1);
757  }
758 
759  if (writeflag == MEM_WRITE) {
760  uint32_t old_lo = cpu->cd.sh.utlb_lo[e];
761  int safe_to_invalidate = 0;
762  if ((cpu->cd.sh.utlb_lo[e] & SH4_PTEL_SZ_MASK)==SH4_PTEL_SZ_4K)
763  safe_to_invalidate = 1;
764 
765  idata = memory_readmax64(cpu, data, len);
766  cpu->cd.sh.utlb_lo[e] &= ~mask;
767  cpu->cd.sh.utlb_lo[e] |= (idata & mask);
768 
769  /* Invalidate if this UTLB entry belongs to the
770  currently running process, or if it was shared: */
771  if (old_lo & SH4_PTEL_SH ||
772  (cpu->cd.sh.utlb_hi[e] & SH4_ITLB_AA_ASID_MASK) ==
773  (cpu->cd.sh.pteh & SH4_PTEH_ASID_MASK)) {
774  if (safe_to_invalidate)
776  cpu->cd.sh.utlb_hi[e] & ~0xfff,
778  else
780  0, INVALIDATE_ALL);
781  }
782  } else {
783  odata = cpu->cd.sh.utlb_lo[e] & mask;
784  memory_writemax64(cpu, data, len, odata);
785  }
786 
787  return 1;
788 }
789 
790 
791 DEVICE_ACCESS(sh4_pcic)
792 {
793  struct sh4_data *d = (struct sh4_data *) extra;
794  uint64_t idata = 0, odata = 0;
795 
796  if (writeflag == MEM_WRITE)
797  idata = memory_readmax64(cpu, data, len);
798 
799  relative_addr += SH4_PCIC;
800 
801  /* Register read/write: */
802  if (writeflag == MEM_WRITE)
803  d->pcic_reg[PCIC_REG(relative_addr)] = idata;
804  else
805  odata = d->pcic_reg[PCIC_REG(relative_addr)];
806 
807  /* Special cases: */
808 
809  switch (relative_addr) {
810 
811  case SH4_PCICONF0:
812  if (writeflag == MEM_WRITE) {
813  fatal("[ sh4_pcic: TODO: Write to SH4_PCICONF0? ]\n");
814  exit(1);
815  } else {
816  if (strcmp(cpu->cd.sh.cpu_type.name, "SH7751") == 0) {
819  } else if (strcmp(cpu->cd.sh.cpu_type.name,
820  "SH7751R") == 0) {
823  } else {
824  fatal("sh4_pcic: TODO: PCICONF0 read for"
825  " unimplemented CPU type?\n");
826  exit(1);
827  }
828  }
829  break;
830 
831  case SH4_PCICONF1:
832  case SH4_PCICONF2:
833  case SH4_PCICR:
834  case SH4_PCIBCR1:
835  case SH4_PCIBCR2:
836  case SH4_PCIBCR3:
837  case SH4_PCIWCR1:
838  case SH4_PCIWCR2:
839  case SH4_PCIWCR3:
840  case SH4_PCIMCR:
841  break;
842 
843  case SH4_PCICONF5:
844  /* Hardcoded to what OpenBSD/landisk uses: */
845  if (writeflag == MEM_WRITE && idata != 0xac000000) {
846  fatal("sh4_pcic: SH4_PCICONF5 unknown value"
847  " 0x%" PRIx32"\n", (uint32_t) idata);
848  exit(1);
849  }
850  break;
851 
852  case SH4_PCICONF6:
853  /* Hardcoded to what OpenBSD/landisk uses: */
854  if (writeflag == MEM_WRITE && idata != 0x8c000000) {
855  fatal("sh4_pcic: SH4_PCICONF6 unknown value"
856  " 0x%" PRIx32"\n", (uint32_t) idata);
857  exit(1);
858  }
859  break;
860 
861  case SH4_PCILSR0:
862  /* Hardcoded to what OpenBSD/landisk uses: */
863  if (writeflag == MEM_WRITE && idata != ((64 - 1) << 20)) {
864  fatal("sh4_pcic: SH4_PCILSR0 unknown value"
865  " 0x%" PRIx32"\n", (uint32_t) idata);
866  exit(1);
867  }
868  break;
869 
870  case SH4_PCILAR0:
871  /* Hardcoded to what OpenBSD/landisk uses: */
872  if (writeflag == MEM_WRITE && idata != 0xac000000) {
873  fatal("sh4_pcic: SH4_PCILAR0 unknown value"
874  " 0x%" PRIx32"\n", (uint32_t) idata);
875  exit(1);
876  }
877  break;
878 
879  case SH4_PCILSR1:
880  /* Hardcoded to what OpenBSD/landisk uses: */
881  if (writeflag == MEM_WRITE && idata != ((64 - 1) << 20)) {
882  fatal("sh4_pcic: SH4_PCILSR1 unknown value"
883  " 0x%" PRIx32"\n", (uint32_t) idata);
884  exit(1);
885  }
886  break;
887 
888  case SH4_PCILAR1:
889  /* Hardcoded to what OpenBSD/landisk uses: */
890  if (writeflag == MEM_WRITE && idata != 0xac000000) {
891  fatal("sh4_pcic: SH4_PCILAR1 unknown value"
892  " 0x%" PRIx32"\n", (uint32_t) idata);
893  exit(1);
894  }
895  break;
896 
897  case SH4_PCIMBR:
898  if (writeflag == MEM_WRITE && idata != SH4_PCIC_MEM) {
899  fatal("sh4_pcic: PCIMBR set to 0x%" PRIx32", not"
900  " 0x%" PRIx32"? TODO\n", (uint32_t) idata,
901  (uint32_t) SH4_PCIC_MEM);
902  exit(1);
903  }
904  break;
905 
906  case SH4_PCIIOBR:
907  if (writeflag == MEM_WRITE && idata != SH4_PCIC_IO) {
908  fatal("sh4_pcic: PCIIOBR set to 0x%" PRIx32", not"
909  " 0x%" PRIx32"? TODO\n", (uint32_t) idata,
910  (uint32_t) SH4_PCIC_IO);
911  exit(1);
912  }
913  break;
914 
915  case SH4_PCIPAR:
916  /* PCI bus access Address Register: */
917  {
918  int bus = (idata >> 16) & 0xff;
919  int dev = (idata >> 11) & 0x1f;
920  int func = (idata >> 8) & 7;
921  int reg = idata & 0xff;
922  bus_pci_setaddr(cpu, d->pci_data, bus, dev, func, reg);
923  }
924  break;
925 
926  case SH4_PCIPDR:
927  /* PCI bus access Data Register: */
928  bus_pci_data_access(cpu, d->pci_data, writeflag == MEM_READ?
929  &odata : &idata, len, writeflag);
930  break;
931 
932  default:if (writeflag == MEM_READ) {
933  fatal("[ sh4_pcic: read from addr 0x%x: TODO ]\n",
934  (int)relative_addr);
935  } else {
936  fatal("[ sh4_pcic: write to addr 0x%x: 0x%x: TODO ]\n",
937  (int)relative_addr, (int)idata);
938  }
939  exit(1);
940  }
941 
942  if (writeflag == MEM_READ)
943  memory_writemax64(cpu, data, len, odata);
944 
945  return 1;
946 }
947 
948 
950 {
951  struct sh4_data *d = (struct sh4_data *) extra;
952  size_t i;
953 
954  if (writeflag == MEM_WRITE) {
955  for (i=0; i<len; i++)
956  d->sq[(relative_addr + i) % sizeof(d->sq)] = data[i];
957  } else {
958  for (i=0; i<len; i++)
959  data[i] = d->sq[(relative_addr + i) % sizeof(d->sq)];
960  }
961 
962  return 1;
963 }
964 
965 
967 {
968  struct sh4_data *d = (struct sh4_data *) extra;
969  uint64_t idata = 0, odata = 0;
970  int timer_nr = 0, dma_channel = 0;
971 
972  if (writeflag == MEM_WRITE)
973  idata = memory_readmax64(cpu, data, len);
974 
975  relative_addr += SH4_REG_BASE;
976 
977  /* SD-RAM access uses address only: */
978  if (relative_addr >= 0xff900000 && relative_addr <= 0xff97ffff) {
979  /* Possibly not 100% correct... TODO */
980  int v = (relative_addr >> 2) & 0xffff;
981  if (relative_addr & 0x00040000)
982  d->sdmr3 = v;
983  else
984  d->sdmr2 = v;
985  debug("[ sh4: sdmr%i set to 0x%04" PRIx16" ]\n",
986  relative_addr & 0x00040000? 3 : 2, v);
987  return 1;
988  }
989 
990 
991  switch (relative_addr) {
992 
993  /*************************************************/
994 
995  case SH4_PVR_ADDR:
996  odata = cpu->cd.sh.cpu_type.pvr;
997  break;
998 
999  case SH4_PRR_ADDR:
1000  odata = cpu->cd.sh.cpu_type.prr;
1001  break;
1002 
1003  case SH4_PTEH:
1004  if (writeflag == MEM_READ)
1005  odata = cpu->cd.sh.pteh;
1006  else {
1007  unsigned int old_asid = cpu->cd.sh.pteh
1009  cpu->cd.sh.pteh = idata;
1010 
1011  if ((idata & SH4_PTEH_ASID_MASK) != old_asid) {
1012  /*
1013  * TODO: Don't invalidate everything,
1014  * only those pages that belonged to the
1015  * old asid.
1016  */
1018  cpu, 0, INVALIDATE_ALL);
1019  }
1020  }
1021  break;
1022 
1023  case SH4_PTEL:
1024  if (writeflag == MEM_READ)
1025  odata = cpu->cd.sh.ptel;
1026  else
1027  cpu->cd.sh.ptel = idata;
1028  break;
1029 
1030  case SH4_TTB:
1031  if (writeflag == MEM_READ)
1032  odata = cpu->cd.sh.ttb;
1033  else
1034  cpu->cd.sh.ttb = idata;
1035  break;
1036 
1037  case SH4_TEA:
1038  if (writeflag == MEM_READ)
1039  odata = cpu->cd.sh.tea;
1040  else
1041  cpu->cd.sh.tea = idata;
1042  break;
1043 
1044  case SH4_PTEA:
1045  if (writeflag == MEM_READ)
1046  odata = cpu->cd.sh.ptea;
1047  else
1048  cpu->cd.sh.ptea = idata;
1049  break;
1050 
1051  case SH4_MMUCR:
1052  if (writeflag == MEM_READ) {
1053  odata = cpu->cd.sh.mmucr;
1054  } else {
1055  if (idata & SH4_MMUCR_TI) {
1056  /* TLB invalidate. */
1057  int i;
1058  for (i = 0; i < SH_N_ITLB_ENTRIES; i++)
1059  cpu->cd.sh.itlb_lo[i] &=
1060  ~SH4_PTEL_V;
1061 
1062  for (i = 0; i < SH_N_UTLB_ENTRIES; i++)
1063  cpu->cd.sh.utlb_lo[i] &=
1064  ~SH4_PTEL_V;
1065 
1067  0, INVALIDATE_ALL);
1068 
1069  /* The TI bit should always read as 0. */
1070  idata &= ~SH4_MMUCR_TI;
1071  }
1072 
1073  cpu->cd.sh.mmucr = idata;
1074  }
1075  break;
1076 
1077  case SH4_CCR:
1078  if (writeflag == MEM_READ) {
1079  odata = cpu->cd.sh.ccr;
1080  } else {
1081  cpu->cd.sh.ccr = idata;
1082  }
1083  break;
1084 
1085  case SH4_QACR0:
1086  if (writeflag == MEM_READ) {
1087  odata = cpu->cd.sh.qacr0;
1088  } else {
1089  cpu->cd.sh.qacr0 = idata;
1090  }
1091  break;
1092 
1093  case SH4_QACR1:
1094  if (writeflag == MEM_READ) {
1095  odata = cpu->cd.sh.qacr1;
1096  } else {
1097  cpu->cd.sh.qacr1 = idata;
1098  }
1099  break;
1100 
1101  case SH4_TRA:
1102  if (writeflag == MEM_READ)
1103  odata = cpu->cd.sh.tra;
1104  else
1105  cpu->cd.sh.tra = idata;
1106  break;
1107 
1108  case SH4_EXPEVT:
1109  if (writeflag == MEM_READ)
1110  odata = cpu->cd.sh.expevt;
1111  else
1112  cpu->cd.sh.expevt = idata;
1113  break;
1114 
1115  case SH4_INTEVT:
1116  if (writeflag == MEM_READ)
1117  odata = cpu->cd.sh.intevt;
1118  else
1119  cpu->cd.sh.intevt = idata;
1120  break;
1121 
1122 
1123  /********************************/
1124  /* UBC: User Break Controller */
1125 
1126  case 0xff000014: /* SH4_UBC_BASRA */
1127  case 0xff000018: /* SH4_UBC_BASRB */
1128 
1129  case 0xff200000: /* SH4_UBC_BARA */
1130  case 0xff200004: /* SH4_UBC_BAMRA */
1131  case 0xff200008: /* SH4_UBC_BBRA */
1132  case 0xff20000c: /* SH4_UBC_BARB */
1133  case 0xff200010: /* SH4_UBC_BAMRB */
1134  case 0xff200014: /* SH4_UBC_BBRB */
1135  case 0xff200018: /* SH4_UBC_BDRB */
1136  case 0xff20001c: /* SH4_UBC_BDMRB */
1137  case 0xff200020: /* SH4_UBC_BRCR */
1138  /* TODO */
1139  break;
1140 
1141 
1142  /********************************/
1143  /* TMU: Timer Management Unit */
1144 
1145  case SH4_TOCR:
1146  /* Timer Output Control Register */
1147  if (writeflag == MEM_WRITE) {
1148  d->tocr = idata;
1149  if (idata & TOCR_TCOE)
1150  fatal("[ sh4 timer: TCOE not yet "
1151  "implemented ]\n");
1152  } else {
1153  odata = d->tocr;
1154  }
1155  break;
1156 
1157  case SH4_TSTR:
1158  /* Timer Start Register */
1159  if (writeflag == MEM_READ) {
1160  odata = d->tstr;
1161  } else {
1162  if (idata & 1 && !(d->tstr & 1))
1163  debug("[ sh4 timer: starting timer 0 ]\n");
1164  if (idata & 2 && !(d->tstr & 2))
1165  debug("[ sh4 timer: starting timer 1 ]\n");
1166  if (idata & 4 && !(d->tstr & 4))
1167  debug("[ sh4 timer: starting timer 2 ]\n");
1168  if (!(idata & 1) && d->tstr & 1)
1169  debug("[ sh4 timer: stopping timer 0 ]\n");
1170  if (!(idata & 2) && d->tstr & 2)
1171  debug("[ sh4 timer: stopping timer 1 ]\n");
1172  if (!(idata & 4) && d->tstr & 4)
1173  debug("[ sh4 timer: stopping timer 2 ]\n");
1174  d->tstr = idata;
1175  }
1176  break;
1177 
1178  case SH4_TCOR2:
1179  timer_nr ++;
1180  case SH4_TCOR1:
1181  timer_nr ++;
1182  case SH4_TCOR0:
1183  /* Timer Constant Register */
1184  if (writeflag == MEM_READ)
1185  odata = d->tcor[timer_nr];
1186  else
1187  d->tcor[timer_nr] = idata;
1188  break;
1189 
1190  case SH4_TCNT2:
1191  timer_nr ++;
1192  case SH4_TCNT1:
1193  timer_nr ++;
1194  case SH4_TCNT0:
1195  /* Timer Counter Register */
1196  if (writeflag == MEM_READ)
1197  odata = d->tcnt[timer_nr];
1198  else
1199  d->tcnt[timer_nr] = idata;
1200  break;
1201 
1202  case SH4_TCR2:
1203  timer_nr ++;
1204  case SH4_TCR1:
1205  timer_nr ++;
1206  case SH4_TCR0:
1207  /* Timer Control Register */
1208  if (writeflag == MEM_READ) {
1209  odata = d->tcr[timer_nr];
1210  } else {
1211  if (cpu->cd.sh.pclock == 0) {
1212  fatal("INTERNAL ERROR: pclock must be set"
1213  " for this machine. Aborting.\n");
1214  exit(1);
1215  }
1216 
1217  switch (idata & 3) {
1218  case TCR_TPSC_P4:
1219  d->timer_hz[timer_nr] = cpu->cd.sh.pclock/4.0;
1220  break;
1221  case TCR_TPSC_P16:
1222  d->timer_hz[timer_nr] = cpu->cd.sh.pclock/16.0;
1223  break;
1224  case TCR_TPSC_P64:
1225  d->timer_hz[timer_nr] = cpu->cd.sh.pclock/64.0;
1226  break;
1227  case TCR_TPSC_P256:
1228  d->timer_hz[timer_nr] = cpu->cd.sh.pclock/256.0;
1229  break;
1230  }
1231 
1232  debug("[ sh4 timer %i clock set to %f Hz ]\n",
1233  timer_nr, d->timer_hz[timer_nr]);
1234 
1235  if (idata & (TCR_ICPF | TCR_ICPE1 | TCR_ICPE0 |
1236  TCR_CKEG1 | TCR_CKEG0 | TCR_TPSC2)) {
1237  fatal("Unimplemented SH4 timer control"
1238  " bits: 0x%08" PRIx32". Aborting.\n",
1239  (int) idata);
1240  exit(1);
1241  }
1242 
1243  INTERRUPT_DEASSERT(d->timer_irq[timer_nr]);
1244 
1245  if (d->tcr[timer_nr] & TCR_UNF && !(idata & TCR_UNF)) {
1246  if (d->timer_interrupts_pending[timer_nr] > 0)
1247  d->timer_interrupts_pending[timer_nr]--;
1248  }
1249 
1250  d->tcr[timer_nr] = idata;
1251  }
1252  break;
1253 
1254 
1255  /*************************************************/
1256  /* DMAC: DMA Controller */
1257  /* 4 channels on SH7750 */
1258  /* 8 channels on SH7760 */
1259 
1260  case SH4_SAR7: dma_channel ++;
1261  case SH4_SAR6: dma_channel ++;
1262  case SH4_SAR5: dma_channel ++;
1263  case SH4_SAR4: dma_channel ++;
1264  case SH4_SAR3: dma_channel ++;
1265  case SH4_SAR2: dma_channel ++;
1266  case SH4_SAR1: dma_channel ++;
1267  case SH4_SAR0:
1268  if (writeflag == MEM_READ)
1269  odata = cpu->cd.sh.dmac_sar[dma_channel];
1270  else
1271  cpu->cd.sh.dmac_sar[dma_channel] = idata;
1272  break;
1273 
1274  case SH4_DAR7: dma_channel ++;
1275  case SH4_DAR6: dma_channel ++;
1276  case SH4_DAR5: dma_channel ++;
1277  case SH4_DAR4: dma_channel ++;
1278  case SH4_DAR3: dma_channel ++;
1279  case SH4_DAR2: dma_channel ++;
1280  case SH4_DAR1: dma_channel ++;
1281  case SH4_DAR0:
1282  if (writeflag == MEM_READ)
1283  odata = cpu->cd.sh.dmac_dar[dma_channel];
1284  else
1285  cpu->cd.sh.dmac_dar[dma_channel] = idata;
1286  break;
1287 
1288  case SH4_DMATCR7: dma_channel ++;
1289  case SH4_DMATCR6: dma_channel ++;
1290  case SH4_DMATCR5: dma_channel ++;
1291  case SH4_DMATCR4: dma_channel ++;
1292  case SH4_DMATCR3: dma_channel ++;
1293  case SH4_DMATCR2: dma_channel ++;
1294  case SH4_DMATCR1: dma_channel ++;
1295  case SH4_DMATCR0:
1296  if (writeflag == MEM_READ)
1297  odata = cpu->cd.sh.dmac_tcr[dma_channel] & 0x00ffffff;
1298  else {
1299  if (idata & ~0x00ffffff) {
1300  fatal("[ SH4 DMA: Attempt to set top 8 "
1301  "bits of the count register? 0x%08"
1302  PRIx32" ]\n", (uint32_t) idata);
1303  exit(1);
1304  }
1305 
1306  cpu->cd.sh.dmac_tcr[dma_channel] = idata;
1307  }
1308  break;
1309 
1310  case SH4_CHCR7: dma_channel ++;
1311  case SH4_CHCR6: dma_channel ++;
1312  case SH4_CHCR5: dma_channel ++;
1313  case SH4_CHCR4: dma_channel ++;
1314  case SH4_CHCR3: dma_channel ++;
1315  case SH4_CHCR2: dma_channel ++;
1316  case SH4_CHCR1: dma_channel ++;
1317  case SH4_CHCR0:
1318  if (writeflag == MEM_READ) {
1319  odata = cpu->cd.sh.dmac_chcr[dma_channel];
1320  } else {
1321  /* CHCR_CHSET always reads back as 0: */
1322  idata &= ~CHCR_CHSET;
1323 
1324  cpu->cd.sh.dmac_chcr[dma_channel] = idata;
1325 
1326  /* Perform a transfer? */
1327  if (idata & CHCR_TD)
1328  sh4_dmac_transfer(cpu, d, dma_channel);
1329  }
1330  break;
1331 
1332  case SH4_DMAOR:
1333  if (writeflag == MEM_READ) {
1334  odata = cpu->cd.sh.dmaor;
1335  } else {
1336  // Only some bits are writable:
1337  idata &= (DMAOR_DDT | DMAOR_PR1 | DMAOR_PR0 | DMAOR_DME);
1338  cpu->cd.sh.dmaor = idata;
1339  }
1340  break;
1341 
1342  /*************************************************/
1343  /* BSC: Bus State Controller */
1344 
1345  case SH4_BCR1:
1346  if (writeflag == MEM_WRITE)
1347  d->bsc_bcr1 = idata & 0x033efffd;
1348  else {
1349  odata = d->bsc_bcr1;
1350  if (cpu->byte_order == EMUL_LITTLE_ENDIAN)
1351  odata |= BCR1_LITTLE_ENDIAN;
1352  }
1353  break;
1354 
1355  case SH4_BCR2:
1356  if (len != sizeof(uint16_t)) {
1357  fatal("Non-16-bit SH4_BCR2 access?\n");
1358  exit(1);
1359  }
1360  if (writeflag == MEM_WRITE)
1361  d->bsc_bcr2 = idata & 0x3ffd;
1362  else
1363  odata = d->bsc_bcr2;
1364  break;
1365 
1366  case SH4_WCR1:
1367  if (writeflag == MEM_WRITE)
1368  d->bsc_wcr1 = idata & 0x77777777;
1369  else
1370  odata = d->bsc_wcr1;
1371  break;
1372 
1373  case SH4_WCR2:
1374  if (writeflag == MEM_WRITE)
1375  d->bsc_wcr2 = idata & 0xfffeefff;
1376  else
1377  odata = d->bsc_wcr2;
1378  break;
1379 
1380  case SH4_WCR3:
1381  if (writeflag == MEM_WRITE)
1382  d->bsc_wcr3 = idata & 0x77777777;
1383  else
1384  odata = d->bsc_wcr3;
1385  break;
1386 
1387  case SH4_MCR:
1388  if (writeflag == MEM_WRITE)
1389  d->bsc_mcr = idata & 0xf8bbffff;
1390  else
1391  odata = d->bsc_mcr;
1392  break;
1393 
1394  case SH4_PCR:
1395  if (writeflag == MEM_WRITE)
1396  d->bsc_pcr = idata;
1397  else
1398  odata = d->bsc_pcr;
1399  break;
1400 
1401  case SH4_RTCSR:
1402  /*
1403  * Refresh Time Control/Status Register. Called RTCSR in
1404  * NetBSD, but RTSCR in the SH7750 manual?
1405  */
1406  if (writeflag == MEM_WRITE) {
1407  idata &= 0x00ff;
1408  if (idata & RTCSR_CMF) {
1409  idata = (idata & ~RTCSR_CMF)
1410  | (d->bsc_rtcsr & RTCSR_CMF);
1411  }
1412  d->bsc_rtcsr = idata & 0x00ff;
1413  } else
1414  odata = d->bsc_rtcsr;
1415  break;
1416 
1417  case SH4_RTCOR:
1418  /* Refresh Time Constant Register (8 bits): */
1419  if (writeflag == MEM_WRITE)
1420  d->bsc_rtcor = idata & 0x00ff;
1421  else
1422  odata = d->bsc_rtcor & 0x00ff;
1423  break;
1424 
1425  case SH4_RFCR:
1426  /* Refresh Count Register (10 bits): */
1427  if (writeflag == MEM_WRITE)
1428  d->bsc_rfcr = idata & 0x03ff;
1429  else
1430  odata = d->bsc_rfcr & 0x03ff;
1431  break;
1432 
1433 
1434  /*******************************************/
1435  /* GPIO: General-purpose I/O controller */
1436 
1437  case SH4_PCTRA:
1438  if (writeflag == MEM_WRITE) {
1439  d->pctra = idata;
1440 
1441  // Hack: Makes the Dreamcast BIOS pass "cable select"
1442  // detection, it seems, without hanging in an endless
1443  // loop.
1444  d->pdtra |= 0x03;
1445  } else {
1446  odata = d->pctra;
1447  }
1448  break;
1449 
1450  case SH4_PDTRA:
1451  if (writeflag == MEM_WRITE) {
1452  // debug("[ sh4: pdtra: write 0x%08x (while pctra = 0x%08x) ]\n", (int)idata, (int)d->pctra);
1453  d->pdtra = idata;
1454 
1455  // Hack: Makes the Dreamcast BIOS pass "cable select"
1456  // detection, it seems, without hanging in an endless
1457  // loop.
1458  if ((idata & 1) == 0 || (idata & 2) == 0)
1459  d->pdtra &= ~3;
1460  } else {
1461  // debug("[ sh4: pdtra: read ]\n");
1462  odata = d->pdtra;
1463 
1464  // bits 8..9 on Dreamcast mean:
1465  // 00 = VGA, 10 = RGB, 11 = composite.
1466  odata |= (0 << 8);
1467  }
1468  break;
1469 
1470  case SH4_PCTRB:
1471  if (writeflag == MEM_WRITE)
1472  d->pctrb = idata;
1473  else
1474  odata = d->pctrb;
1475  break;
1476 
1477  case SH4_PDTRB:
1478  if (writeflag == MEM_WRITE) {
1479  debug("[ sh4: pdtrb: write: TODO ]\n");
1480  d->pdtrb = idata;
1481  } else {
1482  debug("[ sh4: pdtrb: read: TODO ]\n");
1483  odata = d->pdtrb;
1484  }
1485  break;
1486 
1487  case SH4_GPIOIC:
1488  if (writeflag == MEM_WRITE)
1489  d->bsc_gpioic = idata;
1490  else
1491  odata = d->bsc_gpioic;
1492  break;
1493 
1494 
1495  /****************************/
1496  /* SCI: Serial Interface */
1497 
1498  case SHREG_SCSPTR:
1499  odata = sh4_sci_access(d, cpu,
1500  writeflag == MEM_WRITE? 1 : 0, idata);
1501 
1502  /*
1503  * TODO
1504  *
1505  * Find out the REAL way to make OpenBSD/landisk 4.1 run
1506  * in a stable manner! This is a SUPER-UGLY HACK which
1507  * just side-steps the real bug.
1508  *
1509  * NOTE: Snapshots of OpenBSD/landisk _after_ 4.1 seem
1510  * to work WITHOUT this hack, but NOT with it!
1511  */
1513 
1514  break;
1515 
1516 
1517  /*********************************/
1518  /* INTC: Interrupt Controller */
1519 
1520  case SH4_ICR:
1521  if (writeflag == MEM_WRITE) {
1522  if (idata & 0x80) {
1523  fatal("SH4 INTC: IRLM not yet "
1524  "supported. TODO\n");
1525  exit(1);
1526  }
1527  }
1528  break;
1529 
1530  case SH4_IPRA:
1531  if (writeflag == MEM_READ)
1532  odata = cpu->cd.sh.intc_ipra;
1533  else {
1534  cpu->cd.sh.intc_ipra = idata;
1536  }
1537  break;
1538 
1539  case SH4_IPRB:
1540  if (writeflag == MEM_READ)
1541  odata = cpu->cd.sh.intc_iprb;
1542  else {
1543  cpu->cd.sh.intc_iprb = idata;
1545  }
1546  break;
1547 
1548  case SH4_IPRC:
1549  if (writeflag == MEM_READ)
1550  odata = cpu->cd.sh.intc_iprc;
1551  else {
1552  cpu->cd.sh.intc_iprc = idata;
1554  }
1555  break;
1556 
1557  case SH4_IPRD:
1558  if (writeflag == MEM_READ)
1559  odata = cpu->cd.sh.intc_iprd;
1560  else {
1561  cpu->cd.sh.intc_iprd = idata;
1563  }
1564  break;
1565 
1566  case SH4_INTPRI00:
1567  if (writeflag == MEM_READ)
1568  odata = cpu->cd.sh.intc_intpri00;
1569  else {
1570  cpu->cd.sh.intc_intpri00 = idata;
1572  }
1573  break;
1574 
1575  case SH4_INTPRI00 + 4:
1576  if (writeflag == MEM_READ)
1577  odata = cpu->cd.sh.intc_intpri04;
1578  else {
1579  cpu->cd.sh.intc_intpri04 = idata;
1581  }
1582  break;
1583 
1584  case SH4_INTPRI00 + 8:
1585  if (writeflag == MEM_READ)
1586  odata = cpu->cd.sh.intc_intpri08;
1587  else {
1588  cpu->cd.sh.intc_intpri08 = idata;
1590  }
1591  break;
1592 
1593  case SH4_INTPRI00 + 0xc:
1594  if (writeflag == MEM_READ)
1595  odata = cpu->cd.sh.intc_intpri0c;
1596  else {
1597  cpu->cd.sh.intc_intpri0c = idata;
1599  }
1600  break;
1601 
1602  case SH4_INTMSK00:
1603  /* Note: Writes can only set bits, not clear them. */
1604  if (writeflag == MEM_READ)
1605  odata = cpu->cd.sh.intc_intmsk00;
1606  else
1607  cpu->cd.sh.intc_intmsk00 |= idata;
1608  break;
1609 
1610  case SH4_INTMSK00 + 4:
1611  /* Note: Writes can only set bits, not clear them. */
1612  if (writeflag == MEM_READ)
1613  odata = cpu->cd.sh.intc_intmsk04;
1614  else
1615  cpu->cd.sh.intc_intmsk04 |= idata;
1616  break;
1617 
1618  case SH4_INTMSKCLR00:
1619  /* Note: Writes can only clear bits, not set them. */
1620  if (writeflag == MEM_WRITE)
1621  cpu->cd.sh.intc_intmsk00 &= ~idata;
1622  break;
1623 
1624  case SH4_INTMSKCLR00 + 4:
1625  /* Note: Writes can only clear bits, not set them. */
1626  if (writeflag == MEM_WRITE)
1627  cpu->cd.sh.intc_intmsk04 &= ~idata;
1628  break;
1629 
1630 
1631  /*************************************************/
1632  /* SCIF: Serial Controller Interface with FIFO */
1633 
1634  case SH4_SCIF_BASE + SCIF_SMR:
1635  if (writeflag == MEM_WRITE) {
1636  d->scif_smr = idata;
1637  } else {
1638  odata = d->scif_smr;
1639  }
1640  break;
1641 
1642  case SH4_SCIF_BASE + SCIF_BRR:
1643  if (writeflag == MEM_WRITE) {
1644  d->scif_brr = idata;
1645  } else {
1646  odata = d->scif_brr;
1647  }
1648  break;
1649 
1650  case SH4_SCIF_BASE + SCIF_SCR:
1651  if (writeflag == MEM_WRITE) {
1652  d->scif_scr = idata;
1653  scif_reassert_interrupts(d);
1654  } else {
1655  odata = d->scif_scr;
1656  }
1657  break;
1658 
1659  case SH4_SCIF_BASE + SCIF_FTDR:
1660  if (writeflag == MEM_WRITE) {
1661  /* Add to TX fifo: */
1662  if (d->scif_tx_fifo_cursize >=
1663  sizeof(d->scif_tx_fifo)) {
1664  fatal("[ SCIF TX fifo overrun! ]\n");
1665  d->scif_tx_fifo_cursize = 0;
1666  }
1667 
1668  d->scif_tx_fifo[d->scif_tx_fifo_cursize++] = idata;
1670  }
1671  break;
1672 
1673  case SH4_SCIF_BASE + SCIF_SSR:
1674  if (writeflag == MEM_READ) {
1675  odata = d->scif_ssr;
1676  } else {
1677  d->scif_ssr = idata;
1678  scif_reassert_interrupts(d);
1679  }
1680  break;
1681 
1682  case SH4_SCIF_BASE + SCIF_FRDR:
1683  {
1685  if (x == 13)
1686  x = 10;
1687  odata = x < 0? 0 : x;
1689  d->scif_ssr |= SCSSR2_DR;
1690  else
1691  d->scif_ssr &= ~SCSSR2_DR;
1692  scif_reassert_interrupts(d);
1693  }
1694  break;
1695 
1696  case SH4_SCIF_BASE + SCIF_FCR:
1697  if (writeflag == MEM_WRITE) {
1698  d->scif_fcr = idata;
1699  } else {
1700  odata = d->scif_fcr;
1701  }
1702  break;
1703 
1704  case SH4_SCIF_BASE + SCIF_FDR:
1705  /* Nr of bytes in the TX and RX fifos, respectively: */
1706  odata = (console_charavail(d->scif_console_handle)? 1 : 0)
1707  + (d->scif_tx_fifo_cursize << 8);
1708  break;
1709 
1710  case SH4_SCIF_BASE + SCIF_SPTR:
1711  /* TODO: Implement all bits. */
1712  odata = 0;
1713  break;
1714 
1715  case SH4_SCIF_BASE + SCIF_LSR:
1716  /* TODO: Implement all bits. */
1717  odata = 0;
1718  break;
1719 
1720 
1721  /*************************************************/
1722 
1723  case SH4_CPG_FRQCR: // 0xffc00000 16-bit
1724  if (writeflag == MEM_WRITE)
1725  d->cpg_frqcr = idata;
1726  else
1727  odata = d->cpg_frqcr;
1728  break;
1729 
1730  case SH4_CPG_STBCR: // 0xffc00004 8-bit
1731  if (writeflag == MEM_WRITE)
1732  d->cpg_stbcr = idata;
1733  else
1734  odata = d->cpg_stbcr;
1735  break;
1736 
1737  case SH4_CPG_WTCNT: // 0xffc00008 8/16-bit
1738  if (writeflag == MEM_WRITE)
1739  d->cpg_wtcnt = idata;
1740  else
1741  odata = d->cpg_wtcnt;
1742  break;
1743 
1744  case SH4_CPG_WTCSR: // 0xffc0000c 8/16-bit
1745  if (writeflag == MEM_WRITE)
1746  d->cpg_wtcsr = idata;
1747  else
1748  odata = d->cpg_wtcsr;
1749  break;
1750 
1751  case SH4_CPG_STBCR2: // 0xffc00010 8-bit
1752  if (writeflag == MEM_WRITE)
1753  d->cpg_stbcr2 = idata;
1754  else
1755  odata = d->cpg_stbcr2;
1756  break;
1757 
1758 
1759  /*************************************************/
1760 
1761  case SH4_RSECCNT:
1762  case SH4_RMINCNT:
1763  case SH4_RHRCNT:
1764  case SH4_RWKCNT:
1765  case SH4_RDAYCNT:
1766  case SH4_RMONCNT:
1767  case SH4_RYRCNT:
1768  case SH4_RSECAR:
1769  case SH4_RMINAR:
1770  case SH4_RHRAR:
1771  case SH4_RWKAR:
1772  case SH4_RDAYAR:
1773  case SH4_RMONAR:
1774  if (writeflag == MEM_WRITE) {
1775  d->rtc_reg[(relative_addr - 0xffc80000) / 4] = idata;
1776  } else {
1777  /* TODO: Update rtc_reg based on host's date/time. */
1778  odata = d->rtc_reg[(relative_addr - 0xffc80000) / 4];
1779  }
1780  break;
1781 
1782  case SH4_RCR1:
1783  if (writeflag == MEM_READ)
1784  odata = d->rtc_rcr1;
1785  else {
1786  d->rtc_rcr1 = idata;
1787  if (idata & 0x18) {
1788  fatal("SH4: TODO: RTC interrupt enable\n");
1789  exit(1);
1790  }
1791  }
1792  break;
1793 
1794  case SH4_RCR2:
1795  if (writeflag == MEM_READ)
1796  odata = d->rtc_rcr2;
1797  else {
1798  d->rtc_rcr2 = idata;
1799  // bit 1 (i.e. idata == 0x02) means reset.
1800  if (idata != 0x02) {
1801  debug("[ SH4: TODO: RTC RCR2 value 0x%02x ignored. ]\n", (int)idata);
1802  }
1803  }
1804  break;
1805 
1806 
1807  /*************************************************/
1808 
1809  default:if (writeflag == MEM_READ) {
1810  fatal("[ sh4: read from addr 0x%x ]\n",
1811  (int)relative_addr);
1812  } else {
1813  fatal("[ sh4: write to addr 0x%x: 0x%x ]\n",
1814  (int)relative_addr, (int)idata);
1815  }
1816 
1817 #ifdef SH4_DEBUG
1818  exit(1);
1819 #endif
1820  }
1821 
1822  if (writeflag == MEM_READ)
1823  memory_writemax64(cpu, data, len, odata);
1824 
1825  return 1;
1826 }
1827 
1828 
1830 {
1831  char tmp[200], n[200];
1832  int i;
1833  struct machine *machine = devinit->machine;
1834  struct sh4_data *d;
1835 
1836  CHECK_ALLOCATION(d = (struct sh4_data *) malloc(sizeof(struct sh4_data)));
1837  memset(d, 0, sizeof(struct sh4_data));
1838 
1839 
1840  /*
1841  * Main SH4 device, and misc memory stuff:
1842  */
1843 
1845  SH4_REG_BASE, 0x01000000, dev_sh4_access, d, DM_DEFAULT, NULL);
1846 
1847  /* On-chip RAM/cache: */
1848  dev_ram_init(machine, 0x1e000000, 0x8000, DEV_RAM_RAM, 0x0);
1849 
1850  /* 0xe0000000: Store queues: */
1851  memory_device_register(machine->memory, "sh4_sq",
1852  0xe0000000, 0x04000000, dev_sh4_sq_access, d, DM_DEFAULT, NULL);
1853 
1854 
1855  /*
1856  * SCIF (Serial console):
1857  */
1858 
1860  "SH4 SCIF", 1);
1861 
1862  snprintf(tmp, sizeof(tmp), "%s.irq[0x%x]",
1864  INTERRUPT_CONNECT(tmp, d->scif_rx_irq);
1865  snprintf(tmp, sizeof(tmp), "%s.irq[0x%x]",
1867  INTERRUPT_CONNECT(tmp, d->scif_tx_irq);
1868 
1869 
1870  /*
1871  * Caches (fake):
1872  *
1873  * 0xf0000000 SH4_CCIA I-Cache address array
1874  * 0xf1000000 SH4_CCID I-Cache data array
1875  * 0xf4000000 SH4_CCDA D-Cache address array
1876  * 0xf5000000 SH4_CCDD D-Cache data array
1877  *
1878  * TODO: Implement more correct cache behaviour?
1879  */
1880 
1881  dev_ram_init(machine, SH4_CCIA, SH4_ICACHE_SIZE * 2, DEV_RAM_RAM, 0x0);
1883  dev_ram_init(machine, SH4_CCDA, SH4_DCACHE_SIZE * 2, DEV_RAM_RAM, 0x0);
1885 
1886  /* 0xf2000000 SH4_ITLB_AA */
1887  memory_device_register(machine->memory, "sh4_itlb_aa", SH4_ITLB_AA,
1888  0x01000000, dev_sh4_itlb_aa_access, d, DM_DEFAULT, NULL);
1889 
1890  /* 0xf3000000 SH4_ITLB_DA1 */
1891  memory_device_register(machine->memory, "sh4_itlb_da1", SH4_ITLB_DA1,
1892  0x01000000, dev_sh4_itlb_da1_access, d, DM_DEFAULT, NULL);
1893 
1894  /* 0xf6000000 SH4_UTLB_AA */
1895  memory_device_register(machine->memory, "sh4_utlb_aa", SH4_UTLB_AA,
1896  0x01000000, dev_sh4_utlb_aa_access, d, DM_DEFAULT, NULL);
1897 
1898  /* 0xf7000000 SH4_UTLB_DA1 */
1899  memory_device_register(machine->memory, "sh4_utlb_da1", SH4_UTLB_DA1,
1900  0x01000000, dev_sh4_utlb_da1_access, d, DM_DEFAULT, NULL);
1901 
1902 
1903  /*
1904  * PCIC (PCI controller) at 0xfe200000:
1905  */
1906 
1907  memory_device_register(machine->memory, "sh4_pcic", SH4_PCIC,
1908  N_PCIC_REGS * sizeof(uint32_t), dev_sh4_pcic_access, d,
1909  DM_DEFAULT, NULL);
1910 
1911  /* Initial PCI control register contents: */
1912  d->bsc_bcr2 = BCR2_PORTEN;
1915 
1916  /* Register 16 PCIC interrupts: */
1917  for (i=0; i<N_PCIC_IRQS; i++) {
1918  struct interrupt templ;
1919  snprintf(n, sizeof(n), "%s.pcic.%i",
1920  devinit->interrupt_path, i);
1921  memset(&templ, 0, sizeof(templ));
1922  templ.line = i;
1923  templ.name = n;
1924  templ.extra = d;
1925  templ.interrupt_assert = sh4_pcic_interrupt_assert;
1926  templ.interrupt_deassert = sh4_pcic_interrupt_deassert;
1928 
1929  snprintf(tmp, sizeof(tmp), "%s.irq[0x%x]",
1930  devinit->interrupt_path, SH4_INTEVT_IRQ0 + 0x20 * i);
1932  }
1933 
1934  /* Register the PCI bus: */
1935  snprintf(tmp, sizeof(tmp), "%s.pcic", devinit->interrupt_path);
1936  d->pci_data = bus_pci_init(
1937  devinit->machine,
1938  tmp, /* pciirq */
1939  0, /* pci device io offset */
1940  0, /* pci device mem offset */
1941  SH4_PCIC_IO, /* PCI portbase */
1942  SH4_PCIC_MEM, /* PCI membase */
1943  tmp, /* PCI irqbase */
1944  0x00000000, /* ISA portbase */
1945  0x00000000, /* ISA membase */
1946  "TODOisaIrqBase"); /* ISA irqbase */
1947 
1948  /* Return PCI bus pointer, to allow per-machine devices
1949  to be added later: */
1950  devinit->return_ptr = d->pci_data;
1951 
1952 
1953  /*
1954  * Timer:
1955  */
1956 
1957  d->sh4_timer = timer_add(SH4_PSEUDO_TIMER_HZ, sh4_timer_tick, d);
1958  machine_add_tickfunction(devinit->machine, dev_sh4_tick, d,
1959  SH4_TICK_SHIFT);
1960 
1961  /* Initial Timer values, according to the SH7750 manual: */
1962  d->tcor[0] = 0xffffffff; d->tcnt[0] = 0xffffffff;
1963  d->tcor[1] = 0xffffffff; d->tcnt[1] = 0xffffffff;
1964  d->tcor[2] = 0xffffffff; d->tcnt[2] = 0xffffffff;
1965 
1966  snprintf(tmp, sizeof(tmp), "machine[0].cpu[0].irq[0x%x]",
1968  if (!interrupt_handler_lookup(tmp, &d->timer_irq[0])) {
1969  fatal("Could not find interrupt '%s'.\n", tmp);
1970  exit(1);
1971  }
1972  snprintf(tmp, sizeof(tmp), "machine[0].cpu[0].irq[0x%x]",
1974  if (!interrupt_handler_lookup(tmp, &d->timer_irq[1])) {
1975  fatal("Could not find interrupt '%s'.\n", tmp);
1976  exit(1);
1977  }
1978  snprintf(tmp, sizeof(tmp), "machine[0].cpu[0].irq[0x%x]",
1980  if (!interrupt_handler_lookup(tmp, &d->timer_irq[2])) {
1981  fatal("Could not find interrupt '%s'.\n", tmp);
1982  exit(1);
1983  }
1984 
1985 
1986  // The RTC RCR2 register is "basically" initialized to 0x09, with
1987  // some bit undefined. :-) According to the manual.
1988  d->rtc_rcr2 = 0x09;
1989 
1990 
1991  /*
1992  * Bus State Controller initial values, according to the
1993  * SH7760 manual:
1994  */
1995 
1996  d->bsc_bcr2 = 0x3ffc;
1997  d->bsc_wcr1 = 0x77777777;
1998  d->bsc_wcr2 = 0xfffeefff;
1999  d->bsc_wcr3 = 0x77777777;
2000 
2001  return 1;
2002 }
2003 
int scif_console_handle
Definition: dev_sh4.cc:107
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Definition: sh4_cache.h:55
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Definition: sh4_dmacreg.h:129
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Definition: dev_sh4.cc:92
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Definition: sh4_scifreg.h:72
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Definition: sh4_pcicreg.h:97
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Definition: dev_sh4.cc:89
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Definition: sh4_pcicreg.h:49
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Definition: dev_sh4.cc:88
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Definition: dev_sh4.cc:116
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Definition: sh4_scifreg.h:71
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Definition: dev_sh4.cc:160
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DEVICE_ACCESS(sh4_itlb_aa)
Definition: dev_sh4.cc:543
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Definition: sh4_pcicreg.h:67
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Definition: dev_sh4.cc:69
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Definition: devices.h:364
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Definition: sh4_dmacreg.h:135
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Definition: device.h:43
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Definition: cpu.h:362
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Definition: sh4_scifreg.h:70
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Definition: sh4_mmu.h:99
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Definition: sh4_dmacreg.h:37
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Definition: sh4_scireg.h:8
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Definition: sh4_dmacreg.h:63
#define SH4_CHCR6
Definition: sh4_dmacreg.h:80
#define SH4_MMUCR_TI
Definition: sh4_mmu.h:70
#define SH4_CHCR1
Definition: sh4_dmacreg.h:45
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Definition: sh4_rtcreg.h:57
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Definition: cpu_sh.h:164
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Definition: sh4_tmureg.h:59
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Definition: sh4_pcicreg.h:101
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Definition: cpu_sh.h:122
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Definition: sh4_bscreg.h:54
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Definition: sh4_mmu.h:48
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Definition: interrupt.cc:81
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Definition: sh4_tmureg.h:79
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Definition: sh4_cache.h:90
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Definition: cpu_sh.cc:249
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Definition: sh4_intcreg.h:84
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Definition: sh4_bscreg.h:58
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Definition: memory.h:116
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Definition: sh4_pcicreg.h:50
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Definition: sh4_tmureg.h:85
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Definition: interrupt.h:39
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Definition: dev_sh4.cc:77
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Definition: sh4_rtcreg.h:66
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Definition: sh4_scifreg.h:74
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Definition: sh4_pcicreg.h:104
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Definition: machine.h:126
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Definition: sh4_scifreg.h:134
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Definition: pcireg.h:213
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Definition: dev_sh4.cc:128
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Definition: dev_sh4.cc:143
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Definition: dev_sh4.cc:124
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Definition: sh4_mmu.h:133
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Definition: sh4_intcreg.h:86
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Definition: sh4_mmu.h:124
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Definition: dev_sh4.cc:129
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Definition: sh4_mmu.h:49
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Definition: dev_sh4.cc:321
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Definition: sh4_cpu.h:187
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Definition: pcireg.h:73
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Definition: sh4_mmu.h:55
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Definition: dev_sh4.cc:147
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Definition: console.cc:405
#define reg(x)
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Definition: console.cc:385
#define SH4_PCILSR0
Definition: sh4_pcicreg.h:68
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Definition: cpu_sh.cc:632
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Definition: dev_sh4.cc:119
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Definition: sh4_dmacreg.h:48
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Definition: device.h:56
#define SH4_DAR6
Definition: sh4_dmacreg.h:78
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Definition: cpu_sh.h:138
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Definition: sh4_rtcreg.h:58
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Definition: sh4_dmacreg.h:67
Definition: timer.cc:45
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Definition: sh4_bscreg.h:61
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Definition: sh4_pcicreg.h:95
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Definition: cpu_sh.h:150
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Definition: cpu_sh.h:154
#define SH4_CCDD
Definition: sh4_cache.h:100
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Definition: sh4_rtcreg.h:65
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Definition: cpu_sh.h:131
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Definition: sh4_bscreg.h:57
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Definition: sh4_mmu.h:45
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Definition: sh4_dmacreg.h:57
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Definition: sh4_cache.h:49
#define SH4_UTLB_AA_VPN_MASK
Definition: sh4_mmu.h:128
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Definition: sh4_mmu.h:47
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Definition: cpu_sh.h:123
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Definition: interrupt.cc:166
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Definition: dev_sh4.cc:102
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Definition: misc.h:164
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Definition: dev_sh4.cc:169
#define SH4_DMATCR2
Definition: sh4_dmacreg.h:49
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Definition: sh4_scifreg.h:67
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Definition: cpu_sh.h:54
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Definition: dev_sh4.cc:110
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Definition: misc.h:239
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Definition: sh4_tmureg.h:54
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Definition: cpu_sh.h:168
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Definition: cpu_sh.h:129
#define SH4_PTEL_V
Definition: sh4_mmu.h:60
#define EXPEVT_RESET_TLB_MULTI_HIT
Definition: sh4_exception.h:59
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Definition: sh4_mmu.h:57
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Definition: sh4_bscreg.h:67
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Definition: sh4_pcicreg.h:44
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Definition: sh4_intcreg.h:87
#define SH_N_ITLB_ENTRIES
Definition: cpu_sh.h:88
#define SH4_CPG_WTCNT
Definition: dev_sh4.cc:90
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Definition: dev_sh4.cc:148
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Definition: dev_sh4.cc:158
uint32_t itlb_lo[SH_N_ITLB_ENTRIES]
Definition: cpu_sh.h:133
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Definition: console.cc:336
#define PHYSICAL
Definition: memory.h:126
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Definition: sh4_dmacreg.h:58
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Definition: sh4_dmacreg.h:134
#define SH4_PTEA
Definition: sh4_mmu.h:63
struct pci_data * pci_data
Definition: dev_sh4.cc:142
void bus_pci_setaddr(struct cpu *cpu, struct pci_data *pci_data, int bus, int device, int function, int reg)
Definition: bus_pci.cc:197
int(* memory_rw)(struct cpu *cpu, struct memory *mem, uint64_t vaddr, unsigned char *data, size_t len, int writeflag, int cache_flags)
Definition: cpu.h:365
#define SCIF_TX_FIFO_SIZE
Definition: dev_sh4.cc:79
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Definition: sh4_dmacreg.h:73
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Definition: sh4_exception.h:88
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Definition: sh4_intcreg.h:82
#define SH4_DMATCR3
Definition: sh4_dmacreg.h:54
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Definition: cpu_sh.h:140
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Definition: cpu_sh.h:134
u_short data
Definition: siireg.h:79
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Definition: sh4_bscreg.h:56
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Definition: sh4_rtcreg.h:69
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Definition: sh4_mmu.h:59
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Definition: dev_sh4.cc:103
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Definition: dev_sh4.cc:111
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Definition: cpu_sh.h:127
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Definition: sh4_pcicreg.h:51
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Definition: sh4_rtcreg.h:56
uint32_t dmac_chcr[N_SH4_DMA_CHANNELS]
Definition: cpu_sh.h:167
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Definition: sh4_dmacreg.h:53
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Definition: sh4_rtcreg.h:63
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Definition: sh4_scifreg.h:76
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Definition: dev_sh4.cc:122
#define SCIF_FCR
Definition: sh4_scifreg.h:73
struct timer * timer_add(double freq, void(*timer_tick)(struct timer *timer, void *extra), void *extra)
Definition: timer.cc:75
void dev_ram_init(struct machine *machine, uint64_t baseaddr, uint64_t length, int mode, uint64_t otheraddress, const char *name)
Definition: dev_ram.cc:134
#define CHCR_SM
Definition: sh4_dmacreg.h:121
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Definition: sh4_exception.h:90
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Definition: sh4_intcreg.h:81
#define SH4_PCILAR0
Definition: sh4_pcicreg.h:70
#define INTERRUPT_ASSERT(istruct)
Definition: interrupt.h:74
uint32_t pteh
Definition: cpu_sh.h:126
#define SH4_DAR4
Definition: sh4_dmacreg.h:68
uint8_t sq[32 *2]
Definition: dev_sh4.cc:97
#define SCSSR2_TDFE
Definition: sh4_scifreg.h:135
#define CHCR_TS_32BYTE
Definition: sh4_dmacreg.h:132
#define TCR_ICPE1
Definition: sh4_tmureg.h:77
#define CHCR_TD
Definition: sh4_dmacreg.h:136
uint8_t scif_tx_fifo[SCIF_TX_FIFO_SIZE+1]
Definition: dev_sh4.cc:108
#define CHCR_TS
Definition: sh4_dmacreg.h:127
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Definition: dev_sh4.cc:159
#define SH4_PDTRA
Definition: sh4_bscreg.h:66
#define MEM_WRITE
Definition: memory.h:117
#define SH4_PCIPDR
Definition: sh4_pcicreg.h:110
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Definition: sh4_dmacreg.h:131
#define SH4_QACR1
Definition: sh4_cache.h:68
int scif_delayed_tx
Definition: dev_sh4.cc:106
uint32_t intc_intpri08
Definition: cpu_sh.h:149
#define SH4_UTLB_E_SHIFT
Definition: sh4_mmu.h:123
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Definition: dev_sh4.cc:139
#define SH4_PCIWCR1
Definition: sh4_pcicreg.h:103
#define SH4_TCR1
Definition: sh4_tmureg.h:57
uint32_t tcnt[N_SH4_TIMERS]
Definition: dev_sh4.cc:162
int timer_interrupts_pending[N_SH4_TIMERS]
Definition: dev_sh4.cc:165
#define N_PCIC_IRQS
Definition: dev_sh4.cc:73
struct sh_cpu_type_def cpu_type
Definition: cpu_sh.h:97
#define SH4_PCICONF6
Definition: sh4_pcicreg.h:55
#define SH4_ITLB_E_SHIFT
Definition: sh4_mmu.h:94
#define CHCR_SM_DECREMENTED
Definition: sh4_dmacreg.h:124
Definition: device.h:40
uint32_t tstr
Definition: dev_sh4.cc:161
#define SH4_PCIC
Definition: sh4_pcicreg.h:39
#define SH4_PCIBCR3
Definition: sh4_pcicreg.h:107
uint16_t intc_ipra
Definition: cpu_sh.h:143
#define SH4_PTEL_C
Definition: sh4_mmu.h:52
#define PCI_CLASS_CODE(mainclass, subclass, interface)
Definition: pcireg.h:146
#define SH4_DMATCR4
Definition: sh4_dmacreg.h:69
#define SH4_SAR5
Definition: sh4_dmacreg.h:72
uint16_t bsc_bcr2
Definition: dev_sh4.cc:117
#define SH4_DCACHE_SIZE
Definition: sh4_cache.h:50
#define SH4_QACR0
Definition: sh4_cache.h:67
uint16_t bsc_rfcr
Definition: dev_sh4.cc:125
#define SH4_TTB
Definition: sh4_mmu.h:66
#define SH4_MCR
Definition: sh4_bscreg.h:59
uint16_t sdmr3
Definition: dev_sh4.cc:155
uint32_t bsc_wcr3
Definition: dev_sh4.cc:120
uint16_t intc_iprb
Definition: cpu_sh.h:144
uint32_t pcic_reg[N_PCIC_REGS]
Definition: dev_sh4.cc:144
#define SH4_PTEL_SH
Definition: sh4_mmu.h:50
#define SCSPTR_SPB1IO
Definition: sh4_scireg.h:83
#define SH4_UTLB_AA_D
Definition: sh4_mmu.h:129
#define SH4_PCIWCR3
Definition: sh4_pcicreg.h:105
#define debug
Definition: dev_adb.cc:57
DEVICE_TICK(sh4)
Definition: dev_sh4.cc:273
#define SH4_RHRAR
Definition: sh4_rtcreg.h:64
#define SH4_DAR0
Definition: sh4_dmacreg.h:38
#define SH4_CHCR0
Definition: sh4_dmacreg.h:40
uint32_t intc_intpri04
Definition: cpu_sh.h:148
uint32_t line
Definition: interrupt.h:51
#define INTERRUPT_CONNECT(name, istruct)
Definition: interrupt.h:77
Definition: cpu.h:326
uint32_t dmac_dar[N_SH4_DMA_CHANNELS]
Definition: cpu_sh.h:165
uint8_t sci_curbyte
Definition: dev_sh4.cc:150
#define SH4_ICR
Definition: sh4_intcreg.h:79
struct machine * machine
Definition: device.h:41
#define SH4_TCOR0
Definition: sh4_tmureg.h:52
#define SCIF_DELAYED_TX_VALUE
Definition: dev_sh4.cc:80
uint32_t ptea
Definition: cpu_sh.h:128
#define CHCR_CHSET
Definition: sh4_dmacreg.h:133
#define SH4_PTEL_PR_MASK
Definition: sh4_mmu.h:54
char * name
Definition: interrupt.h:66
#define SH4_TCOR2
Definition: sh4_tmureg.h:58
#define SCIF_SCR
Definition: sh4_scifreg.h:69
uint32_t pctra
Definition: dev_sh4.cc:135
uint8_t sci_scsptr
Definition: dev_sh4.cc:149
uint32_t dmac_tcr[N_SH4_DMA_CHANNELS]
Definition: cpu_sh.h:166
#define SH4_ITLB_DA1
Definition: sh4_mmu.h:103
int scif_tx_irq_asserted
Definition: dev_sh4.cc:112
void memory_writemax64(struct cpu *cpu, unsigned char *buf, int len, uint64_t data)
Definition: memory.cc:89
DEVINIT(sh4)
Definition: dev_sh4.cc:1829
#define SH4_REG_BASE
Definition: dev_sh4.cc:67
int console_start_slave(struct machine *machine, const char *consolename, int use_for_input)
Definition: console.cc:668
uint16_t scif_fcr
Definition: dev_sh4.cc:104
#define TCR_CKEG0
Definition: sh4_tmureg.h:81
#define SH4_EXPEVT
Definition: sh4_exception.h:50
#define CHCR_DM_DECREMENTED
Definition: sh4_dmacreg.h:120
#define BCR2_PORTEN
Definition: sh4_bscreg.h:77
#define SH4_DAR7
Definition: sh4_dmacreg.h:83
void memory_device_register(struct memory *mem, const char *, uint64_t baseaddr, uint64_t len, int(*f)(struct cpu *, struct memory *, uint64_t, unsigned char *, size_t, int, void *), void *extra, int flags, unsigned char *dyntrans_data)
Definition: memory.cc:339
#define SH4_PCTRA
Definition: sh4_bscreg.h:65
#define SH4_INTEVT_IRQ0
#define SH4_CHCR4
Definition: sh4_dmacreg.h:70
#define SH4_UTLB_A
Definition: sh4_mmu.h:125
#define SH4_BCR2
Definition: sh4_bscreg.h:55
#define SH4_RMONCNT
Definition: sh4_rtcreg.h:60
#define SH4_IPRD
Definition: sh4_intcreg.h:83
uint32_t itlb_hi[SH_N_ITLB_ENTRIES]
Definition: cpu_sh.h:132
#define SCSPTR_SPB1DT
Definition: sh4_scireg.h:84
uint16_t intc_iprc
Definition: cpu_sh.h:145
#define SH4_PCIC_IO
Definition: sh4_pcicreg.h:41
uint8_t byte_order
Definition: cpu.h:347
uint32_t tea
Definition: cpu_sh.h:130
#define TOCR_TCOE
Definition: sh4_tmureg.h:71
#define SH4_CHCR2
Definition: sh4_dmacreg.h:50
#define PCI_PRODUCT_HITACHI_SH7751
Definition: dev_sh4.cc:76
#define SH4_DAR1
Definition: sh4_dmacreg.h:43
double timer_hz[N_SH4_TIMERS]
Definition: dev_sh4.cc:166
#define SCIF_LSR
Definition: sh4_scifreg.h:77
#define TCR_TPSC_P64
Definition: sh4_tmureg.h:87
#define N_PCIC_REGS
Definition: dev_sh4.cc:72
#define SHREG_SCSPTR
Definition: sh4_scireg.h:64
#define SH4_DMATCR6
Definition: sh4_dmacreg.h:79
struct pci_data * bus_pci_init(struct machine *machine, const char *irq_path, uint64_t pci_actual_io_offset, uint64_t pci_actual_mem_offset, uint64_t pci_portbase, uint64_t pci_membase, const char *pci_irqbase, uint64_t isa_portbase, uint64_t isa_membase, const char *isa_irqbase)
Definition: bus_pci.cc:356
uint16_t cpg_wtcsr
Definition: dev_sh4.cc:131
#define CHCR_SM_FIXED
Definition: sh4_dmacreg.h:122
#define SH4_PCIBCR2
Definition: sh4_pcicreg.h:102
#define SCSCR2_TIE
Definition: sh4_scifreg.h:125
#define SH4_RTCOR
Definition: sh4_bscreg.h:63
addr & if(addr >=0x24 &&page !=NULL)
#define SH4_UTLB_AA
Definition: sh4_mmu.h:121
#define SH4_SCIF_BASE
Definition: sh4_scifreg.h:39
#define SH4_UTLB_AA_V
Definition: sh4_mmu.h:130
#define SH4_TRA
Definition: sh4_exception.h:49
#define SH4_RSECAR
Definition: sh4_rtcreg.h:62
#define SH4_TCR2
Definition: sh4_tmureg.h:60
uint32_t bsc_mcr
Definition: dev_sh4.cc:121
#define SH4_GPIOIC
Definition: sh4_bscreg.h:69
#define SH4_SAR1
Definition: sh4_dmacreg.h:42
#define CHCR_TS_8BYTE
Definition: sh4_dmacreg.h:128
#define SH4_SAR2
Definition: sh4_dmacreg.h:47
#define SH4_PTEL_SZ_64K
Definition: sh4_mmu.h:58
void machine_add_tickfunction(struct machine *machine, void(*func)(struct cpu *, void *), void *extra, int clockshift)
Definition: machine.cc:280
int pclock
Definition: cpu_sh.h:161
uint32_t ccr
Definition: cpu_sh.h:121
#define SH4_PCIMCR
Definition: sh4_pcicreg.h:106
uint32_t tcr[N_SH4_TIMERS]
Definition: dev_sh4.cc:164
#define CHCR_DM_INCREMENTED
Definition: sh4_dmacreg.h:119
#define SH4_TCOR1
Definition: sh4_tmureg.h:55
#define CHCR_TS_2BYTE
Definition: sh4_dmacreg.h:130
#define SCSPTR_SPB0IO
Definition: sh4_scireg.h:85
#define SH4_TICK_SHIFT
Definition: dev_sh4.cc:68
void * extra
Definition: interrupt.h:59
uint16_t scif_lsr
Definition: dev_sh4.cc:105
#define RTCSR_CMIE
Definition: sh4_bscreg.h:80
#define CHCR_SM_INCREMENTED
Definition: sh4_dmacreg.h:123
#define SCSSR2_DR
Definition: sh4_scifreg.h:140
void bus_pci_data_access(struct cpu *cpu, struct pci_data *pci_data, uint64_t *data, int len, int writeflag)
Definition: bus_pci.cc:96
#define SH4_SAR6
Definition: sh4_dmacreg.h:77
uint16_t scif_smr
Definition: dev_sh4.cc:100
#define DMAOR_PR0
Definition: sh4_dmacreg.h:60
uint16_t bsc_rtcsr
Definition: dev_sh4.cc:123
uint16_t sdmr2
Definition: dev_sh4.cc:154
#define SCSCR2_RIE
Definition: sh4_scifreg.h:126
#define SH4_CPG_WTCSR
Definition: dev_sh4.cc:91
#define SH4_DMATCR5
Definition: sh4_dmacreg.h:74
uint32_t pdtrb
Definition: dev_sh4.cc:138
#define SH4_TEA
Definition: sh4_mmu.h:67
#define TCR_ICPF
Definition: sh4_tmureg.h:75
#define SH4_PSEUDO_TIMER_HZ
Definition: dev_sh4.cc:175
#define SH4_PCIMBR
Definition: sh4_pcicreg.h:96
#define PCIC_REG(addr)
Definition: dev_sh4.cc:74
#define TSTR_STR0
Definition: sh4_tmureg.h:74
uint8_t scif_brr
Definition: dev_sh4.cc:101
#define SH4_TOCR
Definition: sh4_tmureg.h:50
uint32_t utlb_lo[SH_N_UTLB_ENTRIES]
Definition: cpu_sh.h:135
#define CHCR_DM_FIXED
Definition: sh4_dmacreg.h:118
#define PCI_CLASS_BRIDGE
Definition: pcireg.h:158
uint32_t pdtra
Definition: dev_sh4.cc:136
#define TCR_CKEG1
Definition: sh4_tmureg.h:80
#define SH4_CHCR5
Definition: sh4_dmacreg.h:75
int scif_rx_irq_asserted
Definition: dev_sh4.cc:113
#define SH4_ITLB_AA
Definition: sh4_mmu.h:92
#define SH4_IPRA
Definition: sh4_intcreg.h:80
uint32_t intc_intmsk00
Definition: cpu_sh.h:153
uint32_t pctrb
Definition: dev_sh4.cc:137
#define RTCSR_OVIE
Definition: sh4_bscreg.h:83
#define PCI_VENDOR_HITACHI
Definition: dev_sh4.cc:75
struct sh_cpu sh
Definition: cpu.h:445
size_t scif_tx_fifo_cursize
Definition: dev_sh4.cc:109
#define SH_INTEVT_TMU1_TUNI1
Definition: sh4_exception.h:89
uint32_t tcor[N_SH4_TIMERS]
Definition: dev_sh4.cc:163
#define SH4_PDTRB
Definition: sh4_bscreg.h:68
void(* invalidate_translation_caches)(struct cpu *, uint64_t paddr, int flags)
Definition: cpu.h:374
uint8_t rtc_rcr1
Definition: dev_sh4.cc:170
#define SH4_ITLB_E_MASK
Definition: sh4_mmu.h:95
char * interrupt_path
Definition: device.h:50
#define INTERRUPT_DEASSERT(istruct)
Definition: interrupt.h:75
#define TCR_TPSC_P256
Definition: sh4_tmureg.h:88
#define SH4_PTEL_SZ_1K
Definition: sh4_mmu.h:56
#define SH4_SAR3
Definition: sh4_dmacreg.h:52

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