61 static int arm_dpi_uses_d[16] = { 1,1,1,1,1,1,1,1,0,0,0,0,1,1,1,1 };
62 static int arm_dpi_uses_n[16] = { 1,1,1,1,1,1,1,1,1,1,1,1,1,0,1,0 };
88 while (i >= 0 && cpu_type_defs[i].
name != NULL) {
89 if (strcasecmp(cpu_type_defs[i].
name, cpu_type_name) == 0) {
132 isize = 1 << (isize - 10);
134 dsize = 1 << (dsize - 10);
135 debug(
" (I+D = %i+%i KB)", isize, dsize);
178 struct interrupt templ;
180 snprintf(name,
sizeof(name),
"%s.irq", cpu->
path);
182 memset(&templ, 0,
sizeof(templ));
206 unsigned char nothing[16384];
214 memset(nothing, 0,
sizeof(nothing));
217 for (i=0; i<256; i++)
218 for (j=0x0; j<=0xf; j++) {
219 unsigned char descr[4];
221 (((j << 28) + (i << 20)) >> 18);
222 uint32_t d = (1048576*i) | 0xc02;
225 descr[0] = d; descr[1] = d >> 8;
226 descr[2] = d >> 16; descr[3] = d >> 24;
228 descr[3] = d; descr[2] = d >> 8;
229 descr[1] = d >> 16; descr[0] = d >> 24;
243 unsigned int i, j, vhigh = vaddr >> 28, phigh = paddr >> 28;
245 for (i=0; i<256; i++)
246 for (j=vhigh; j<=vhigh; j++) {
247 unsigned char descr[4];
249 (((j << 28) + (i << 20)) >> 18);
250 uint32_t d = ((phigh << 28) + 1048576*i) | 0xc02;
253 descr[0] = d; descr[1] = d >> 8;
254 descr[2] = d >> 16; descr[3] = d >> 24;
256 descr[3] = d; descr[2] = d >> 8;
257 descr[1] = d >> 16; descr[0] = d >> 24;
271 unsigned int i, j, vhigh = vaddr >> 24, phigh = paddr >> 24;
274 for (j=vhigh; j<=vhigh; j++) {
275 unsigned char descr[4];
277 (((j << 24) + (i << 20)) >> 18);
278 uint32_t d = ((phigh << 24) + 1048576*i) | 0xc02;
281 descr[0] = d; descr[1] = d >> 8;
282 descr[2] = d >> 16; descr[3] = d >> 24;
284 descr[3] = d; descr[2] = d >> 8;
285 descr[1] = d >> 16; descr[0] = d >> 24;
300 debug(
" (I+D = %i+%i KB)\n",
316 while (tdefs[i].
name != NULL) {
318 for (j=13 -
strlen(tdefs[i].name); j>0; j--)
321 if ((i % 5) == 0 || tdefs[i].name == NULL)
348 debug(
"cpu%i: cpsr = ", x);
349 debug(
"%s%s%s%s%s%s%s%s",
359 debug(
" pc = 0x%07x", (
int)(cpu->
pc & 0x03ffffff));
361 debug(
" pc = 0x%08x", (
int)cpu->
pc);
363 debug(
" <%s>\n", symbol != NULL? symbol :
" no symbol ");
369 debug(
" %s = 0x%08x", arm_regname[i],
381 debug(
"USR32)\n");
break;
383 debug(
"SYS32)\n");
break;
385 debug(
"FIQ32)\n");
break;
387 debug(
"IRQ32)\n");
break;
389 debug(
"SVC32)\n");
break;
391 debug(
"ABT32)\n");
break;
393 debug(
"UND32)\n");
break;
394 default:
debug(
"unimplemented)\n");
398 debug(
"cpu%i: usr r8-14:", x);
405 debug(
"cpu%i: fiq r8-14:", x);
412 debug(
"cpu%i: irq r13-14:", x);
419 debug(
"cpu%i: svc r13-14:", x);
426 debug(
"cpu%i: abt r13-14:", x);
433 debug(
"cpu%i: und r13-14:", x);
442 debug(
"cpu%i: MMU: %s\n", x,
445 debug(
"cpu%i: alignment checks: %s\n", x,
448 debug(
"cpu%i: [data] cache: %s\n", x,
451 debug(
"cpu%i: instruction cache: %s\n", x,
454 debug(
"cpu%i: write buffer: %s\n", x,
457 debug(
"cpu%i: prog32: %s\n", x,
460 debug(
"cpu%i: data32: %s\n", x,
463 debug(
"cpu%i: endianness: %s\n", x,
466 debug(
"cpu%i: high vectors: %s\n", x,
472 debug(
"cpu%i: auxctrl = 0x%08x\n", x,
474 debug(
"cpu%i: minidata cache attr = 0x%x\n", x,
477 debug(
"cpu%i: page table memory attr: %i\n", x,
479 debug(
"cpu%i: write buffer coalescing: %s\n", x,
481 "disabled" :
"enabled");
484 debug(
"cpu%i: ttb = 0x%08x dacr = 0x%08x\n", x,
486 debug(
"cpu%i: fsr = 0x%08x far = 0x%08x\n", x,
502 &cpu->
cd.
arm.
r[8],
sizeof(uint32_t) * 7);
506 &cpu->
cd.
arm.
r[8],
sizeof(uint32_t) * 7);
510 &cpu->
cd.
arm.
r[8],
sizeof(uint32_t) * 5);
516 &cpu->
cd.
arm.
r[8],
sizeof(uint32_t) * 5);
522 &cpu->
cd.
arm.
r[8],
sizeof(uint32_t) * 5);
528 &cpu->
cd.
arm.
r[8],
sizeof(uint32_t) * 5);
532 default:
fatal(
"arm_save_register_bank: unimplemented mode %i\n",
553 sizeof(uint32_t) * 7);
579 default:
fatal(
"arm_load_register_bank: unimplemented mode %i\n",
591 int oldmode, newmode;
595 fatal(
"arm_exception(): exception_nr = %i\n", exception_nr);
602 debug(
"[ arm_exception(): ");
603 switch (exception_nr) {
605 fatal(
"RESET: TODO");
614 debug(
"PREFETCH ABORT");
623 debug(
"DATA ABORT, far=0x%08x fsr=0x%02x",
630 switch (exception_nr) {
633 fatal(
"ARM RESET: TODO");
647 switch (arm_exception_to_mode[exception_nr]) {
658 default:
fatal(
"arm_exception(): unimplemented exception nr\n");
671 cpu->
cd.
arm.
cpsr |= arm_exception_to_mode[exception_nr];
682 fatal(
"[ WARNING! Exception caused no mode change? " 683 "mode 0x%02x (pc=0x%x) ]\n", newmode, (
int)cpu->
pc);
730 struct cpu *cpu = (
struct cpu *) interrupt->
extra;
735 struct cpu *cpu = (
struct cpu *) interrupt->
extra;
748 int running, uint64_t dumpaddr)
752 iw = ib[0] + (ib[1]<<8);
754 iw = ib[1] + (ib[0]<<8);
755 debug(
"%04x \t", (
int)iw);
757 int main_opcode = (iw >> 12) & 15;
758 int rn = (iw >> 6) & 7;
759 int rs_rb = (iw >> 3) & 7;
761 int offset5 = (iw >> 6) & 0x1f;
762 int b_bit = (iw >> 12) & 1;
763 int l_bit = (iw >> 11) & 1;
764 int addsub_op = (iw >> 9) & 1;
765 int addsub_immediate = (iw >> 10) & 1;
766 int op11 = (iw >> 11) & 3;
767 int op10 = (iw >> 10) & 3;
768 int op8 = (iw >> 8) & 3;
769 int h1 = (iw >> 7) & 1;
770 int h2 = (iw >> 6) & 1;
771 int condition_code = (iw >> 8) & 15;
772 const char* condition = arm_condition_string[condition_code];
783 debug(
"movs\tr%i,r%i, %s #%i\n",
786 op11 & 1 ?
"lsr" : (op11 & 2 ?
"asr" :
"lsl"),
790 debug(
"%s\tr%i,r%i,%s%i\n",
791 addsub_op ?
"subs" :
"adds",
794 addsub_immediate ?
"#" :
"r",
804 debug(
"%s\tr%i,r%i,#%i\n",
805 op11 & 1 ?
"subs" :
"adds",
809 debug(
"%s\tr%i,#%i\n",
810 op11 & 1 ?
"cmp" :
"movs",
820 debug(
"TODO main_opcode = %i, op10 = %i\n", main_opcode, op10);
833 if (h1 == 0 && h2 == 0) {
834 debug(
"TODO main_opcode = %i, op10 = %i, h1 AND h2 are zero?!\n", main_opcode, op10);
837 debug(
"add\tr%i,r%i,r%i\n", rd, rd, rs_rb);
839 debug(
"%s\tr%i,r%i\n",
840 op8 == 1 ?
"cmp" :
"mov", rd, rs_rb);
845 debug(
"TODO main_opcode = %i, op10 = %i, h1 set for BX?!\n", main_opcode, op10);
847 debug(
"bx\tr%i\n", rs_rb);
856 debug(
"TODO main_opcode = %i, op10 = %i\n", main_opcode, op10);
864 debug(
"%s%s\tr%i,[r%i,#%i]\n",
865 l_bit ?
"ldr" :
"str",
869 offset5 * (b_bit ?
sizeof(uint8_t) :
sizeof(uint32_t)));
874 debug(
"%sh\tr%i,[r%i,#%i]\n",
875 l_bit ?
"ldr" :
"str",
878 offset5 *
sizeof(uint16_t));
882 if (condition_code < 0xe) {
884 debug(
"b%s\t", condition);
885 tmp = (iw & 0xff) << 1;
888 tmp = (int32_t)(dumpaddr + 4 + tmp);
889 debug(
"0x%x", (
int)tmp);
893 debug(
" \t<%s>", symbol);
898 debug(
"UNIMPLEMENTED\n");
905 debug(
"UNKNOWN encoding?\n");
907 tmp = (iw & 0x7ff) << 1;
910 tmp = (int32_t)(dumpaddr + 4 + tmp);
911 debug(
"bal\t0x%x", (
int)tmp);
915 debug(
" \t<%s>", symbol);
921 debug(
"TODO: unimplemented opcode %i\n", main_opcode);
924 return sizeof(uint16_t);
941 int running, uint64_t dumpaddr)
944 int main_opcode, secondary_opcode, s_bit, r16, r12, r8;
945 int i, n, p_bit, u_bit, b_bit, w_bit, l_bit;
946 const char *
symbol, *condition;
954 if (symbol != NULL && offset == 0)
955 debug(
"<%s>\n", symbol);
960 debug(
"%08x: ", (
int)dumpaddr);
966 iw = ib[0] + (ib[1]<<8) + (ib[2]<<16) + (ib[3]<<24);
968 iw = ib[3] + (ib[2]<<8) + (ib[1]<<16) + (ib[0]<<24);
969 debug(
"%08x\t", (
int)iw);
971 condition = arm_condition_string[iw >> 28];
972 main_opcode = (iw >> 24) & 15;
973 secondary_opcode = (iw >> 21) & 15;
974 u_bit = (iw >> 23) & 1;
975 b_bit = (iw >> 22) & 1;
976 w_bit = (iw >> 21) & 1;
977 s_bit = l_bit = (iw >> 20) & 1;
978 r16 = (iw >> 16) & 15;
979 r12 = (iw >> 12) & 15;
982 switch (main_opcode) {
995 if ((iw & 0x0fc000f0) == 0x00000090) {
996 int a_bit = (iw >> 21) & 1;
997 debug(
"%s%s%s\t", a_bit?
"mla" :
"mul",
998 condition, s_bit?
"s" :
"");
999 debug(
"%s,", arm_regname[r16]);
1000 debug(
"%s,", arm_regname[iw & 15]);
1001 debug(
"%s", arm_regname[r8]);
1003 debug(
",%s", arm_regname[r12]);
1012 if ((iw & 0x0f8000f0) == 0x00800090) {
1013 int a_bit = (iw >> 21) & 1;
1014 u_bit = (iw >> 22) & 1;
1015 debug(
"%s%sl%s%s\t", u_bit?
"s" :
"u",
1016 a_bit?
"mla" :
"mul", condition, s_bit?
"s" :
"");
1017 debug(
"%s,%s,", arm_regname[r12], arm_regname[r16]);
1018 debug(
"%s,%s\n", arm_regname[iw&15], arm_regname[r8]);
1028 if ((iw & 0x0f900ff0) == 0x01000050) {
1029 debug(
"q%s%s%s\t", iw & 0x400000?
"d" :
"",
1030 iw & 0x200000?
"sub" :
"add", condition);
1031 debug(
"%s,%s,%s\n", arm_regname[r12],
1032 arm_regname[iw&15], arm_regname[r16]);
1039 if ((iw & 0x0ff000d0) == 0x01200010) {
1041 debug(
"b%sx%s\t%s\n", l_bit?
"l" :
"", condition,
1042 arm_regname[iw & 15]);
1051 if ((iw & 0x0fb0fff0) == 0x0120f000 ||
1052 (iw & 0x0fb0f000) == 0x0320f000) {
1053 debug(
"msr%s\t%s", condition, (iw&0x400000)?
"S":
"C");
1055 if (iw & (1<<19))
debug(
"f");
1056 if (iw & (1<<18))
debug(
"s");
1057 if (iw & (1<<17))
debug(
"x");
1058 if (iw & (1<<16))
debug(
"c");
1059 if (iw & 0x02000000) {
1060 int r = (iw >> 7) & 30;
1061 uint32_t b = iw & 0xff;
1063 b = (b >> 1) | ((b & 1) << 31);
1064 debug(
",#0x%x\n", b);
1066 debug(
",%s\n", arm_regname[iw & 15]);
1069 if ((iw & 0x0fbf0fff) == 0x010f0000) {
1070 debug(
"mrs%s\t", condition);
1071 debug(
"%s,%sPSR\n", arm_regname[r12],
1072 (iw&0x400000)?
"S":
"C");
1079 if ((iw & 0x0fb00ff0) == 0x01000090) {
1080 debug(
"swp%s%s\t", condition, (iw&0x400000)?
"b":
"");
1081 debug(
"%s,%s,[%s]\n", arm_regname[r12],
1082 arm_regname[iw & 15], arm_regname[r16]);
1089 if ((iw & 0x0ff000f0) == 0x01200070) {
1090 debug(
"bkpt%s\t0x%04x\n", condition,
1091 ((iw & 0x000fff00) >> 4) + (iw & 0xf));
1098 if ((iw & 0x0fff0ff0) == 0x016f0f10) {
1099 debug(
"clz%s\t", condition);
1100 debug(
"%s,%s\n", arm_regname[r12], arm_regname[iw&15]);
1111 if ((iw & 0x0ff00090) == 0x01000080) {
1112 debug(
"smla%s%s%s\t",
1113 iw & 0x20?
"t" :
"b", iw & 0x40?
"t" :
"b",
1115 debug(
"%s,%s,%s,%s\n", arm_regname[r16],
1116 arm_regname[iw&15], arm_regname[r8],
1120 if ((iw & 0x0ff00090) == 0x01400080) {
1121 debug(
"smlal%s%s%s\t",
1122 iw & 0x20?
"t" :
"b", iw & 0x40?
"t" :
"b",
1124 debug(
"%s,%s,%s,%s\n", arm_regname[r12],
1125 arm_regname[r16], arm_regname[iw&15],
1129 if ((iw & 0x0ff000b0) == 0x01200080) {
1130 debug(
"smlaw%s%s\t", iw & 0x40?
"t" :
"b",
1132 debug(
"%s,%s,%s,%s\n", arm_regname[r16],
1133 arm_regname[iw&15], arm_regname[r8],
1137 if ((iw & 0x0ff0f090) == 0x01600080) {
1138 debug(
"smul%s%s%s\t",
1139 iw & 0x20?
"t" :
"b", iw & 0x40?
"t" :
"b",
1141 debug(
"%s,%s,%s\n", arm_regname[r16],
1142 arm_regname[iw&15], arm_regname[r8]);
1145 if ((iw & 0x0ff0f0b0) == 0x012000a0) {
1146 debug(
"smulw%s%s\t", iw & 0x40?
"t" :
"b",
1148 debug(
"%s,%s,%s\n", arm_regname[r16],
1149 arm_regname[iw&15], arm_regname[r8]);
1156 if ((iw & 0x0e000090) == 0x00000090) {
1157 const char *
op =
"st";
1158 int imm = ((iw >> 4) & 0xf0) | (iw & 0xf);
1159 int regform = !(iw & 0x00400000);
1160 p_bit = main_opcode & 1;
1165 if (!l_bit && (iw & 0xd0) == 0xd0 && (r12 & 1)) {
1166 debug(
"TODO: r12 odd, not load/store\n");
1170 if (iw & 0x00100000)
1172 if (!l_bit && (iw & 0xd0) == 0xd0) {
1178 debug(
"%sr%s", op, condition);
1179 if (!l_bit && (iw & 0xd0) == 0xd0) {
1189 debug(
"\t%s,[%s", arm_regname[r12], arm_regname[r16]);
1193 debug(
",%s%s", u_bit?
"" :
"-",
1194 arm_regname[iw & 15]);
1197 debug(
",#%s%i", u_bit?
"" :
"-",
1200 debug(
"]%s\n", w_bit?
"!" :
"");
1205 debug(
"%s%s\n", u_bit?
"" :
"-",
1206 arm_regname[iw & 15]);
1208 debug(
"#%s%i\n", u_bit?
"" :
"-", imm);
1214 if (iw & 0x80 && !(main_opcode & 2) && iw & 0x10) {
1215 debug(
"UNIMPLEMENTED reg (c!=0), t odd\n");
1226 debug(
"%s%s%s\t", arm_dpiname[secondary_opcode],
1227 condition, s_bit?
"s" :
"");
1228 if (arm_dpi_uses_d[secondary_opcode])
1229 debug(
"%s,", arm_regname[r12]);
1230 if (arm_dpi_uses_n[secondary_opcode])
1231 debug(
"%s,", arm_regname[r16]);
1233 if (main_opcode & 2) {
1235 int r = (iw >> 7) & 30;
1236 uint32_t b = iw & 0xff;
1238 b = (b >> 1) | ((b & 1) << 31);
1245 int t = (iw >> 4) & 7;
1246 int c = (iw >> 7) & 31;
1247 debug(
"%s", arm_regname[iw & 15]);
1250 debug(
", lsl #%i", c);
1252 case 1:
debug(
", lsl %s", arm_regname[c >> 1]);
1254 case 2:
debug(
", lsr #%i", c? c : 32);
1256 case 3:
debug(
", lsr %s", arm_regname[c >> 1]);
1258 case 4:
debug(
", asr #%i", c? c : 32);
1260 case 5:
debug(
", asr %s", arm_regname[c >> 1]);
1263 debug(
", ror #%i", c);
1267 case 7:
debug(
", ror %s", arm_regname[c >> 1]);
1272 if (running && t == 0 && c == 0 && secondary_opcode
1278 debug(
" \t<%s>", symbol);
1288 if ((iw & 0xfc70f000) == 0xf450f000) {
1290 debug(
"pld\t[%s]\n", arm_regname[r16]);
1298 p_bit = main_opcode & 1;
1299 if (main_opcode >= 6 && iw & 0x10) {
1300 debug(
"TODO: single data transf. but 0x10\n");
1303 debug(
"%s%s%s", l_bit?
"ldr" :
"str",
1304 condition, b_bit?
"b" :
"");
1305 if (!p_bit && w_bit)
1307 debug(
"\t%s,[%s", arm_regname[r12], arm_regname[r16]);
1308 if ((iw & 0x0e000000) == 0x04000000) {
1310 uint32_t imm = iw & 0xfff;
1314 debug(
",#%s%i", u_bit?
"" :
"-", imm);
1317 }
else if ((iw & 0x0e000010) == 0x06000000) {
1321 if ((iw & 0xfff) != 0)
1322 debug(
",%s%s", u_bit?
"" :
"-",
1323 arm_regname[iw & 15]);
1324 if ((iw & 0xff0) != 0x000) {
1325 int c = (iw >> 7) & 31;
1326 int t = (iw >> 4) & 7;
1329 debug(
", lsl #%i", c);
1331 case 2:
debug(
", lsr #%i", c? c : 32);
1333 case 4:
debug(
", asr #%i", c? c : 32);
1336 debug(
", ror #%i", c);
1348 debug(
"%s", (p_bit && w_bit)?
"!" :
"");
1349 if ((iw & 0x0f000000) == 0x05000000 &&
1350 (r16 ==
ARM_PC || running)) {
1351 unsigned char tmpw[4];
1352 uint32_t imm = iw & 0xfff;
1353 uint32_t
addr = (u_bit? imm : -imm);
1355 addr += dumpaddr + 8;
1357 addr += cpu->
cd.
arm.
r[r16];
1361 debug(
" \t<%s", symbol);
1363 debug(
" \t<0x%08x", addr);
1364 if ((l_bit && cpu->
memory_rw(cpu, cpu->
mem, addr, tmpw,
1366 || (!l_bit && running)) {
1370 addr = tmpw[0] +(tmpw[1] << 8) +
1371 (tmpw[2]<<16)+(tmpw[3]<<24);
1373 addr = tmpw[3] + (tmpw[2]<<8) +
1374 (tmpw[1]<<16)+(tmpw[0]<<24);
1376 tmpw[0] = addr = cpu->
cd.
arm.
r[r12];
1382 debug(
"%i", tmpw[0]);
1387 debug(
"%s", symbol);
1388 else if ((int32_t)addr > -256 &&
1389 (int32_t)addr < 256)
1392 debug(
"0x%x", addr);
1402 p_bit = main_opcode & 1;
1404 debug(
"%s%s", l_bit?
"ldm" :
"stm", condition);
1405 switch (u_bit * 2 + p_bit) {
1406 case 0:
debug(
"da");
break;
1407 case 1:
debug(
"db");
break;
1408 case 2:
debug(
"ia");
break;
1409 case 3:
debug(
"ib");
break;
1411 debug(
"\t%s", arm_regname[r16]);
1416 for (i=0; i<16; i++)
1417 if ((iw >> i) & 1) {
1418 debug(
"%s%s", (n > 0)?
",":
"", arm_regname[i]);
1428 debug(
"b%s%s\t", main_opcode == 0xa?
"" :
"l", condition);
1429 tmp = (iw & 0x00ffffff) << 2;
1430 if (tmp & 0x02000000)
1432 tmp = (int32_t)(dumpaddr + tmp + 8);
1433 debug(
"0x%x", (
int)tmp);
1437 debug(
" \t<%s>", symbol);
1446 if ((iw & 0x0fe00fff) == 0x0c400000) {
1447 debug(
"%s%s\t", iw & 0x100000?
"mra" :
"mar",
1450 debug(
"%s,%s,acc0\n",
1451 arm_regname[r12], arm_regname[r16]);
1453 debug(
"acc0,%s,%s\n",
1454 arm_regname[r12], arm_regname[r16]);
1457 if ((iw & 0x0fe00000) == 0x0c400000) {
1458 debug(
"%s%s\t", iw & 0x100000?
"mrrc" :
"mcrr",
1460 debug(
"%i,%i,%s,%s,cr%i\n", r8, (iw >> 4) & 15,
1461 arm_regname[r12], arm_regname[r16], iw & 15);
1466 debug(
"TODO: coprocessor LDC/STC\n");
1473 if ((iw & 0x0ff00ff0) == 0x0e200010) {
1475 switch ((iw >> 16) & 0xf) {
1476 case 0:
debug(
"mia");
break;
1477 case 8:
debug(
"miaph");
break;
1478 case 12:
debug(
"miaBB");
break;
1479 case 13:
debug(
"miaTB");
break;
1480 case 14:
debug(
"miaBT");
break;
1481 case 15:
debug(
"miaTT");
break;
1482 default:
debug(
"UNKNOWN mia vector instruction?");
1484 debug(
"%s\t", condition);
1485 debug(
"acc%i,%s,%s\n", ((iw >> 5) & 7),
1486 arm_regname[iw & 15], arm_regname[r12]);
1491 (iw & 0x00100000)?
"mrc" :
"mcr", condition);
1492 debug(
"%i,%i,r%i,cr%i,cr%i,%i",
1493 (
int)((iw >> 8) & 15), (
int)((iw >>21) & 7),
1494 (
int)((iw >>12) & 15), (
int)((iw >>16) & 15),
1495 (
int)((iw >> 0) & 15), (
int)((iw >> 5) & 7));
1497 debug(
"cdp%s\t", condition);
1498 debug(
"%i,%i,cr%i,cr%i,cr%i",
1499 (
int)((iw >> 8) & 15),
1500 (
int)((iw >>20) & 15),
1501 (
int)((iw >>12) & 15),
1502 (
int)((iw >>16) & 15),
1503 (
int)((iw >> 0) & 15));
1505 debug(
",0x%x", (
int)((iw >> 5) & 7));
1510 debug(
"swi%s\t", condition);
1511 debug(
"0x%x\n", (
int)(iw & 0x00ffffff));
1513 default:
debug(
"UNIMPLEMENTED\n");
1516 return sizeof(uint32_t);
1533 int opcode1 = (iword >> 21) & 7;
1534 int l_bit = (iword >> 20) & 1;
1535 int crn = (iword >> 16) & 15;
1536 int rd = (iword >> 12) & 15;
1537 int cp_num = (iword >> 8) & 15;
1538 int opcode2 = (iword >> 5) & 7;
1539 int crm = iword & 15;
1542 cpu->
cd.
arm.
coproc[cp_num](cpu, opcode1, opcode2, l_bit,
1545 fatal(
"[ arm_mcr_mrc: pc=0x%08x, iword=0x%08x: " 1546 "cp_num=%i ]\n", (
int)cpu->
pc, iword, cp_num);
1563 fatal(
"[ arm_cdp: pc=0x%08x, iword=0x%08x ]\n", (
int)cpu->
pc, iword);
#define ARM_CONTROL_ALIGN
void fatal(const char *fmt,...)
void arm_save_register_bank(struct cpu *cpu)
void(* interrupt_assert)(struct interrupt *)
int(* translate_v2p)(struct cpu *, uint64_t vaddr, uint64_t *return_paddr, int flags)
int arm_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr, unsigned char *data, size_t len, int writeflag, int cache_flags)
#define ARM_EXCEPTION_TO_MODE
int arm_translate_v2p_mmu(struct cpu *cpu, uint64_t vaddr64, uint64_t *return_paddr, int flags)
int store_32bit_word(struct cpu *cpu, uint64_t addr, uint64_t data32)
void arm_cpu_list_available_types(void)
struct arm_cpu_type_def cpu_type
#define ARM_CACHETYPE_IASSOC_SHIFT
void arm_invalidate_code_translation(struct cpu *cpu, uint64_t, int)
#define ARM_AUXCTRL_MD_SHIFT
void arm_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, unsigned char *host_page, int writeflag, uint64_t paddr_page)
#define ARM_EXCEPTION_DATA_ABT
void interrupt_handler_register(struct interrupt *templ)
void(* interrupt_deassert)(struct interrupt *)
void arm_coproc_15(struct cpu *cpu, int opcode1, int opcode2, int l_bit, int crn, int crm, int rd)
void arm_load_register_bank(struct cpu *cpu)
void arm_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs)
void arm_translation_table_set_l1_b(struct cpu *cpu, uint32_t vaddr, uint32_t paddr)
int(* run_instr)(struct cpu *cpu)
char * get_symbol_name(struct symbol_context *, uint64_t addr, uint64_t *offset)
uint32_t default_r8_r14[7]
#define ARM_CACHETYPE_DLINE_SHIFT
#define EMUL_LITTLE_ENDIAN
#define quick_pc_to_pointers(cpu)
#define ARM_CACHETYPE_HARVARD_SHIFT
void arm_exception(struct cpu *cpu, int exception_nr)
int arm_run_instr(struct cpu *cpu)
#define ARM_EXCEPTION_IRQ
#define ARM_CONTROL_ICACHE
#define ARM_CACHETYPE_CLASS_SHIFT
#define ARM_CACHETYPE_DSIZE_SHIFT
int(* memory_rw)(struct cpu *cpu, struct memory *mem, uint64_t vaddr, unsigned char *data, size_t len, int writeflag, int cache_flags)
#define ARM_EXCEPTION_SWI
int arm_translate_v2p(struct cpu *cpu, uint64_t vaddr64, uint64_t *return_paddr, int flags)
#define ARM_CONTROL_DATA32
#define ARM_CACHETYPE_ILINE_SHIFT
#define ARM_EXCEPTION_RESET
#define ARM_CONTROL_WBUFFER
#define ARM_CACHETYPE_ISIZE_SHIFT
#define ARM_CACHETYPE_DASSOC_SHIFT
void arm_pc_to_pointers(struct cpu *cpu)
int arm_cpu_disassemble_instr_thumb(struct cpu *cpu, unsigned char *ib, int running, uint64_t dumpaddr)
#define CPU_SETTINGS_ADD_REGISTER32(name, var)
#define ARM_EXCEPTION_PREF_ABT
void arm_cpu_tlbdump(struct machine *m, int x, int rawflag)
void COMBINE() strlen(struct cpu *cpu, struct arm_instr_call *ic, int low_addr)
int arm_cpu_disassemble_instr(struct cpu *cpu, unsigned char *ib, int running, uint64_t dumpaddr)
struct symbol_context symbol_context
#define ARM_CONDITION_STRINGS
int arm_cpu_new(struct cpu *cpu, struct memory *mem, struct machine *machine, int cpu_id, char *cpu_type_name)
void(* coproc[16])(struct cpu *, int opcode1, int opcode2, int l_bit, int crn, int crm, int rd)
void(* update_translation_table)(struct cpu *, uint64_t vaddr_page, unsigned char *host_page, int writeflag, uint64_t paddr_page)
void arm_irq_interrupt_assert(struct interrupt *interrupt)
void arm_irq_interrupt_deassert(struct interrupt *interrupt)
#define ARM_CPU_TYPE_DEFS
#define ARM_CONTROL_CACHE
#define ARM_EXCEPTION_FIQ
void arm_coproc_xscale_14(struct cpu *cpu, int opcode1, int opcode2, int l_bit, int crn, int crm, int rd)
void(* invalidate_code_translation)(struct cpu *, uint64_t paddr, int flags)
void arm_invalidate_translation_caches(struct cpu *cpu, uint64_t, int)
void arm_mcr_mrc(struct cpu *cpu, uint32_t iword)
#define CPU_SETTINGS_ADD_REGISTER64(name, var)
void arm_translation_table_set_l1(struct cpu *cpu, uint32_t vaddr, uint32_t paddr)
void arm_cpu_dumpinfo(struct cpu *cpu)
#define ARM_CONTROL_PROG32
void arm_setup_initial_translation_table(struct cpu *cpu, uint32_t ttb_addr)
void arm_cdp(struct cpu *cpu, uint32_t iword)
#define ARM_EXCEPTION_UND
void(* invalidate_translation_caches)(struct cpu *, uint64_t paddr, int flags)