m8820x.h Source File
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m8820x.h
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/* $OpenBSD: m8820x.h,v 1.7 2006/05/06 16:59:26 miod Exp $ */
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/*
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* Copyright (c) 2004, Miodrag Vallat.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Mach Operating System
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* Copyright (c) 1993-1992 Carnegie Mellon University
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* All Rights Reserved.
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*
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* Permission to use, copy, modify and distribute this software and its
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* documentation is hereby granted, provided that both the copyright
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* notice and this permission notice appear in all copies of the
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* software, derivative works or modified versions, and any portions
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* thereof, and that both notices appear in supporting documentation.
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*
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* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
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* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
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* ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
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*
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* Carnegie Mellon requests users of this software to return to
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*
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* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
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* School of Computer Science
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* Carnegie Mellon University
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* Pittsburgh PA 15213-3890
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*
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* any improvements or extensions that they make and grant Carnegie Mellon
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* the rights to redistribute these changes.
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*/
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#ifndef __M88K_M8820X_H__
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#define __M88K_M8820X_H__
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/*
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* 8820x CMMU definitions
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*/
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/* CMMU registers */
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#define CMMU_IDR (0x000 / 4)
/* CMMU id register */
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#define CMMU_SCR (0x004 / 4)
/* system command register */
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#define CMMU_SSR (0x008 / 4)
/* system status register */
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#define CMMU_SAR (0x00c / 4)
/* system address register */
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#define CMMU_SCTR (0x104 / 4)
/* system control register */
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#define CMMU_PFSR (0x108 / 4)
/* P bus fault status register */
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#define CMMU_PFAR (0x10c / 4)
/* P bus fault address register */
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#define CMMU_SAPR (0x200 / 4)
/* supervisor area pointer register */
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#define CMMU_UAPR (0x204 / 4)
/* user area pointer register */
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#define CMMU_BWP0 (0x400 / 4)
/* block ATC writer port 0 */
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#define CMMU_BWP1 (0x404 / 4)
/* block ATC writer port 1 */
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#define CMMU_BWP2 (0x408 / 4)
/* block ATC writer port 2 */
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#define CMMU_BWP3 (0x40c / 4)
/* block ATC writer port 3 */
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#define CMMU_BWP4 (0x410 / 4)
/* block ATC writer port 4 */
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#define CMMU_BWP5 (0x414 / 4)
/* block ATC writer port 5 */
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#define CMMU_BWP6 (0x418 / 4)
/* block ATC writer port 6 */
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#define CMMU_BWP7 (0x41c / 4)
/* block ATC writer port 7 */
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#define CMMU_BWP(n) (CMMU_BWP0 + (n))
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#define CMMU_CDP0 (0x800 / 4)
/* cache data port 0 */
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#define CMMU_CDP1 (0x804 / 4)
/* cache data port 1 */
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#define CMMU_CDP2 (0x808 / 4)
/* cache data port 2 */
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#define CMMU_CDP3 (0x80c / 4)
/* cache data port 3 */
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#define CMMU_CTP0 (0x840 / 4)
/* cache tag port 0 */
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#define CMMU_CTP1 (0x844 / 4)
/* cache tag port 1 */
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#define CMMU_CTP2 (0x848 / 4)
/* cache tag port 2 */
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#define CMMU_CTP3 (0x84c / 4)
/* cache tag port 3 */
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#define CMMU_CSSP0 (0x880 / 4)
/* cache set status register */
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#define CMMU_CSSP(n) ((0x880 + (n * 0x10)) / 4)
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/* the following only exist on 88204 */
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#define CMMU_CSSP1 (0x890 / 4)
/* cache set status register */
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#define CMMU_CSSP2 (0x8a0 / 4)
/* cache set status register */
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#define CMMU_CSSP3 (0x8b0 / 4)
/* cache set status register */
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/* system commands */
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#define CMMU_FLUSH_CACHE_INV_LINE 0x14
/* data cache invalidate */
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#define CMMU_FLUSH_CACHE_INV_PAGE 0x15
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#define CMMU_FLUSH_CACHE_INV_SEGMENT 0x16
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#define CMMU_FLUSH_CACHE_INV_ALL 0x17
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#define CMMU_FLUSH_CACHE_CB_LINE 0x18
/* data cache copyback */
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#define CMMU_FLUSH_CACHE_CB_PAGE 0x19
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#define CMMU_FLUSH_CACHE_CB_SEGMENT 0x1a
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#define CMMU_FLUSH_CACHE_CB_ALL 0x1b
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#define CMMU_FLUSH_CACHE_CBI_LINE 0x1c
/* copyback and invalidate */
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#define CMMU_FLUSH_CACHE_CBI_PAGE 0x1d
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#define CMMU_FLUSH_CACHE_CBI_SEGMENT 0x1e
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#define CMMU_FLUSH_CACHE_CBI_ALL 0x1f
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#define CMMU_PROBE_USER 0x20
/* probe user address */
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#define CMMU_PROBE_SUPER 0x24
/* probe supervisor address */
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#define CMMU_FLUSH_USER_LINE 0x30
/* flush PATC */
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#define CMMU_FLUSH_USER_PAGE 0x31
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#define CMMU_FLUSH_USER_SEGMENT 0x32
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#define CMMU_FLUSH_USER_ALL 0x33
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#define CMMU_FLUSH_SUPER_LINE 0x34
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#define CMMU_FLUSH_SUPER_PAGE 0x35
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#define CMMU_FLUSH_SUPER_SEGMENT 0x36
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#define CMMU_FLUSH_SUPER_ALL 0x37
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/* system control values */
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#define CMMU_SCTR_PE 0x00008000
/* parity enable */
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#define CMMU_SCTR_SE 0x00004000
/* snoop enable */
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#define CMMU_SCTR_PR 0x00002000
/* priority arbitration */
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/* P bus fault status */
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#define CMMU_PFSR_FAULT(pfsr) (((pfsr) >> 16) & 0x07)
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#define CMMU_PFSR_SUCCESS 0
/* no fault */
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#define CMMU_PFSR_BERROR 3
/* bus error */
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#define CMMU_PFSR_SFAULT 4
/* segment fault */
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#define CMMU_PFSR_PFAULT 5
/* page fault */
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#define CMMU_PFSR_SUPER 6
/* supervisor violation */
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#define CMMU_PFSR_WRITE 7
/* writer violation */
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/* CSSP values */
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#define CMMU_CSSP_L5 0x20000000
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#define CMMU_CSSP_L4 0x10000000
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#define CMMU_CSSP_L3 0x08000000
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#define CMMU_CSSP_L2 0x04000000
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#define CMMU_CSSP_L1 0x02000000
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#define CMMU_CSSP_L0 0x01000000
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#define CMMU_CSSP_D3 0x00800000
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#define CMMU_CSSP_D2 0x00400000
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#define CMMU_CSSP_D1 0x00200000
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#define CMMU_CSSP_D0 0x00100000
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#define CMMU_CSSP_VV(n,v) (((v) & 0x03) << (12 + 2 * (n)))
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#define CMMU_VV_EXCLUSIVE 0x00
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#define CMMU_VV_MODIFIED 0x01
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#define CMMU_VV_SHARED 0x02
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#define CMMU_VV_INVALID 0x03
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/* IDR values */
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#define CMMU_ID(idr) ((idr) >> 24)
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#define CMMU_TYPE(idr) (((idr) >> 21) & 0x07)
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#define CMMU_VERSION(idr) (((idr) >> 16) & 0x1f)
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#define M88200_ID 5
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#define M88204_ID 6
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/* SSR values */
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#define CMMU_SSR_CE 0x00008000
/* copyback error */
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#define CMMU_SSR_BE 0x00004000
/* bus error */
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#define CMMU_SSR_SO 0x00000100
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#define CMMU_SSR_M 0x00000010
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#define CMMU_SSR_U 0x00000008
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#define CMMU_SSR_PROT 0x00000004
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#define CMMU_SSR_BH 0x00000002
/* probe BATC hit */
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#define CMMU_SSR_V 0x00000001
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/*
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* Cache line information
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*/
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#define MC88200_CACHE_SHIFT 4
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#define MC88200_CACHE_LINE (1 << MC88200_CACHE_SHIFT)
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/*
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* Hardwired BATC information
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*/
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#define BATC8 0xfff7ffb5
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#define BATC9 0xfffffff5
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#define BATC8_VA 0xfff00000
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#define BATC9_VA 0xfff80000
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#define NBSG (1 << (PDT_BITS + PG_BITS))
/* segment size */
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#define INST_CMMU 0x00
/* even number */
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#define DATA_CMMU 0x01
/* odd number */
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#define CMMU_MODE(num) ((num) & 1)
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#define MAX_CMMUS 8
/* maximum cmmus on the board */
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#if 0
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#ifndef _LOCORE
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/*
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* CMMU kernel information
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*/
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struct
m8820x_cmmu
{
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volatile
u_int32_t *cmmu_regs;
/* CMMU "base" area */
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#ifdef M88200_HAS_SPLIT_ADDRESS
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vaddr_t cmmu_addr;
/* address range */
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vaddr_t cmmu_addr_mask;
/* address mask */
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#endif
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};
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extern
struct
m8820x_cmmu
m8820x_cmmu[MAX_CMMUS];
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extern
u_int cmmu_shift;
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extern
u_int max_cmmus;
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void
m8820x_setup_board_config(
void
);
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cpuid_t m8820x_cpu_number(
void
);
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#endif
/* _LOCORE */
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#endif
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#endif
/* __M88K_M8820X_H__ */
m8820x_cmmu
Definition:
M88K_CPUComponent.h:323
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