34 #include <sys/types.h> 38 #include "../../config.h" 57 static const char *hi6_names[] =
HI6_NAMES;
62 static const char *mmi_names[] =
MMI_NAMES;
73 #define DYNTRANS_DUALMODE_32 74 #define DYNTRANS_DELAYSLOT 90 int cpu_id,
char *cpu_type_name)
92 int i, found, j, tags_size, n_cache_lines, size_per_cache_line;
94 int64_t secondary_cache_size;
100 while (i >= 0 && cpu_type_defs[i].
name != NULL) {
101 if (strcasecmp(cpu_type_defs[i].
name, cpu_type_name) == 0) {
213 size_per_cache_line = 32;
223 tags_size = n_cache_lines * size_per_cache_line;
232 for (j=0; j<n_cache_lines; j++) {
251 secondary_cache_size = 0;
257 debug(
" (I+D = %i+%i KB",
261 if (secondary_cache_size != 0) {
263 if (secondary_cache_size >= 1048576)
265 (secondary_cache_size / 1048576));
268 (secondary_cache_size / 1024));
275 for (i=2; i<8; i++) {
278 snprintf(name,
sizeof(name),
"%s.%i", cpu->
path, i);
279 memset(&templ, 0,
sizeof(templ));
351 debug(
"\n%i-bit %s-endian (MIPS",
356 case 1:
debug(
" ISA I");
break;
357 case 2:
debug(
" ISA II");
break;
358 case 3:
debug(
" ISA III");
break;
359 case 4:
debug(
" ISA IV");
break;
360 case 5:
debug(
" ISA V");
break;
381 debug(
", direct-mapped");
392 debug(
", direct-mapped");
397 int kb = (1 << ct->
scache) / 1024;
398 debug(
"L2 cache: %i %s",
399 kb >= 1024? kb / 1024 : kb, kb >= 1024?
"MB":
"KB");
405 debug(
", direct-mapped");
424 while (cpu_type_defs[i].
name != NULL) {
426 for (j=10 -
strlen(cpu_type_defs[i].name); j>0; j--)
429 if ((i % 6) == 0 || cpu_type_defs[i].name == NULL)
442 uint32_t iword = *((uint32_t *)&ib[0]);
449 switch (iword >> 26) {
451 switch (iword & 0x3f) {
458 switch ((iword >> 16) & 0x1f) {
502 for (i=0; i<m->
ncpus; i++) {
506 if (x >= 0 && i != x)
510 printf(
"cpu%i: (", i);
513 printf(
"index=0x%08x random=0x%08x",
517 printf(
"index=0x%016" PRIx64
518 " random=0x%016" PRIx64,
519 (uint64_t) cop0->
reg[COP0_INDEX],
520 (uint64_t) cop0->
reg[COP0_RANDOM]);
523 printf(
" wired=0x%" PRIx64,
529 nr_of_tlb_entries; j++) {
532 printf(
" %02x: hi=0x%08" PRIx32
" lo=0x%08" 534 (uint32_t) cop0->
tlbs[j].
hi,
537 printf(
" %02x: hi=0x%08" PRIx32
" mask=0x" 538 "%08" PRIx32
" lo0=0x%08" PRIx32
539 " lo1=0x%08" PRIx32
"\n", j,
540 (uint32_t) cop0->
tlbs[j].
hi,
545 printf(
" %02x: hi=0x%016" PRIx64
" mask=" 546 "0x%016" PRIx64
" lo0=0x%016" PRIx64
547 " lo1=0x%016" PRIx64
"\n", j,
548 (uint64_t) cop0->
tlbs[j].
hi,
559 for (i=0; i<m->
ncpus; i++) {
563 if (x >= 0 && i != x)
570 printf(
"cpu%i: (", i);
573 case 2: printf(
"index=0x%x random=0x%x",
579 default:printf(
"index=0x%x random=0x%x",
582 printf(
" wired=0x%" PRIx64,
589 nr_of_tlb_entries; j++) {
590 uint64_t hi = cop0->
tlbs[j].
hi;
591 uint64_t lo0 = cop0->
tlbs[j].
lo0;
592 uint64_t lo1 = cop0->
tlbs[j].
lo1;
596 mask |= (1 << (pageshift+1)) - 1;
599 printf(
" %02x: ", j);
604 printf(
"(invalid)\n");
607 printf(
"vaddr=0x%08x ",
610 printf(
"(global), ");
612 printf(
"(asid %02x),", (
int) ((hi &
615 printf(
" paddr=0x%08x ",
625 printf(
"vaddr=0x%08" PRIx32
" ",
626 (uint32_t) (hi & ~mask));
629 printf(
"vaddr=%016" PRIx64
" ",
630 (uint64_t) (hi & ~mask));
633 printf(
"(global): ");
635 printf(
"(asid %02x):",
641 printf(
" p0=(invalid) ");
646 paddr &= ~(mask >> 1);
647 printf(
" p0=0x%09" PRIx64
" ",
652 if (!(lo1 & ENTRYLO_V))
653 printf(
" p1=(invalid) ");
658 paddr &= ~(mask >> 1);
659 printf(
" p1=0x%09" PRIx64
" ",
662 printf(lo1 & ENTRYLO_D?
"D" :
" ");
665 psize = (mask + 1) >> 1;
667 if (psize >= 1024 && psize <= 256*1024)
668 printf(
" (%iKB)", (
int) (psize >> 10));
669 else if (psize >= 1024*1024 && psize <=
671 printf(
" (%iMB)", (
int) (psize >> 20));
697 int running, uint64_t dumpaddr)
699 int hi6, special6, regimm5, sub;
700 int rt, rd, rs, sa, imm, copz, cache_op, which_cache, showtag;
701 uint64_t
addr, offset;
703 unsigned char instr[4];
709 if ((dumpaddr & 3) != 0)
710 printf(
"WARNING: Unaligned address!\n");
714 if (symbol != NULL && offset==0)
715 debug(
"<%s>\n", symbol);
721 debug(
"%08" PRIx32, (uint32_t)dumpaddr);
723 debug(
"%016" PRIx64, (uint64_t)dumpaddr);
725 memcpy(instr, originstr,
sizeof(uint32_t));
732 int tmp = instr[0]; instr[0] = instr[3];
734 tmp = instr[1]; instr[1] = instr[2];
738 debug(
": %02x%02x%02x%02x",
739 instr[3], instr[2], instr[1], instr[0]);
750 hi6 = (instr[3] >> 2) & 0x3f;
754 special6 = instr[0] & 0x3f;
765 sub = ((instr[3] & 3) << 3) + ((instr[2] >> 5) & 7);
767 rd = (instr[1] >> 3) & 31;
768 sa = ((instr[1] & 7) << 2) + ((instr[0] >> 6) & 3);
778 debug(
"nop (weird, sa=%i)", sa);
784 debug(
"%s\t%s,", special_names[special6],
786 debug(
"%s,%i", regnames[rt], sa);
790 special_rot_names[special6],
792 debug(
"%s,%i", regnames[rt], sa);
794 default:
debug(
"UNIMPLEMENTED special, sub=0x%02x\n",
804 rs = ((instr[3] & 3) << 3) + ((instr[2] >> 5) & 7);
806 rd = (instr[1] >> 3) & 31;
807 sub = ((instr[1] & 7) << 2) + ((instr[0] >> 6) & 3);
811 debug(
"%s\t%s", special_names[special6],
813 debug(
",%s", regnames[rt]);
814 debug(
",%s", regnames[rs]);
817 debug(
"%s\t%s", special_rot_names[special6],
819 debug(
",%s", regnames[rt]);
820 debug(
",%s", regnames[rs]);
822 default:
debug(
"UNIMPLEMENTED special, sub=0x%02x\n",
827 rs = ((instr[3] & 3) << 3) + ((instr[2] >> 5) & 7);
832 (instr[1] & 0x04) ?
".hb" :
"",
834 if (running && symbol != NULL)
835 debug(
"\t<%s>", symbol);
838 rs = ((instr[3] & 3) << 3) + ((instr[2] >> 5) & 7);
839 rd = (instr[1] >> 3) & 31;
844 (instr[1] & 0x04) ?
".hb" :
"",
846 debug(
",%s", regnames[rs]);
847 if (running && symbol != NULL)
848 debug(
"\t<%s>", symbol);
852 rd = (instr[1] >> 3) & 31;
853 debug(
"%s\t%s", special_names[special6], regnames[rd]);
857 rs = ((instr[3] & 3) << 3) + ((instr[2] >> 5) & 7);
858 debug(
"%s\t%s", special_names[special6], regnames[rs]);
876 rs = ((instr[3] & 3) << 3) + ((instr[2] >> 5) & 7);
878 rd = (instr[1] >> 3) & 31;
883 debug(
"move\t%s", regnames[rd]);
884 debug(
",%s", regnames[rs]);
889 debug(
"move\t%s", regnames[rd]);
890 debug(
",%s", regnames[rt]);
892 debug(
"%s\t%s", special_names[special6],
894 debug(
",%s", regnames[rs]);
895 debug(
",%s", regnames[rt]);
906 rs = ((instr[3] & 3) << 3) + ((instr[2] >> 5) & 7);
908 rd = (instr[1] >> 3) & 31;
909 debug(
"%s\t", special_names[special6]);
914 debug(
"%s,", regnames[rd]);
916 debug(
"WEIRD_R5900_RD,");
918 debug(
"WEIRD_RD_NONZERO,");
921 debug(
"%s", regnames[rs]);
922 debug(
",%s", regnames[rt]);
930 rs = ((instr[3] & 3) << 3) + ((instr[2] >> 5) & 7);
932 rd = ((instr[1] << 8) + instr[0]) >> 6;
933 debug(
"%s\t", special_names[special6]);
934 debug(
"%s", regnames[rs]);
935 debug(
",%s", regnames[rt]);
940 imm = ((instr[1] & 7) << 2) + (instr[0] >> 6);
941 debug(
"sync\t0x%02x", imm);
944 imm = (((instr[3] << 24) + (instr[2] << 16) +
945 (instr[1] << 8) + instr[0]) >> 6) & 0xfffff;
947 debug(
"syscall\t0x%05x", imm);
952 imm = (((instr[3] << 24) + (instr[2] << 16) +
953 (instr[1] << 8) + instr[0]) >> 6) & 0xfffff;
955 debug(
"break\t0x%05x", imm);
961 rd = (instr[1] >> 3) & 31;
962 debug(
"mfsa\t%s", regnames[rd]);
964 debug(
"unimplemented special 0x28");
969 rs = ((instr[3] & 3) << 3) +
970 ((instr[2] >> 5) & 7);
971 debug(
"mtsa\t%s", regnames[rs]);
973 debug(
"unimplemented special 0x29");
977 debug(
"%s\t= UNIMPLEMENTED", special_names[special6]);
988 rs = ((instr[3] & 3) << 3) + ((instr[2] >> 5) & 7);
990 imm = (instr[1] << 8) + instr[0];
993 addr = (dumpaddr + 4) + (imm << 2);
999 debug(
"%s\t", hi6_names[hi6]);
1005 debug(
"%s,", regnames[rt]);
1007 debug(
"%s,", regnames[rs]);
1011 debug(
"0x%08" PRIx32, (uint32_t)addr);
1013 debug(
"0x%016" PRIx64, (uint64_t)addr);
1017 if (symbol != NULL && offset != addr)
1018 debug(
"\t<%s>", symbol);
1029 rs = ((instr[3] & 3) << 3) + ((instr[2] >> 5) & 7);
1031 imm = (instr[1] << 8) + instr[0];
1034 debug(
"%s\t%s,", hi6_names[hi6], regnames[rt]);
1035 debug(
"%s,", regnames[rs]);
1037 debug(
"0x%04x", imm & 0xffff);
1043 imm = (instr[1] << 8) + instr[0];
1044 debug(
"lui\t%s,0x%x", regnames[rt], imm);
1083 debug(
"mdmx\t(UNIMPLEMENTED)");
1088 int msbd, lsb, sub10;
1089 special6 = instr[0] & 0x3f;
1090 rs = ((instr[3] & 3) << 3) + ((instr[2] >> 5) & 7);
1092 rd = msbd = (instr[1] >> 3) & 31;
1093 lsb = ((instr[1] & 7) << 2) | (instr[0] >> 6);
1094 sub10 = (rs << 5) | lsb;
1102 debug(
"%s", special3_names[special6]);
1107 debug(
"\t%s", regnames[rt]);
1108 debug(
",%s", regnames[rs]);
1109 debug(
",%i,%i", lsb, msbd + 1);
1116 debug(
"%s", special3_names[special6]);
1124 debug(
"\t%s", regnames[rt]);
1125 debug(
",%s", regnames[rs]);
1126 debug(
",%i,%i", lsb, msbd + 1);
1139 debug(
"\t%s", regnames[rd]);
1140 debug(
",%s", regnames[rt]);
1142 default:
debug(
"%s", special3_names[special6]);
1143 debug(
"\t(UNIMPLEMENTED)");
1155 debug(
"\t%s", regnames[rd]);
1156 debug(
",%s", regnames[rt]);
1158 default:
debug(
"%s", special3_names[special6]);
1159 debug(
"\t(UNIMPLEMENTED)");
1164 debug(
"%s", special3_names[special6]);
1165 debug(
"\t%s", regnames[rt]);
1166 debug(
",hwr%i", rd);
1169 default:
debug(
"%s", special3_names[special6]);
1170 debug(
"\t(UNIMPLEMENTED)");
1175 rs = ((instr[3] & 3) << 3) + ((instr[2] >> 5) & 7);
1177 imm = (instr[1] << 8) + instr[0];
1186 debug(
"pref\t0x%x,%i(%s)",
1187 rt, imm, regnames[rs]);
1190 debug(
"\t[0x%016" PRIx64
" = %s]",
1191 (uint64_t)(cpu->
cd.
mips.
gpr[rs] + imm));
1193 debug(
" = %s", symbol);
1199 debug(
"%s\t", hi6_names[hi6]);
1207 debug(
"%s", regnames[rt]);
1209 debug(
",%i(%s)", imm, regnames[rs]);
1215 debug(
"0x%08" PRIx32,
1216 (uint32_t) (cpu->
cd.
mips.
gpr[rs] + imm));
1218 debug(
"0x%016" PRIx64,
1219 (uint64_t) (cpu->
cd.
mips.
gpr[rs] + imm));
1222 debug(
" = %s", symbol);
1234 imm = (((instr[3] & 3) << 24) + (instr[2] << 16) +
1235 (instr[1] << 8) + instr[0]) << 2;
1236 addr = (dumpaddr + 4) & ~((1 << 28) - 1);
1240 debug(
"%s\t0x", hi6_names[hi6]);
1242 debug(
"%08" PRIx32, (uint32_t) addr);
1244 debug(
"%016" PRIx64, (uint64_t) addr);
1246 debug(
"\t<%s>", symbol);
1253 imm = (instr[3] << 24) + (instr[2] << 16) +
1254 (instr[1] << 8) + instr[0];
1255 imm &= ((1 << 26) - 1);
1260 return sizeof(instrword);
1263 rt = ((instr[3] & 3) << 3) + (instr[2] >> 5);
1264 copz = instr[2] & 31;
1265 imm = (instr[1] << 8) + instr[0];
1266 cache_op = copz >> 2;
1267 which_cache = copz & 3;
1269 debug(
"cache\t0x%02x,0x%04x(%s)", copz, imm, regnames[rt]);
1270 if (which_cache==0)
debug(
" [ primary I-cache");
1271 if (which_cache==1)
debug(
" [ primary D-cache");
1272 if (which_cache==2)
debug(
" [ secondary I-cache");
1273 if (which_cache==3)
debug(
" [ secondary D-cache");
1275 if (cache_op==0)
debug(
"index invalidate");
1276 if (cache_op==1)
debug(
"index load tag");
1277 if (cache_op==2)
debug(
"index store tag"), showtag=1;
1278 if (cache_op==3)
debug(
"create dirty exclusive");
1279 if (cache_op==4)
debug(
"hit invalidate");
1280 if (cache_op==5)
debug(
"fill OR hit writeback invalidate");
1281 if (cache_op==6)
debug(
"hit writeback");
1282 if (cache_op==7)
debug(
"hit set virtual");
1284 debug(
", addr 0x%016" PRIx64,
1285 (uint64_t)(cpu->
cd.
mips.
gpr[rt] + imm));
1287 debug(
", taghi=%08lx lo=%08lx",
1294 special6 = instr[0] & 0x3f;
1295 instrword = (instr[3] << 24) + (instr[2] << 16) +
1296 (instr[1] << 8) + instr[0];
1297 rs = ((instr[3] & 3) << 3) + ((instr[2] >> 5) & 7);
1299 rd = (instr[1] >> 3) & 31;
1302 int c790mmifunc = (instrword >> 6) & 0x1f;
1305 debug(
"%s\t", mmi_names[special6]);
1312 debug(
"%s,", regnames[rd]);
1314 debug(
"%s,%s", regnames[rs], regnames[rt]);
1318 debug(
"%s\t", mmi0_names[c790mmifunc]);
1319 switch (c790mmifunc) {
1329 debug(
"%s,%s,%s", regnames[rd],
1330 regnames[rs], regnames[rt]);
1333 default:
debug(
"(UNIMPLEMENTED)");
1338 debug(
"%s\t", mmi1_names[c790mmifunc]);
1339 switch (c790mmifunc) {
1346 debug(
"%s,%s,%s", regnames[rd],
1347 regnames[rs], regnames[rt]);
1350 default:
debug(
"(UNIMPLEMENTED)");
1355 debug(
"%s\t", mmi2_names[c790mmifunc]);
1356 switch (c790mmifunc) {
1360 debug(
"%s", regnames[rd]);
1373 debug(
"%s,%s,%s", regnames[rd],
1374 regnames[rs], regnames[rt]);
1377 default:
debug(
"(UNIMPLEMENTED)");
1382 debug(
"%s\t", mmi3_names[c790mmifunc]);
1383 switch (c790mmifunc) {
1387 debug(
"%s", regnames[rs]);
1396 debug(
"%s,%s,%s", regnames[rd],
1397 regnames[rs], regnames[rt]);
1400 default:
debug(
"(UNIMPLEMENTED)");
1404 default:
debug(
"(UNIMPLEMENTED)");
1410 debug(
"%s\t", special2_names[special6]);
1419 debug(
"WEIRD_NONZERO_RD(%s),",
1422 debug(
"%s,%s", regnames[rs], regnames[rt]);
1427 debug(
"%s,%s,%s", regnames[rd],
1428 regnames[rs], regnames[rt]);
1435 debug(
"%s,%s", regnames[rd], regnames[rs]);
1439 debug(
"(UNIMPLEMENTED)");
1444 regimm5 = instr[2] & 0x1f;
1445 rs = ((instr[3] & 3) << 3) + ((instr[2] >> 5) & 7);
1446 imm = (instr[1] << 8) + instr[0];
1460 debug(
"%s\t%s,", regimm_names[regimm5], regnames[rs]);
1462 addr = (dumpaddr + 4) + (imm << 2);
1465 debug(
"0x%08" PRIx32, (uint32_t) addr);
1467 debug(
"0x%016" PRIx64, (uint64_t) addr);
1471 debug(
"%s\t%i(%s)", regimm_names[regimm5],
1476 debug(
"unimplemented regimm5 = 0x%02x", regimm5);
1480 debug(
"unimplemented hi6 = 0x%02x", hi6);
1485 return sizeof(instrword);
1499 int coprocnr, i, bits32;
1512 debug(
"cpu%i: pc = %08" PRIx32,
1515 debug(
"cpu%i: pc=%016" PRIx64,
1518 debug(
"cpu%i: pc = 0x%016" PRIx64,
1521 debug(
" <%s>\n", symbol != NULL? symbol :
1525 debug(
"cpu%i: hi = %08" PRIx32
" lo = %08" PRIx32
"\n",
1529 debug(
"cpu%i: hi=%016" PRIx64
"%016" PRIx64
" lo=" 1530 "%016" PRIx64
"%016" PRIx64
"\n", cpu->
cpu_id,
1534 debug(
"cpu%i: hi = 0x%016" PRIx64
" lo = 0x%016" 1543 for (i=0; i<32; i++) {
1544 int r = (i >> 1) + ((i & 1) << 4);
1551 debug(
" %3s=%016" PRIx64
"%016" PRIx64,
1552 regnames[r], (uint64_t)
1558 }
else if (bits32) {
1560 for (i=0; i<32; i++) {
1566 debug(
" %3s = %08" PRIx32, regnames[i],
1573 for (i=0; i<32; i++) {
1574 int r = (i >> 1) + ((i & 1) << 4);
1580 debug(
" %3s = 0x%016" PRIx64,
1589 for (coprocnr=0; coprocnr<4; coprocnr++) {
1595 if (!(coprocs & (1<<coprocnr)))
1598 debug(
"cpu%i: no coprocessor %i\n",
1604 for (i=0; i<32; i++) {
1610 debug(
" %8s", cop0_names[i]);
1612 debug(
" c%i,%02i", coprocnr, i);
1616 coproc[coprocnr]->reg[i]);
1625 debug(
" = 0x%016" PRIx64, (uint64_t)
1630 if ((i & nm1) == nm1)
1641 debug(
"config_select1 = 0x");
1646 debug(
"%016" PRIx64,
1652 if (coprocnr == 1) {
1653 for (i=0; i<32; i++)
1656 printf(
"cpu%i: fcr0 (fcir) = 0x%08x\n",
1658 coproc[coprocnr]->fcr[i]);
1661 printf(
"cpu%i: fcr25 (fccr) = 0x%08x\n",
1663 coproc[coprocnr]->fcr[i]);
1666 printf(
"cpu%i: fcr31 (fcsr) = 0x%08x\n",
1668 coproc[coprocnr]->fcr[i]);
1675 printf(
"cpu%i: Read-Modify-Write in progress, address " 1689 struct cpu *
cpu = (
struct cpu *) interrupt->
extra;
1694 struct cpu *
cpu = (
struct cpu *) interrupt->
extra;
1715 int coproc_nr, uint64_t vaddr_vpn2,
int vaddr_asid,
int x_64)
1728 cpu->
pc +=
sizeof(uint32_t);
1741 debug(
"exception %s%s",
1742 exception_names[exccode], tlb?
" <tlb>" :
"");
1747 debug(
" cause_im=0x%02x", (
int)
1754 for (x=0; x<4; x++) {
1758 if (d > -256 && d < 256) {
1759 debug(
" a%i=%i", x, (
int)d);
1762 debug(
" a%i=\"%s\"", x,
1764 d, strbuf,
sizeof(strbuf)));
1767 debug(
" a%i=0x%" PRIx32, x,
1770 debug(
" a%i=0x%" PRIx64, x,
1777 debug(
" coproc_nr=%i", coproc_nr);
1782 debug(
" vaddr=0x%08x", (
int)vaddr);
1784 debug(
" vaddr=0x%016" PRIx64, (uint64_t)vaddr);
1788 debug(
" pc=0x%08" PRIx32
" ", (uint32_t)cpu->
pc);
1790 debug(
" pc=0x%016" PRIx64
" ", (uint64_t)cpu->
pc);
1793 debug(
"<%s> ]\n", symbol);
1798 if (tlb && vaddr < 0x1000) {
1805 fatal(
"warning: LOW reference: vaddr=");
1807 fatal(
"0x%08" PRIx32, (uint32_t) vaddr);
1809 fatal(
"0x%016" PRIx64, (uint64_t) vaddr);
1810 fatal(
", exception %s, pc=", exception_names[exccode]);
1812 fatal(
"0x%08" PRIx32, (uint32_t) cpu->
pc);
1814 fatal(
"0x%016" PRIx64, (uint64_t)cpu->
pc);
1815 fatal(
" <%s> ]\n", symbol? symbol :
"(no symbol)");
1819 if (exc_model ==
EXC3K)
1837 if (exc_model ==
EXC3K) {
1911 base = 0xffffffffbfc00200ULL;
1913 base = 0xffffffff80000000ULL;
1915 switch (exc_model) {
1918 if (tlb && !(vaddr & 0x80000000ULL) &&
1920 cpu->
pc = base + 0x000;
1922 cpu->
pc = base + 0x080;
1939 cpu->
pc = base + 0x080;
1941 cpu->
pc = base + 0x000;
1945 cpu->
pc = base + 0x200;
1947 cpu->
pc = base + 0x180;
1951 if (exc_model ==
EXC3K) {
#define MIPS_REGISTER_NAMES
void fatal(const char *fmt,...)
int cache_secondary_linesize
void mips_cpu_list_available_types(void)
#define DEBUG_INDENTATION
void(* interrupt_assert)(struct interrupt *)
int(* translate_v2p)(struct cpu *, uint64_t vaddr, uint64_t *return_paddr, int flags)
#define ENTRYHI_VPN2_MASK_R10K
int store_32bit_word(struct cpu *cpu, uint64_t addr, uint64_t data32)
#define DEFAULT_PCACHE_LINESIZE
#define R2K3K_CAUSE_EXCCODE_MASK
int mips_cpu_new(struct cpu *cpu, struct memory *mem, struct machine *machine, int cpu_id, char *cpu_type_name)
#define R2K3K_ENTRYHI_ASID_MASK
uint64_t cache_last_paddr[2]
void coproc_function(struct cpu *cpu, struct mips_coproc *cp, int cpnr, uint32_t function, int unassemble_only, int running)
#define R2K3K_ENTRYLO_PFN_MASK
int translate_v2p_mmu4100(struct cpu *cpu, uint64_t vaddr, uint64_t *return_addr, int flags)
void interrupt_handler_register(struct interrupt *templ)
void(* interrupt_deassert)(struct interrupt *)
int memory_points_to_string(struct cpu *cpu, struct memory *mem, uint64_t addr, int min_string_length)
int mips_cpu_instruction_has_delayslot(struct cpu *cpu, unsigned char *ib)
#define R2K3K_INDEX_SHIFT
int mips32_run_instr(struct cpu *cpu)
#define R2K3K_ENTRYHI_ASID_SHIFT
#define CONTEXT_BADVPN2_MASK_R4100
void mips32_pc_to_pointers(struct cpu *)
int(* run_instr)(struct cpu *cpu)
#define ENTRYHI_VPN2_MASK
int cache_pdcache_linesize
char * get_symbol_name(struct symbol_context *, uint64_t addr, uint64_t *offset)
void mips32_invalidate_translation_caches(struct cpu *cpu, uint64_t, int)
void mips_pc_to_pointers(struct cpu *)
void mips_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, unsigned char *host_page, int writeflag, uint64_t paddr_page)
#define CAUSE_EXCCODE_MASK
#define EMUL_LITTLE_ENDIAN
#define CHECK_ALLOCATION(ptr)
int mips_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr, unsigned char *data, size_t len, int writeflag, int cache_flags)
uint64_t reg[N_MIPS_COPROC_REGS]
#define R2K3K_CONTEXT_BADVPN_SHIFT
int(* memory_rw)(struct cpu *cpu, struct memory *mem, uint64_t vaddr, unsigned char *data, size_t len, int writeflag, int cache_flags)
int cache_picache_linesize
#define XCONTEXT_BADVPN2_MASK
#define R2K3K_ENTRYHI_VPN_MASK
struct interrupt irq_compare
#define CONTEXT_BADVPN2_SHIFT
int translate_v2p_mmu3k(struct cpu *cpu, uint64_t vaddr, uint64_t *return_addr, int flags)
#define ENTRYLO_PFN_SHIFT
#define N_MIPS_COPROC_REGS
void mips_invalidate_code_translation(struct cpu *cpu, uint64_t, int)
void mips_cpu_exception(struct cpu *cpu, int exccode, int tlb, uint64_t vaddr, int coproc_nr, uint64_t vaddr_vpn2, int vaddr_asid, int x_64)
#define R2K3K_RANDOM_SHIFT
#define CAUSE_EXCCODE_SHIFT
struct mips_coproc * coproc[N_MIPS_COPROCS]
void mips_cpu_interrupt_deassert(struct interrupt *interrupt)
#define CONTEXT_BADVPN2_MASK
void mips_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs)
struct mips_coproc * mips_coproc_new(struct cpu *cpu, int coproc_nr)
int mips_run_instr(struct cpu *cpu)
void mips_cpu_dumpinfo(struct cpu *cpu)
int translate_v2p_mmu8k(struct cpu *cpu, uint64_t vaddr, uint64_t *return_addr, int flags)
void mips32_invalidate_code_translation(struct cpu *cpu, uint64_t, int)
#define MIPS_CPU_TYPE_DEFS
uint64_t gpr_quadhi[N_MIPS_GPRS]
#define INTERRUPT_CONNECT(name, istruct)
#define XCONTEXT_BADVPN2_SHIFT
int(* instruction_has_delayslot)(struct cpu *cpu, unsigned char *ib)
void COMBINE() strlen(struct cpu *cpu, struct arm_instr_call *ic, int low_addr)
#define CACHE_INSTRUCTION
#define R2K3K_RANDOM_MASK
uint64_t cop0_config_select1
void debug_indentation(int diff)
struct symbol_context symbol_context
int translate_v2p_mmu10k(struct cpu *cpu, uint64_t vaddr, uint64_t *return_addr, int flags)
void mips_invalidate_translation_caches(struct cpu *cpu, uint64_t, int)
char * memory_conv_to_string(struct cpu *cpu, struct memory *mem, uint64_t addr, char *buf, int bufsize)
void mips_cpu_tlbdump(struct machine *m, int x, int rawflag)
#define EXCEPTION_IN_DELAY_SLOT
void(* update_translation_table)(struct cpu *, uint64_t vaddr_page, unsigned char *host_page, int writeflag, uint64_t paddr_page)
uint64_t gpr[N_MIPS_GPRS]
#define DEFAULT_PCACHE_SIZE
void mips32_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, unsigned char *host_page, int writeflag, uint64_t paddr_page)
#define SPECIAL_ROT_NAMES
#define INITIAL_STACK_POINTER
void(* invalidate_code_translation)(struct cpu *, uint64_t paddr, int flags)
struct mips_cpu_type_def cpu_type
#define CPU_SETTINGS_ADD_REGISTER64(name, var)
#define R2K3K_CONTEXT_BADVPN_MASK
void mips_cpu_interrupt_assert(struct interrupt *interrupt)
int translate_v2p_generic(struct cpu *cpu, uint64_t vaddr, uint64_t *return_addr, int flags)
void(* invalidate_translation_caches)(struct cpu *, uint64_t paddr, int flags)
int mips_cpu_disassemble_instr(struct cpu *cpu, unsigned char *originstr, int running, uint64_t dumpaddr)