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#define | __attribute__(x) /* */ |
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#define | __noreturn__ /* */ |
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#define | PCI_ID_REG 0x00 |
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#define | PCI_VENDOR_SHIFT 0 |
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#define | PCI_VENDOR_MASK 0xffff |
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#define | PCI_VENDOR(id) (((id) >> PCI_VENDOR_SHIFT) & PCI_VENDOR_MASK) |
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#define | PCI_PRODUCT_SHIFT 16 |
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#define | PCI_PRODUCT_MASK 0xffff |
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#define | PCI_PRODUCT(id) (((id) >> PCI_PRODUCT_SHIFT) & PCI_PRODUCT_MASK) |
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#define | PCI_ID_CODE(vid, pid) |
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#define | PCI_COMMAND_STATUS_REG 0x04 |
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#define | PCI_COMMAND_SHIFT 0 |
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#define | PCI_COMMAND_MASK 0xffff |
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#define | PCI_STATUS_SHIFT 16 |
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#define | PCI_STATUS_MASK 0xffff |
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#define | PCI_COMMAND_STATUS_CODE(cmd, stat) |
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#define | PCI_COMMAND_IO_ENABLE 0x00000001 |
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#define | PCI_COMMAND_MEM_ENABLE 0x00000002 |
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#define | PCI_COMMAND_MASTER_ENABLE 0x00000004 |
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#define | PCI_COMMAND_SPECIAL_ENABLE 0x00000008 |
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#define | PCI_COMMAND_INVALIDATE_ENABLE 0x00000010 |
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#define | PCI_COMMAND_PALETTE_ENABLE 0x00000020 |
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#define | PCI_COMMAND_PARITY_ENABLE 0x00000040 |
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#define | PCI_COMMAND_STEPPING_ENABLE 0x00000080 |
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#define | PCI_COMMAND_SERR_ENABLE 0x00000100 |
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#define | PCI_COMMAND_BACKTOBACK_ENABLE 0x00000200 |
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#define | PCI_STATUS_CAPLIST_SUPPORT 0x00100000 |
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#define | PCI_STATUS_66MHZ_SUPPORT 0x00200000 |
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#define | PCI_STATUS_UDF_SUPPORT 0x00400000 |
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#define | PCI_STATUS_BACKTOBACK_SUPPORT 0x00800000 |
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#define | PCI_STATUS_PARITY_ERROR 0x01000000 |
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#define | PCI_STATUS_DEVSEL_FAST 0x00000000 |
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#define | PCI_STATUS_DEVSEL_MEDIUM 0x02000000 |
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#define | PCI_STATUS_DEVSEL_SLOW 0x04000000 |
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#define | PCI_STATUS_DEVSEL_MASK 0x06000000 |
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#define | PCI_STATUS_TARGET_TARGET_ABORT 0x08000000 |
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#define | PCI_STATUS_MASTER_TARGET_ABORT 0x10000000 |
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#define | PCI_STATUS_MASTER_ABORT 0x20000000 |
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#define | PCI_STATUS_SPECIAL_ERROR 0x40000000 |
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#define | PCI_STATUS_PARITY_DETECT 0x80000000 |
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#define | PCI_CLASS_REG 0x08 |
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#define | PCI_CLASS_SHIFT 24 |
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#define | PCI_CLASS_MASK 0xff |
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#define | PCI_CLASS(cr) (((cr) >> PCI_CLASS_SHIFT) & PCI_CLASS_MASK) |
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#define | PCI_SUBCLASS_SHIFT 16 |
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#define | PCI_SUBCLASS_MASK 0xff |
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#define | PCI_SUBCLASS(cr) (((cr) >> PCI_SUBCLASS_SHIFT) & PCI_SUBCLASS_MASK) |
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#define | PCI_INTERFACE_SHIFT 8 |
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#define | PCI_INTERFACE_MASK 0xff |
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#define | PCI_INTERFACE(cr) (((cr) >> PCI_INTERFACE_SHIFT) & PCI_INTERFACE_MASK) |
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#define | PCI_REVISION_SHIFT 0 |
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#define | PCI_REVISION_MASK 0xff |
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#define | PCI_REVISION(cr) (((cr) >> PCI_REVISION_SHIFT) & PCI_REVISION_MASK) |
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#define | PCI_CLASS_CODE(mainclass, subclass, interface) |
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#define | PCI_CLASS_PREHISTORIC 0x00 |
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#define | PCI_CLASS_MASS_STORAGE 0x01 |
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#define | PCI_CLASS_NETWORK 0x02 |
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#define | PCI_CLASS_DISPLAY 0x03 |
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#define | PCI_CLASS_MULTIMEDIA 0x04 |
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#define | PCI_CLASS_MEMORY 0x05 |
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#define | PCI_CLASS_BRIDGE 0x06 |
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#define | PCI_CLASS_COMMUNICATIONS 0x07 |
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#define | PCI_CLASS_SYSTEM 0x08 |
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#define | PCI_CLASS_INPUT 0x09 |
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#define | PCI_CLASS_DOCK 0x0a |
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#define | PCI_CLASS_PROCESSOR 0x0b |
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#define | PCI_CLASS_SERIALBUS 0x0c |
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#define | PCI_CLASS_WIRELESS 0x0d |
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#define | PCI_CLASS_I2O 0x0e |
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#define | PCI_CLASS_SATCOM 0x0f |
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#define | PCI_CLASS_CRYPTO 0x10 |
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#define | PCI_CLASS_DASP 0x11 |
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#define | PCI_CLASS_UNDEFINED 0xff |
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#define | PCI_SUBCLASS_PREHISTORIC_MISC 0x00 |
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#define | PCI_SUBCLASS_PREHISTORIC_VGA 0x01 |
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#define | PCI_SUBCLASS_MASS_STORAGE_SCSI 0x00 |
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#define | PCI_SUBCLASS_MASS_STORAGE_IDE 0x01 |
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#define | PCI_SUBCLASS_MASS_STORAGE_FLOPPY 0x02 |
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#define | PCI_SUBCLASS_MASS_STORAGE_IPI 0x03 |
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#define | PCI_SUBCLASS_MASS_STORAGE_RAID 0x04 |
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#define | PCI_SUBCLASS_MASS_STORAGE_ATA 0x05 |
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#define | PCI_SUBCLASS_MASS_STORAGE_MISC 0x80 |
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#define | PCI_SUBCLASS_NETWORK_ETHERNET 0x00 |
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#define | PCI_SUBCLASS_NETWORK_TOKENRING 0x01 |
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#define | PCI_SUBCLASS_NETWORK_FDDI 0x02 |
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#define | PCI_SUBCLASS_NETWORK_ATM 0x03 |
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#define | PCI_SUBCLASS_NETWORK_ISDN 0x04 |
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#define | PCI_SUBCLASS_NETWORK_WORLDFIP 0x05 |
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#define | PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP 0x06 |
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#define | PCI_SUBCLASS_NETWORK_MISC 0x80 |
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#define | PCI_SUBCLASS_DISPLAY_VGA 0x00 |
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#define | PCI_SUBCLASS_DISPLAY_XGA 0x01 |
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#define | PCI_SUBCLASS_DISPLAY_3D 0x02 |
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#define | PCI_SUBCLASS_DISPLAY_MISC 0x80 |
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#define | PCI_SUBCLASS_MULTIMEDIA_VIDEO 0x00 |
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#define | PCI_SUBCLASS_MULTIMEDIA_AUDIO 0x01 |
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#define | PCI_SUBCLASS_MULTIMEDIA_TELEPHONY 0x02 |
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#define | PCI_SUBCLASS_MULTIMEDIA_MISC 0x80 |
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#define | PCI_SUBCLASS_MEMORY_RAM 0x00 |
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#define | PCI_SUBCLASS_MEMORY_FLASH 0x01 |
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#define | PCI_SUBCLASS_MEMORY_MISC 0x80 |
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#define | PCI_SUBCLASS_BRIDGE_HOST 0x00 |
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#define | PCI_SUBCLASS_BRIDGE_ISA 0x01 |
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#define | PCI_SUBCLASS_BRIDGE_EISA 0x02 |
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#define | PCI_SUBCLASS_BRIDGE_MC 0x03 /* XXX _MCA? */ |
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#define | PCI_SUBCLASS_BRIDGE_PCI 0x04 |
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#define | PCI_SUBCLASS_BRIDGE_PCMCIA 0x05 |
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#define | PCI_SUBCLASS_BRIDGE_NUBUS 0x06 |
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#define | PCI_SUBCLASS_BRIDGE_CARDBUS 0x07 |
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#define | PCI_SUBCLASS_BRIDGE_RACEWAY 0x08 |
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#define | PCI_SUBCLASS_BRIDGE_STPCI 0x09 |
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#define | PCI_SUBCLASS_BRIDGE_INFINIBAND 0x0a |
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#define | PCI_SUBCLASS_BRIDGE_MISC 0x80 |
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#define | PCI_SUBCLASS_COMMUNICATIONS_SERIAL 0x00 |
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#define | PCI_SUBCLASS_COMMUNICATIONS_PARALLEL 0x01 |
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#define | PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL 0x02 |
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#define | PCI_SUBCLASS_COMMUNICATIONS_MODEM 0x03 |
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#define | PCI_SUBCLASS_COMMUNICATIONS_GPIB 0x04 |
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#define | PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD 0x05 |
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#define | PCI_SUBCLASS_COMMUNICATIONS_MISC 0x80 |
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#define | PCI_SUBCLASS_SYSTEM_PIC 0x00 |
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#define | PCI_SUBCLASS_SYSTEM_DMA 0x01 |
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#define | PCI_SUBCLASS_SYSTEM_TIMER 0x02 |
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#define | PCI_SUBCLASS_SYSTEM_RTC 0x03 |
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#define | PCI_SUBCLASS_SYSTEM_PCIHOTPLUG 0x04 |
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#define | PCI_SUBCLASS_SYSTEM_MISC 0x80 |
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#define | PCI_SUBCLASS_INPUT_KEYBOARD 0x00 |
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#define | PCI_SUBCLASS_INPUT_DIGITIZER 0x01 |
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#define | PCI_SUBCLASS_INPUT_MOUSE 0x02 |
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#define | PCI_SUBCLASS_INPUT_SCANNER 0x03 |
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#define | PCI_SUBCLASS_INPUT_GAMEPORT 0x04 |
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#define | PCI_SUBCLASS_INPUT_MISC 0x80 |
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#define | PCI_SUBCLASS_DOCK_GENERIC 0x00 |
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#define | PCI_SUBCLASS_DOCK_MISC 0x80 |
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#define | PCI_SUBCLASS_PROCESSOR_386 0x00 |
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#define | PCI_SUBCLASS_PROCESSOR_486 0x01 |
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#define | PCI_SUBCLASS_PROCESSOR_PENTIUM 0x02 |
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#define | PCI_SUBCLASS_PROCESSOR_ALPHA 0x10 |
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#define | PCI_SUBCLASS_PROCESSOR_POWERPC 0x20 |
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#define | PCI_SUBCLASS_PROCESSOR_MIPS 0x30 |
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#define | PCI_SUBCLASS_PROCESSOR_COPROC 0x40 |
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#define | PCI_SUBCLASS_SERIALBUS_FIREWIRE 0x00 |
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#define | PCI_SUBCLASS_SERIALBUS_ACCESS 0x01 |
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#define | PCI_SUBCLASS_SERIALBUS_SSA 0x02 |
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#define | PCI_SUBCLASS_SERIALBUS_USB 0x03 |
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#define | PCI_SUBCLASS_SERIALBUS_FIBER 0x04 /* XXX _FIBRECHANNEL */ |
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#define | PCI_SUBCLASS_SERIALBUS_SMBUS 0x05 |
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#define | PCI_SUBCLASS_SERIALBUS_INFINIBAND 0x06 |
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#define | PCI_SUBCLASS_SERIALBUS_IPMI 0x07 |
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#define | PCI_SUBCLASS_SERIALBUS_SERCOS 0x08 |
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#define | PCI_SUBCLASS_SERIALBUS_CANBUS 0x09 |
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#define | PCI_SUBCLASS_WIRELESS_IRDA 0x00 |
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#define | PCI_SUBCLASS_WIRELESS_CONSUMERIR 0x01 |
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#define | PCI_SUBCLASS_WIRELESS_RF 0x10 |
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#define | PCI_SUBCLASS_WIRELESS_BLUETOOTH 0x11 |
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#define | PCI_SUBCLASS_WIRELESS_BROADBAND 0x12 |
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#define | PCI_SUBCLASS_WIRELESS_MISC 0x80 |
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#define | PCI_SUBCLASS_I2O_STANDARD 0x00 |
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#define | PCI_SUBCLASS_SATCOM_TV 0x01 |
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#define | PCI_SUBCLASS_SATCOM_AUDIO 0x02 |
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#define | PCI_SUBCLASS_SATCOM_VOICE 0x03 |
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#define | PCI_SUBCLASS_SATCOM_DATA 0x04 |
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#define | PCI_SUBCLASS_CRYPTO_NETCOMP 0x00 |
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#define | PCI_SUBCLASS_CRYPTO_ENTERTAINMENT 0x10 |
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#define | PCI_SUBCLASS_CRYPTO_MISC 0x80 |
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#define | PCI_SUBCLASS_DASP_DPIO 0x00 |
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#define | PCI_SUBCLASS_DASP_TIMEFREQ 0x01 |
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#define | PCI_SUBCLASS_DASP_SYNC 0x10 |
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#define | PCI_SUBCLASS_DASP_MGMT 0x20 |
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#define | PCI_SUBCLASS_DASP_MISC 0x80 |
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#define | PCI_BHLC_REG 0x0c |
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#define | PCI_BIST_SHIFT 24 |
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#define | PCI_BIST_MASK 0xff |
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#define | PCI_BIST(bhlcr) (((bhlcr) >> PCI_BIST_SHIFT) & PCI_BIST_MASK) |
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#define | PCI_HDRTYPE_SHIFT 16 |
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#define | PCI_HDRTYPE_MASK 0xff |
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#define | PCI_HDRTYPE(bhlcr) (((bhlcr) >> PCI_HDRTYPE_SHIFT) & PCI_HDRTYPE_MASK) |
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#define | PCI_HDRTYPE_TYPE(bhlcr) (PCI_HDRTYPE(bhlcr) & 0x7f) |
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#define | PCI_HDRTYPE_MULTIFN(bhlcr) ((PCI_HDRTYPE(bhlcr) & 0x80) != 0) |
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#define | PCI_LATTIMER_SHIFT 8 |
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#define | PCI_LATTIMER_MASK 0xff |
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#define | PCI_LATTIMER(bhlcr) (((bhlcr) >> PCI_LATTIMER_SHIFT) & PCI_LATTIMER_MASK) |
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#define | PCI_CACHELINE_SHIFT 0 |
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#define | PCI_CACHELINE_MASK 0xff |
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#define | PCI_CACHELINE(bhlcr) (((bhlcr) >> PCI_CACHELINE_SHIFT) & PCI_CACHELINE_MASK) |
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#define | PCI_BHLC_CODE(bist, type, multi, latency, cacheline) |
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#define | PCI_MAPREG_START 0x10 |
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#define | PCI_MAPREG_END 0x28 |
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#define | PCI_MAPREG_ROM 0x30 |
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#define | PCI_MAPREG_PPB_END 0x18 |
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#define | PCI_MAPREG_PCB_END 0x14 |
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#define | PCI_MAPREG_TYPE(mr) ((mr) & PCI_MAPREG_TYPE_MASK) |
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#define | PCI_MAPREG_TYPE_MASK 0x00000001 |
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#define | PCI_MAPREG_TYPE_MEM 0x00000000 |
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#define | PCI_MAPREG_TYPE_IO 0x00000001 |
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#define | PCI_MAPREG_ROM_ENABLE 0x00000001 |
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#define | PCI_MAPREG_MEM_TYPE(mr) ((mr) & PCI_MAPREG_MEM_TYPE_MASK) |
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#define | PCI_MAPREG_MEM_TYPE_MASK 0x00000006 |
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#define | PCI_MAPREG_MEM_TYPE_32BIT 0x00000000 |
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#define | PCI_MAPREG_MEM_TYPE_32BIT_1M 0x00000002 |
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#define | PCI_MAPREG_MEM_TYPE_64BIT 0x00000004 |
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#define | PCI_MAPREG_MEM_PREFETCHABLE(mr) (((mr) & PCI_MAPREG_MEM_PREFETCHABLE_MASK) != 0) |
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#define | PCI_MAPREG_MEM_PREFETCHABLE_MASK 0x00000008 |
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#define | PCI_MAPREG_MEM_ADDR(mr) ((mr) & PCI_MAPREG_MEM_ADDR_MASK) |
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#define | PCI_MAPREG_MEM_SIZE(mr) (PCI_MAPREG_MEM_ADDR(mr) & -PCI_MAPREG_MEM_ADDR(mr)) |
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#define | PCI_MAPREG_MEM_ADDR_MASK 0xfffffff0 |
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#define | PCI_MAPREG_MEM64_ADDR(mr) ((mr) & PCI_MAPREG_MEM64_ADDR_MASK) |
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#define | PCI_MAPREG_MEM64_SIZE(mr) (PCI_MAPREG_MEM64_ADDR(mr) & -PCI_MAPREG_MEM64_ADDR(mr)) |
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#define | PCI_MAPREG_MEM64_ADDR_MASK 0xfffffffffffffff0ULL |
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#define | PCI_MAPREG_IO_ADDR(mr) ((mr) & PCI_MAPREG_IO_ADDR_MASK) |
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#define | PCI_MAPREG_IO_SIZE(mr) (PCI_MAPREG_IO_ADDR(mr) & -PCI_MAPREG_IO_ADDR(mr)) |
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#define | PCI_MAPREG_IO_ADDR_MASK 0xfffffffc |
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#define | PCI_MAPREG_SIZE_TO_MASK(size) (-(size)) |
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#define | PCI_MAPREG_NUM(offset) (((unsigned)(offset)-PCI_MAPREG_START)/4) |
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#define | PCI_CARDBUS_CIS_REG 0x28 |
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#define | PCI_SUBSYS_ID_REG 0x2c |
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#define | PCI_CAPLISTPTR_REG 0x34 /* header type 0 */ |
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#define | PCI_CARDBUS_CAPLISTPTR_REG 0x14 /* header type 2 */ |
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#define | PCI_CAPLIST_PTR(cpr) ((cpr) & 0xff) |
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#define | PCI_CAPLIST_NEXT(cr) (((cr) >> 8) & 0xff) |
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#define | PCI_CAPLIST_CAP(cr) ((cr) & 0xff) |
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#define | PCI_CAP_RESERVED0 0x00 |
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#define | PCI_CAP_PWRMGMT 0x01 |
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#define | PCI_CAP_AGP 0x02 |
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#define | PCI_CAP_VPD 0x03 |
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#define | PCI_CAP_SLOTID 0x04 |
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#define | PCI_CAP_MBI 0x05 |
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#define | PCI_CAP_CPCI_HOTSWAP 0x06 |
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#define | PCI_CAP_PCIX 0x07 |
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#define | PCI_CAP_LDT 0x08 |
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#define | PCI_CAP_VENDSPEC 0x09 |
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#define | PCI_CAP_DEBUGPORT 0x0a |
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#define | PCI_CAP_CPCI_RSRCCTL 0x0b |
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#define | PCI_CAP_HOTPLUG 0x0c |
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#define | PCI_PMCSR_STATE_MASK 0x03 |
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#define | PCI_PMCSR_STATE_D0 0x00 |
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#define | PCI_PMCSR_STATE_D1 0x01 |
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#define | PCI_PMCSR_STATE_D2 0x02 |
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#define | PCI_PMCSR_STATE_D3 0x03 |
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#define | PCI_INTERRUPT_REG 0x3c |
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#define | PCI_MAX_LAT_SHIFT 24 |
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#define | PCI_MAX_LAT_MASK 0xff |
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#define | PCI_MAX_LAT(icr) (((icr) >> PCI_MAX_LAT_SHIFT) & PCI_MAX_LAT_MASK) |
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#define | PCI_MIN_GNT_SHIFT 16 |
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#define | PCI_MIN_GNT_MASK 0xff |
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#define | PCI_MIN_GNT(icr) (((icr) >> PCI_MIN_GNT_SHIFT) & PCI_MIN_GNT_MASK) |
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#define | PCI_INTERRUPT_GRANT_SHIFT 24 |
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#define | PCI_INTERRUPT_GRANT_MASK 0xff |
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#define | PCI_INTERRUPT_GRANT(icr) (((icr) >> PCI_INTERRUPT_GRANT_SHIFT) & PCI_INTERRUPT_GRANT_MASK) |
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#define | PCI_INTERRUPT_LATENCY_SHIFT 16 |
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#define | PCI_INTERRUPT_LATENCY_MASK 0xff |
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#define | PCI_INTERRUPT_LATENCY(icr) (((icr) >> PCI_INTERRUPT_LATENCY_SHIFT) & PCI_INTERRUPT_LATENCY_MASK) |
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#define | PCI_INTERRUPT_PIN_SHIFT 8 |
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#define | PCI_INTERRUPT_PIN_MASK 0xff |
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#define | PCI_INTERRUPT_PIN(icr) (((icr) >> PCI_INTERRUPT_PIN_SHIFT) & PCI_INTERRUPT_PIN_MASK) |
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#define | PCI_INTERRUPT_LINE_SHIFT 0 |
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#define | PCI_INTERRUPT_LINE_MASK 0xff |
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#define | PCI_INTERRUPT_LINE(icr) (((icr) >> PCI_INTERRUPT_LINE_SHIFT) & PCI_INTERRUPT_LINE_MASK) |
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#define | PCI_INTERRUPT_CODE(lat, gnt, pin, line) |
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#define | PCI_INTERRUPT_PIN_NONE 0x00 |
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#define | PCI_INTERRUPT_PIN_A 0x01 |
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#define | PCI_INTERRUPT_PIN_B 0x02 |
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#define | PCI_INTERRUPT_PIN_C 0x03 |
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#define | PCI_INTERRUPT_PIN_D 0x04 |
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#define | PCI_INTERRUPT_PIN_MAX 0x04 |
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#define | PCI_BRIDGE_BUS_REG 0x18 |
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#define | PCI_BRIDGE_BUS_PRIMARY_SHIFT 0 |
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#define | PCI_BRIDGE_BUS_SECONDARY_SHIFT 8 |
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#define | PCI_BRIDGE_BUS_SUBORDINATE_SHIFT 16 |
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#define | PCI_BRIDGE_STATIO_REG 0x1C |
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#define | PCI_BRIDGE_STATIO_IOBASE_SHIFT 0 |
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#define | PCI_BRIDGE_STATIO_IOLIMIT_SHIFT 8 |
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#define | PCI_BRIDGE_STATIO_STATUS_SHIFT 16 |
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#define | PCI_BRIDGE_STATIO_IOBASE_MASK 0xf0 |
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#define | PCI_BRIDGE_STATIO_IOLIMIT_MASK 0xf0 |
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#define | PCI_BRIDGE_STATIO_STATUS_MASK 0xffff |
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#define | PCI_BRIDGE_IO_32BITS(reg) (((reg) & 0xf) == 1) |
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#define | PCI_BRIDGE_MEMORY_REG 0x20 |
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#define | PCI_BRIDGE_MEMORY_BASE_SHIFT 4 |
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#define | PCI_BRIDGE_MEMORY_LIMIT_SHIFT 20 |
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#define | PCI_BRIDGE_MEMORY_BASE_MASK 0xffff |
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#define | PCI_BRIDGE_MEMORY_LIMIT_MASK 0xffff |
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#define | PCI_BRIDGE_PREFETCHMEM_REG 0x24 |
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#define | PCI_BRIDGE_PREFETCHMEM_BASE_SHIFT 4 |
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#define | PCI_BRIDGE_PREFETCHMEM_LIMIT_SHIFT 20 |
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#define | PCI_BRIDGE_PREFETCHMEM_BASE_MASK 0xffff |
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#define | PCI_BRIDGE_PREFETCHMEM_LIMIT_MASK 0xffff |
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#define | PCI_BRIDGE_PREFETCHMEM_64BITS(reg) ((reg) & 0xf) |
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#define | PCI_BRIDGE_PREFETCHBASE32_REG 0x28 |
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#define | PCI_BRIDGE_PREFETCHLIMIT32_REG 0x2C |
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#define | PCI_BRIDGE_IOHIGH_REG 0x30 |
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#define | PCI_BRIDGE_IOHIGH_BASE_SHIFT 0 |
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#define | PCI_BRIDGE_IOHIGH_LIMIT_SHIFT 16 |
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#define | PCI_BRIDGE_IOHIGH_BASE_MASK 0xffff |
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#define | PCI_BRIDGE_IOHIGH_LIMIT_MASK 0xffff |
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#define | PCI_BRIDGE_CONTROL_REG 0x3C |
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#define | PCI_BRIDGE_CONTROL_SHIFT 16 |
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#define | PCI_BRIDGE_CONTROL_MASK 0xffff |
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#define | PCI_BRIDGE_CONTROL_PERE (1 << 0) |
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#define | PCI_BRIDGE_CONTROL_SERR (1 << 1) |
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#define | PCI_BRIDGE_CONTROL_ISA (1 << 2) |
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#define | PCI_BRIDGE_CONTROL_VGA (1 << 3) |
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#define | PCI_BRIDGE_CONTROL_MABRT (1 << 5) |
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#define | PCI_BRIDGE_CONTROL_SECBR (1 << 6) |
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#define | PCI_BRIDGE_CONTROL_SECFASTB2B (1 << 7) |
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#define | PCI_BRIDGE_CONTROL_PRI_DISC_TIMER (1 << 8) |
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#define | PCI_BRIDGE_CONTROL_SEC_DISC_TIMER (1 << 9) |
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#define | PCI_BRIDGE_CONTROL_DISC_TIMER_STAT (1 << 10) |
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#define | PCI_BRIDGE_CONTROL_DISC_TIMER_SERR (1 << 11) |
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#define | PCI_VPDRES_ISLARGE(x) ((x) & 0x80) |
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#define | PCI_VPDRES_SMALL_LENGTH(x) ((x) & 0x7) |
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#define | PCI_VPDRES_SMALL_NAME(x) (((x) >> 3) & 0xf) |
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#define | PCI_VPDRES_LARGE_NAME(x) ((x) & 0x7f) |
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#define | PCI_VPDRES_TYPE_COMPATIBLE_DEVICE_ID 0x3 /* small */ |
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#define | PCI_VPDRES_TYPE_VENDOR_DEFINED 0xe /* small */ |
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#define | PCI_VPDRES_TYPE_END_TAG 0xf /* small */ |
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#define | PCI_VPDRES_TYPE_IDENTIFIER_STRING 0x02 /* large */ |
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#define | PCI_VPDRES_TYPE_VPD 0x10 /* large */ |
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