dev_i80321.cc Source File

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dev_i80321.cc
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1 /*
2  * Copyright (C) 2005-2009 Anders Gavare. All rights reserved.
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions are met:
6  *
7  * 1. Redistributions of source code must retain the above copyright
8  * notice, this list of conditions and the following disclaimer.
9  * 2. Redistributions in binary form must reproduce the above copyright
10  * notice, this list of conditions and the following disclaimer in the
11  * documentation and/or other materials provided with the distribution.
12  * 3. The name of the author may not be used to endorse or promote products
13  * derived from this software without specific prior written permission.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25  * SUCH DAMAGE.
26  *
27  *
28  * COMMENT: Intel i80321 (ARM) core functionality
29  *
30  * o) Interrupt controller
31  * o) Timer
32  * o) PCI controller
33  * o) Memory controller
34  * o) I2C
35  *
36  * TODO:
37  * o) More or less everything.
38  * o) This is hardcoded for little endian emulation.
39  */
40 
41 #include <stdio.h>
42 #include <stdlib.h>
43 #include <string.h>
44 
45 #include "bus_pci.h"
46 #include "cpu.h"
47 #include "device.h"
48 #include "machine.h"
49 #include "memory.h"
50 #include "misc.h"
51 #include "timer.h"
52 
53 #include "thirdparty/i80321reg.h"
54 #include "thirdparty/iopi2creg.h"
55 
56 
57 #define TICK_SHIFT 15
58 #define DEV_I80321_LENGTH VERDE_PMMR_SIZE
59 
60 struct i80321_data {
61  /* Interrupt Controller */
62  struct interrupt irq;
63  uint32_t *status; /* Note: these point to i80321_isrc */
64  uint32_t *enable; /* and i80321_inten in the CPU! */
65 
66  /* Timer: */
67  struct timer *timer;
68  double hz;
70 
71  /* PCI Controller: */
72  uint32_t pci_addr;
73  struct pci_data *pci_bus;
74 
75  /* Memory Controller: */
76  uint32_t mcu_reg[0x100 / sizeof(uint32_t)];
77 
78  /* I2C Controller: */
79  uint32_t i2c_reg[VERDE_I2C_SIZE / sizeof(uint32_t)];
80 };
81 
82 
83 static void i80321_assert(struct i80321_data *d, uint32_t linemask)
84 {
85  *d->status |= linemask;
86  if (*d->status & *d->enable)
88 }
89 static void i80321_deassert(struct i80321_data *d, uint32_t linemask)
90 {
91  *d->status &= ~linemask;
92  if (!(*d->status & *d->enable))
94 }
95 
96 
97 /*
98  * i80321_interrupt_assert():
99  * i80321_interrupt_deassert():
100  *
101  * Called whenever an i80321 interrupt is asserted/deasserted.
102  */
104 { i80321_assert((struct i80321_data *)interrupt->extra, interrupt->line); }
106 {
107  struct i80321_data *d = (struct i80321_data *) interrupt->extra;
108 
109  /* Ack. timer interrupts: */
110  if (interrupt->line == 1 << 9 &&
113 
114  i80321_deassert(d, interrupt->line);
115 }
116 
117 
118 /* TMR0 ticks, called d->hz times per second. */
119 static void tmr0_tick(struct timer *t, void *extra)
120 {
121  struct i80321_data *d = (struct i80321_data *) extra;
123 }
124 
125 
126 DEVICE_TICK(i80321)
127 {
128  struct i80321_data *d = (struct i80321_data *) extra;
129 
130  if (cpu->cd.arm.tmr0 & TMRx_ENABLE && d->pending_tmr0_interrupts > 0) {
131  i80321_assert(d, 1 << 9);
132  cpu->cd.arm.tisr |= TISR_TMR0;
133  } else {
134  i80321_deassert(d, 1 << 9);
135  cpu->cd.arm.tisr &= ~TISR_TMR0;
136  }
137 }
138 
139 
141 {
142  struct i80321_data *d = (struct i80321_data *) extra;
143  uint64_t idata = 0, odata = 0;
144  const char *n = NULL;
145  int bus, dev, func, reg;
146 
147  if (writeflag == MEM_WRITE)
148  idata = memory_readmax64(cpu, data, len);
149 
150  /* PCI configuration space: */
151  if (relative_addr >= 0x100 && relative_addr < 0x140) {
152  /* TODO */
153  goto ret;
154  }
155 
156  /* MCU registers: */
157  if (relative_addr >= VERDE_MCU_BASE &&
158  relative_addr < VERDE_MCU_BASE + VERDE_MCU_SIZE) {
159  int regnr = (relative_addr - VERDE_MCU_BASE) / sizeof(uint32_t);
160  if (writeflag == MEM_WRITE)
161  d->mcu_reg[regnr] = idata;
162  else
163  odata = d->mcu_reg[regnr];
164  }
165 
166  /* I2C registers: */
167  if (relative_addr >= VERDE_I2C_BASE &&
168  relative_addr < VERDE_I2C_BASE + VERDE_I2C_SIZE) {
169  int regnr = (relative_addr - VERDE_I2C_BASE) / sizeof(uint32_t);
170  if (writeflag == MEM_WRITE)
171  d->i2c_reg[regnr] = idata;
172  else
173  odata = d->i2c_reg[regnr];
174  }
175 
176 
177  switch (relative_addr) {
178 
179  /* Address Translation Unit: */
180  case VERDE_ATU_BASE + ATU_IALR0:
181  case VERDE_ATU_BASE + ATU_IATVR0:
182  case VERDE_ATU_BASE + ATU_IALR1:
183  case VERDE_ATU_BASE + ATU_IALR2:
184  case VERDE_ATU_BASE + ATU_IATVR2:
190  /* Ignoring these for now. TODO */
191  break;
192  case VERDE_ATU_BASE + ATU_ATUCR:
193  /* ATU configuration register; ignored for now. TODO */
194  break;
195  case VERDE_ATU_BASE + ATU_PCSR:
196  /* TODO: Temporary hack to allow NetBSD/evbarm to
197  reboot itself. Should be rewritten as soon as possible! */
198  if (writeflag == MEM_WRITE && idata == 0x30) {
199  int j;
200  for (j=0; j<cpu->machine->ncpus; j++)
201  cpu->machine->cpus[j]->running = 0;
203  }
204  break;
205  case VERDE_ATU_BASE + ATU_ATUIMR:
206  case VERDE_ATU_BASE + ATU_IABAR3:
208  case VERDE_ATU_BASE + ATU_IALR3:
209  case VERDE_ATU_BASE + ATU_IATVR3:
210  /* Ignoring these for now. TODO */
211  break;
212  case VERDE_ATU_BASE + ATU_OCCAR:
213  /* PCI address */
214  if (writeflag == MEM_WRITE) {
215  d->pci_addr = idata;
216  bus_pci_decompose_1(idata, &bus, &dev, &func, &reg);
217  bus = 0; /* NOTE */
218  bus_pci_setaddr(cpu, d->pci_bus, bus, dev, func, reg);
219  } else {
220  odata = d->pci_addr;
221  }
222  break;
223  case VERDE_ATU_BASE + ATU_OCCDR:
224  case VERDE_ATU_BASE + ATU_OCCDR + 1:
225  case VERDE_ATU_BASE + ATU_OCCDR + 2:
226  case VERDE_ATU_BASE + ATU_OCCDR + 3:
227  /* PCI data */
228  if (writeflag == MEM_READ) {
229  uint64_t tmp;
230  bus_pci_data_access(cpu, d->pci_bus, &tmp,
231  sizeof(uint32_t), MEM_READ);
232  switch (relative_addr) {
233  case VERDE_ATU_BASE + ATU_OCCDR + 1:
234  odata = tmp >> 8; break;
235  case VERDE_ATU_BASE + ATU_OCCDR + 2:
236  odata = tmp >> 16; break;
237  case VERDE_ATU_BASE + ATU_OCCDR + 3:
238  odata = tmp >> 24; break;
239  default:odata = tmp;
240  }
241  } else {
242  uint64_t tmp;
243  unsigned int i;
244  int r = relative_addr - (VERDE_ATU_BASE + ATU_OCCDR);
245  bus_pci_data_access(cpu, d->pci_bus, &tmp,
246  sizeof(uint32_t), MEM_READ);
247  for (i=0; i<len; i++) {
248  uint8_t b = idata >> (i*8);
249  tmp &= ~(0xff << ((r+i)*8));
250  tmp |= b << ((r+i)*8);
251  }
252  tmp &= 0xffffffff; /* needed because << is 32-bit */
253  bus_pci_data_access(cpu, d->pci_bus, &tmp,
254  sizeof(uint32_t), MEM_WRITE);
255  }
256  break;
257  case VERDE_ATU_BASE + ATU_PCIXSR:
258  odata = 0; /* TODO */
259  break;
260 
261  /* Memory Controller Unit: */
262  case VERDE_MCU_BASE + MCU_SDIR:
263  n = "MCU_SDIR (DDR SDRAM Init Register)";
264  break;
265  case VERDE_MCU_BASE + MCU_SDCR:
266  n = "MCU_SDCR (DDR SDRAM Control Register)";
267  break;
268  case VERDE_MCU_BASE + MCU_SDBR:
269  n = "MCU_SDBR (SDRAM Base Register)";
270  break;
271  case VERDE_MCU_BASE + MCU_SBR0:
272  n = "MCU_SBR0 (SDRAM Boundary 0)";
273  break;
274  case VERDE_MCU_BASE + MCU_SBR1:
275  n = "MCU_SBR1 (SDRAM Boundary 1)";
276  break;
277  case VERDE_MCU_BASE + MCU_ECCR:
278  n = "MCU_ECCR (ECC Control Register)";
279  break;
280  case VERDE_MCU_BASE + MCU_RFR:
281  n = "MCU_RFR (Refresh Frequency Register)";
282  break;
283  case VERDE_MCU_BASE + MCU_DBUDSR:
284  n = "MCU_DBUDSR (Data Bus Pull-up Drive Strength)";
285  break;
286  case VERDE_MCU_BASE + MCU_DBDDSR:
287  n = "MCU_DBDDSR (Data Bus Pull-down Drive Strength)";
288  break;
289  case VERDE_MCU_BASE + MCU_CUDSR:
290  n = "MCU_CUDSR (Clock Pull-up Drive Strength)";
291  break;
292  case VERDE_MCU_BASE + MCU_CDDSR:
293  n = "MCU_CDDSR (Clock Pull-down Drive Strength)";
294  break;
295  case VERDE_MCU_BASE + MCU_CEUDSR:
296  n = "MCU_CEUDSR (Clock En Pull-up Drive Strength)";
297  break;
298  case VERDE_MCU_BASE + MCU_CEDDSR:
299  n = "MCU_CEDDSR (Clock En Pull-down Drive Strength)";
300  break;
301  case VERDE_MCU_BASE + MCU_CSUDSR:
302  n = "MCU_CSUDSR (Chip Sel Pull-up Drive Strength)";
303  break;
304  case VERDE_MCU_BASE + MCU_CSDDSR:
305  n = "MCU_CSDDSR (Chip Sel Pull-down Drive Strength)";
306  break;
307  case VERDE_MCU_BASE + MCU_REUDSR:
308  n = "MCU_REUDSR (Rx En Pull-up Drive Strength)";
309  break;
310  case VERDE_MCU_BASE + MCU_REDDSR:
311  n = "MCU_REDDSR (Rx En Pull-down Drive Strength)";
312  break;
313 
314  case VERDE_MCU_BASE + MCU_ABUDSR:
315  n = "MCU_ABUDSR (Addr Bus Pull-up Drive Strength)";
316  break;
317  case VERDE_MCU_BASE + MCU_ABDDSR:
318  n = "MCU_ABDDSR (Addr Bus Pull-down Drive Strength)";
319  break;
320 
321  /* Peripheral Bus Interface Unit */
322  case VERDE_PBIU_BASE + PBIU_PBCR:
323  n = "PBIU_PBCR (PBIU Control Register)";
324  break;
326  n = "PBIU_PBBAR0 (PBIU Base Address Register 0)";
327  break;
329  n = "PBIU_PBLR0 (PBIU Limit Register 0)";
330  break;
332  n = "PBIU_PBBAR1 (PBIU Base Address Register 1)";
333  break;
335  n = "PBIU_PBLR1 (PBIU Limit Register 1)";
336  break;
338  n = "PBIU_PBBAR2 (PBIU Base Address Register 2)";
339  break;
341  n = "PBIU_PBLR2 (PBIU Limit Register 2)";
342  break;
343 
344  /* TODO: */
345  case 0x7cc:
346  n = "0x7cc_TODO";
347  break;
348 
349  case VERDE_I2C_BASE0 + IIC_ICR:
350  n = "I2C 0, IIC_ICR (control register)";
351  break;
352  case VERDE_I2C_BASE0 + IIC_ISR:
353  n = "I2C 0, IIC_ISR (status register)";
354  break;
355  case VERDE_I2C_BASE0 + IIC_ISAR:
356  n = "I2C 0, IIC_ISAR (slave address register)";
357  break;
358  case VERDE_I2C_BASE0 + IIC_IDBR:
359  n = "I2C 0, IIC_IDBR (data buffer register)";
360  break;
361 
362  case VERDE_I2C_BASE1 + IIC_ICR:
363  n = "I2C 1, IIC_ICR (control register)";
364  break;
365  case VERDE_I2C_BASE1 + IIC_ISR:
366  n = "I2C 1, IIC_ISR (status register)";
367  odata = IIC_ISR_ITE; /* IDBR Tx empty */
368  odata |= IIC_ISR_IRF; /* IDBR Rx full */
369  break;
370  case VERDE_I2C_BASE1 + IIC_ISAR:
371  n = "I2C 1, IIC_ISAR (slave address register)";
372  break;
373  case VERDE_I2C_BASE1 + IIC_IDBR:
374  n = "I2C 1, IIC_IDBR (data buffer register)";
375  odata = 7; /* TODO */
376  break;
377 
378  default:if (writeflag == MEM_READ) {
379  fatal("[ i80321: read from 0x%x ]\n",
380  (int)relative_addr);
381  } else {
382  fatal("[ i80321: write to 0x%x: 0x%llx ]\n",
383  (int)relative_addr, (long long)idata);
384  }
385  exit(1);
386  }
387 
388  if (n != NULL) {
389  if (writeflag == MEM_READ) {
390  debug("[ i80321: read from %s: 0x%llx ]\n",
391  n, (long long)idata);
392  } else {
393  debug("[ i80321: write to %s: 0x%llx ]\n",
394  n, (long long)idata);
395  }
396  }
397 
398 ret:
399  if (writeflag == MEM_READ)
400  memory_writemax64(cpu, data, len, odata);
401 
402  return 1;
403 }
404 
405 
406 DEVINIT(i80321)
407 {
408  struct i80321_data *d;
409  uint32_t memsize = devinit->machine->physical_ram_in_mb * 1048576;
410  uint32_t base;
411  char tmpstr[300];
412  struct cpu *cpu = devinit->machine->cpus[devinit->
414  int i;
415 
416  CHECK_ALLOCATION(d = (struct i80321_data *) malloc(sizeof(struct i80321_data)));
417  memset(d, 0, sizeof(struct i80321_data));
418 
419  /* Connect to the CPU interrupt pin: */
421 
422  /* Register 32 i80321 interrupts: */
423  for (i=0; i<32; i++) {
424  struct interrupt templ;
425  char tmpstr2[300];
426  snprintf(tmpstr2, sizeof(tmpstr2), "%s.i80321.%i",
427  devinit->interrupt_path, i);
428  memset(&templ, 0, sizeof(templ));
429  templ.line = 1 << i;
430  templ.name = tmpstr2;
431  templ.extra = d;
435 
436  /*
437  * Connect the CPU's TMR0 and TMR1 interrupts to these
438  * i80321 timer interrupts (nr 9 and 10):
439  */
440  if (i == 9)
441  INTERRUPT_CONNECT(tmpstr2, cpu->cd.arm.tmr0_irq);
442  if (i == 10)
443  INTERRUPT_CONNECT(tmpstr2, cpu->cd.arm.tmr1_irq);
444  }
445 
446  d->status = &cpu->cd.arm.i80321_isrc;
447  d->enable = &cpu->cd.arm.i80321_inten;
448 
449  /* TODO: base = 0 on Iyonix? */
450  d->mcu_reg[MCU_SDBR / sizeof(uint32_t)] = base = 0xa0000000;
451  d->mcu_reg[MCU_SBR0 / sizeof(uint32_t)] = (base + memsize) >> 25;
452  d->mcu_reg[MCU_SBR1 / sizeof(uint32_t)] = (base + memsize) >> 25;
453 
454  snprintf(tmpstr, sizeof(tmpstr), "%s.i80321", devinit->interrupt_path);
455 
457  tmpstr /* pciirq */,
458  0x90000000 /* TODO: pci_io_offset */,
459  0x90010000 /* TODO: pci_mem_offset */,
460  0xffff0000 /* TODO: pci_portbase */,
461  0x00000000 /* TODO: pci_membase */,
462  tmpstr /* pci_irqbase */,
463  0x90000000 /* TODO: isa_portbase */,
464  0x90010000 /* TODO: isa_membase */,
465  "TODO: isa_irqbase" /* TODO: isa_irqbase */);
466 
469  dev_i80321_access, d, DM_DEFAULT, NULL);
470 
471  /* TODO: Don't hardcode to 100 Hz! */
472  d->hz = 100;
473  d->timer = timer_add(d->hz, tmr0_tick, d);
474 
475  machine_add_tickfunction(devinit->machine, dev_i80321_tick,
476  d, TICK_SHIFT);
477 
478  devinit->return_ptr = d->pci_bus;
479 
480  return 1;
481 }
482 
#define ATU_IALR2
Definition: i80321reg.h:116
uint64_t memory_readmax64(struct cpu *cpu, unsigned char *buf, int len)
Definition: memory.cc:55
#define IIC_ISAR
Definition: iopi2creg.h:43
void fatal(const char *fmt,...)
Definition: main.cc:152
uint32_t mcu_reg[0x100/sizeof(uint32_t)]
Definition: dev_i80321.cc:76
uint32_t tisr
Definition: cpu_arm.h:200
void(* interrupt_assert)(struct interrupt *)
Definition: interrupt.h:38
#define DM_DEFAULT
Definition: memory.h:130
#define PBIU_PBBAR2
Definition: i80321reg.h:431
uint32_t i80321_isrc
Definition: cpu_arm.h:191
uint32_t * status
Definition: dev_i80321.cc:63
#define VERDE_MCU_SIZE
Definition: i80321reg.h:90
#define MCU_SDCR
Definition: i80321reg.h:226
#define ATU_IATVR2
Definition: i80321reg.h:117
#define ATU_OMWTVR1
Definition: i80321reg.h:121
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Definition: i80321reg.h:237
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Definition: i80321reg.h:101
#define VERDE_I2C_BASE0
Definition: i80321reg.h:102
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Definition: i80321reg.h:427
#define IIC_ISR_IRF
Definition: iopi2creg.h:68
char * name
Definition: device.h:43
#define TMRx_ENABLE
Definition: i80321reg.h:300
union cpu::@1 cd
struct interrupt irq
Definition: dev_i80321.cc:62
struct machine * machine
Definition: cpu.h:328
void interrupt_handler_register(struct interrupt *templ)
Definition: interrupt.cc:81
#define MEM_READ
Definition: memory.h:116
#define ATU_OCCDR
Definition: i80321reg.h:133
void(* interrupt_deassert)(struct interrupt *)
Definition: interrupt.h:39
#define MCU_SBR1
Definition: i80321reg.h:229
DEVINIT(i80321)
Definition: dev_i80321.cc:406
#define ATU_OCCAR
Definition: i80321reg.h:132
struct memory * memory
Definition: machine.h:126
#define ATU_OMWTVR0
Definition: i80321reg.h:119
#define ATU_IALR3
Definition: i80321reg.h:130
#define ATU_IABAR3
Definition: i80321reg.h:128
struct pci_data * pci_bus
Definition: dev_i80321.cc:73
struct arm_cpu arm
Definition: cpu.h:441
#define MCU_ABUDSR
Definition: i80321reg.h:248
#define MCU_SBR0
Definition: i80321reg.h:228
#define reg(x)
#define PBIU_PBLR1
Definition: i80321reg.h:430
#define MCU_ABDDSR
Definition: i80321reg.h:249
void * return_ptr
Definition: device.h:56
struct interrupt tmr0_irq
Definition: cpu_arm.h:194
uint32_t tmr0
Definition: cpu_arm.h:192
#define MCU_CUDSR
Definition: i80321reg.h:240
#define TICK_SHIFT
Definition: dev_i80321.cc:57
struct cpu ** cpus
Definition: machine.h:140
Definition: timer.cc:45
int exit_without_entering_debugger
Definition: machine.h:172
int physical_ram_in_mb
Definition: machine.h:147
#define ATU_IALR1
Definition: i80321reg.h:115
int ncpus
Definition: machine.h:139
#define MCU_DBUDSR
Definition: i80321reg.h:238
double hz
Definition: dev_i80321.cc:68
#define MCU_REUDSR
Definition: i80321reg.h:246
#define CHECK_ALLOCATION(ptr)
Definition: misc.h:239
#define VERDE_ATU_BASE
Definition: i80321reg.h:77
#define ATU_IATVR0
Definition: i80321reg.h:112
#define VERDE_I2C_SIZE
Definition: i80321reg.h:104
#define ATU_PCSR
Definition: i80321reg.h:125
#define ATU_OIOWTVR
Definition: i80321reg.h:118
#define ATU_ATUCR
Definition: i80321reg.h:124
#define ATU_IALR0
Definition: i80321reg.h:111
#define VERDE_I2C_BASE1
Definition: i80321reg.h:103
#define MCU_SDIR
Definition: i80321reg.h:225
int bootstrap_cpu
Definition: machine.h:136
#define MCU_REDDSR
Definition: i80321reg.h:247
#define MCU_CDDSR
Definition: i80321reg.h:241
void bus_pci_setaddr(struct cpu *cpu, struct pci_data *pci_data, int bus, int device, int function, int reg)
Definition: bus_pci.cc:197
u_short data
Definition: siireg.h:79
uint32_t * enable
Definition: dev_i80321.cc:64
#define MCU_CEUDSR
Definition: i80321reg.h:242
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Definition: timer.cc:75
#define INTERRUPT_ASSERT(istruct)
Definition: interrupt.h:74
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Definition: cpu.h:353
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Definition: memory.h:117
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Definition: dev_i80321.cc:72
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Definition: i80321reg.h:428
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Definition: i80321reg.h:139
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Definition: cpu_arm.h:189
#define TISR_TMR0
Definition: i80321reg.h:307
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Definition: i80321reg.h:230
Definition: device.h:40
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Definition: i80321reg.h:426
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Definition: i80321reg.h:244
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Definition: i80321reg.h:120
#define VERDE_PBIU_BASE
Definition: i80321reg.h:95
#define DEV_I80321_LENGTH
Definition: dev_i80321.cc:58
#define debug
Definition: dev_adb.cc:57
#define IIC_ISR_ITE
Definition: iopi2creg.h:69
#define IIC_ICR
Definition: iopi2creg.h:41
uint32_t line
Definition: interrupt.h:51
#define INTERRUPT_CONNECT(name, istruct)
Definition: interrupt.h:77
Definition: cpu.h:326
int pending_tmr0_interrupts
Definition: dev_i80321.cc:69
#define MCU_CEDDSR
Definition: i80321reg.h:243
struct machine * machine
Definition: device.h:41
#define VERDE_MCU_BASE
Definition: i80321reg.h:89
#define ATU_OUMWTVR1
Definition: i80321reg.h:122
struct interrupt tmr1_irq
Definition: cpu_arm.h:195
char * name
Definition: interrupt.h:66
void i80321_interrupt_deassert(struct interrupt *interrupt)
Definition: dev_i80321.cc:105
void memory_writemax64(struct cpu *cpu, unsigned char *buf, int len, uint64_t data)
Definition: memory.cc:89
#define ATU_IAUBAR3
Definition: i80321reg.h:129
#define PBIU_PBBAR1
Definition: i80321reg.h:429
#define ATU_IATVR3
Definition: i80321reg.h:131
struct timer * timer
Definition: dev_i80321.cc:67
void memory_device_register(struct memory *mem, const char *, uint64_t baseaddr, uint64_t len, int(*f)(struct cpu *, struct memory *, uint64_t, unsigned char *, size_t, int, void *), void *extra, int flags, unsigned char *dyntrans_data)
Definition: memory.cc:339
#define ATU_ATUIMR
Definition: i80321reg.h:127
#define MCU_CSDDSR
Definition: i80321reg.h:245
#define IIC_ISR
Definition: iopi2creg.h:42
#define PBIU_PBLR2
Definition: i80321reg.h:432
void bus_pci_decompose_1(uint32_t t, int *bus, int *dev, int *func, int *reg)
Definition: bus_pci.cc:77
#define IIC_IDBR
Definition: iopi2creg.h:44
struct pci_data * bus_pci_init(struct machine *machine, const char *irq_path, uint64_t pci_actual_io_offset, uint64_t pci_actual_mem_offset, uint64_t pci_portbase, uint64_t pci_membase, const char *pci_irqbase, uint64_t isa_portbase, uint64_t isa_membase, const char *isa_irqbase)
Definition: bus_pci.cc:356
#define MCU_SDBR
Definition: i80321reg.h:227
addr & if(addr >=0x24 &&page !=NULL)
uint64_t addr
Definition: device.h:46
#define MCU_DBDDSR
Definition: i80321reg.h:239
uint32_t i2c_reg[VERDE_I2C_SIZE/sizeof(uint32_t)]
Definition: dev_i80321.cc:79
void machine_add_tickfunction(struct machine *machine, void(*func)(struct cpu *, void *), void *extra, int clockshift)
Definition: machine.cc:280
void * extra
Definition: interrupt.h:59
void bus_pci_data_access(struct cpu *cpu, struct pci_data *pci_data, uint64_t *data, int len, int writeflag)
Definition: bus_pci.cc:96
DEVICE_ACCESS(i80321)
Definition: dev_i80321.cc:140
void i80321_interrupt_assert(struct interrupt *interrupt)
Definition: dev_i80321.cc:103
DEVICE_TICK(i80321)
Definition: dev_i80321.cc:126
char * interrupt_path
Definition: device.h:50
#define INTERRUPT_DEASSERT(istruct)
Definition: interrupt.h:75

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