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1 /* gxemul: $Id: dec_maxine.h,v 1.3 2005-03-05 12:34:02 debug Exp $ */
2 /* $NetBSD: maxine.h,v 1.8 2000/02/29 04:41:57 nisimura Exp $ */
3 
4 /*-
5  * Copyright (c) 1992, 1993
6  * The Regents of the University of California. All rights reserved.
7  *
8  * This code is derived from software contributed to Berkeley by
9  * The Mach Operating System project at Carnegie-Mellon University,
10  * Ralph Campbell and Rick Macklem.
11  *
12  * Redistribution and use in source and binary forms, with or without
13  * modification, are permitted provided that the following conditions
14  * are met:
15  * 1. Redistributions of source code must retain the above copyright
16  * notice, this list of conditions and the following disclaimer.
17  * 2. Redistributions in binary form must reproduce the above copyright
18  * notice, this list of conditions and the following disclaimer in the
19  * documentation and/or other materials provided with the distribution.
20  * 3. All advertising materials mentioning features or use of this software
21  * must display the following acknowledgement:
22  * This product includes software developed by the University of
23  * California, Berkeley and its contributors.
24  * 4. Neither the name of the University nor the names of its contributors
25  * may be used to endorse or promote products derived from this software
26  * without specific prior written permission.
27  *
28  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
29  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
31  * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
32  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
36  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
37  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
38  * SUCH DAMAGE.
39  *
40  * @(#)maxine.h 8.1 (Berkeley) 6/10/93
41  */
42 
43 /*
44  * Mach Operating System
45  * Copyright (c) 1991,1990,1989 Carnegie Mellon University
46  * All Rights Reserved.
47  *
48  * Permission to use, copy, modify and distribute this software and
49  * its documentation is hereby granted, provided that both the copyright
50  * notice and this permission notice appear in all copies of the
51  * software, derivative works or modified versions, and any portions
52  * thereof, and that both notices appear in supporting documentation.
53  *
54  * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
55  * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
56  * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
57  *
58  * Carnegie Mellon requests users of this software to return to
59  *
60  * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
61  * School of Computer Science
62  * Carnegie Mellon University
63  * Pittsburgh PA 15213-3890
64  *
65  * any improvements or extensions that they make and grant Carnegie the
66  * rights to redistribute these changes.
67  */
68 /*
69  * HISTORY
70  * Log: maxine.h,v
71  * Revision 2.3 92/04/01 15:14:52 rpd
72  * Defined pseudo slot for mappable timer.
73  * [92/03/11 02:37:41 af]
74  *
75  * Revision 2.2 92/03/02 18:34:28 rpd
76  * Created, from the DEC specs:
77  * "MAXine System Module Functional Specification" Revision 1.2
78  * Workstation Systems Engineering, Palo Alto, CA. July 15, 1991.
79  * [92/01/17 af]
80  *
81  */
82 /*
83  * File: maxine.h
84  * Author: Alessandro Forin, Carnegie Mellon University
85  * Date: 1/92
86  *
87  * Definitions specific to the MAXine system module (54-21325-01)
88  * and compatible processors (KN02BA).
89  */
90 
91 #ifndef MIPS_XINE_H
92 #define MIPS_XINE_H 1
93 
94 /*
95  * MAXine's Physical address space
96  */
97 #define XINE_PHYS_MIN 0x00000000 /* 512 Meg */
98 #define XINE_PHYS_MAX 0x1fffffff
99 
100 /*
101  * Memory map
102  */
103 #define XINE_PHYS_MEMORY_START 0x00000000
104 #define XINE_PHYS_MEMORY_END 0x027fffff /* 40 Meg in 2 slots
105  and baseboard */
106 
107 /*
108  * I/O map
109  */
110 #define XINE_PHYS_CFB_START 0x08000000 /* Color Frame Buffer */
111 #define XINE_PHYS_CFB_END 0x0bffffff /* 64 Meg */
112 
113 #define XINE_PHYS_MREGS_START 0x0c000000 /* Memory control registers */
114 #define XINE_PHYS_MREGS_END 0x0dffffff /* 32 Meg */
115 #define XINE_PHYS_CREGS_START 0x0e000000 /* CPU ASIC control regs */
116 #define XINE_PHYS_CREGS_END 0x0fffffff /* 32 Meg */
117 
118 #define XINE_PHYS_TC_0_START 0x10000000 /* TURBOchannel, slot 0 */
119 #define XINE_PHYS_TC_0_END 0x13ffffff /* 64 Meg, option0 */
120 
121 #define XINE_PHYS_TC_1_START 0x14000000 /* TURBOchannel, slot 1 */
122 #define XINE_PHYS_TC_1_END 0x17ffffff /* 64 Meg, option1 */
123 
124 #define XINE_PHYS_TC_RESERVED 0x18000000 /* Unused slot 2 */
125  /* 64 Meg */
126 
127 #define XINE_PHYS_TC_3_START 0x1c000000 /* TURBOchannel, slot 3 */
128 #define XINE_PHYS_TC_3_END 0x1fffffff /* 64 Meg, system devices */
129 
130 #define XINE_PHYS_TC_START XINE_PHYS_TC_0_START
131 #define XINE_PHYS_TC_END XINE_PHYS_TC_3_END /* 256 Meg */
132 
133 #define XINE_TC_NSLOTS 4
134 #define XINE_TC_MIN 0
135 #define XINE_TC_MAX 1 /* only option slots */
136 
137 /*
138  * System module space
139  */
140 #define XINE_SYS_ASIC (XINE_PHYS_TC_3_START + 0x0000000)
141 #define XINE_SYS_ROM_START (XINE_SYS_ASIC + IOASIC_SLOT_0_START)
142 #define XINE_SYS_ASIC_REGS (XINE_SYS_ASIC + IOASIC_SLOT_1_START)
143 #define XINE_SYS_ETHER_ADDRESS (XINE_SYS_ASIC + IOASIC_SLOT_2_START)
144 #define XINE_SYS_LANCE (XINE_SYS_ASIC + IOASIC_SLOT_3_START)
145 #define XINE_SYS_SCC_0 (XINE_SYS_ASIC + IOASIC_SLOT_4_START)
146 #define XINE_SYS_VDAC_HI (XINE_SYS_ASIC + IOASIC_SLOT_5_START)
147 #define XINE_SYS_VDAC_LO (XINE_SYS_ASIC + IOASIC_SLOT_7_START)
148 #define XINE_SYS_CLOCK (XINE_SYS_ASIC + IOASIC_SLOT_8_START)
149 #define XINE_SYS_ISDN (XINE_SYS_ASIC + IOASIC_SLOT_9_START)
150 #define XINE_SYS_DTOP (XINE_SYS_ASIC + IOASIC_SLOT_10_START)
151 #define XINE_SYS_FLOPPY (XINE_SYS_ASIC + IOASIC_SLOT_11_START)
152 #define XINE_SYS_SCSI (XINE_SYS_ASIC + IOASIC_SLOT_12_START)
153 #define XINE_SYS_FLOPPY_DMA (XINE_SYS_ASIC + IOASIC_SLOT_13_START)
154 #define XINE_SYS_SCSI_DMA (XINE_SYS_ASIC + IOASIC_SLOT_14_START)
155 #define XINE_SYS_BOOT_ROM_START (XINE_PHYS_TC_3_START + 0x3c00000)
156 #define XINE_SYS_BOOT_ROM_END (XINE_PHYS_TC_3_START + 0x3c40000)
157 
158 /*
159  * Interrupts
160  */
161 #define XINE_INT_FPA IP_LEV7 /* Floating Point coproc */
162 #define XINE_INT_HALTB IP_LEV6 /* Halt keycode (DTOP) */
163 #define XINE_INT_TC3 IP_LEV5 /* TC slot 3, system */
164 #define XINE_INT_TIMEOUT IP_LEV4 /* Timeout on I/O write */
165 #define XINE_INT_TOY IP_LEV3 /* Clock chip */
166 #define XINE_INT_1_10_MS IP_LEV2 /* Periodic interrupt */
167 
168 /*
169  * System registers addresses (MREG and CREG space, and IO Control ASIC)
170  */
171 #define XINE_REG_CMR 0x0c000000 /* Color mask register */
172 #define XINE_REG_MER 0x0c400000 /* Memory error register */
173 #define XINE_REG_MSR 0x0c800000 /* Memory size register */
174 #define XINE_REG_FCTR 0x0ca00000 /* 1us free running counter */
175 #define XINE_REG_FI 0x0cc00000 /* FI signal polarity (1!) */
176 
177 #define XINE_REG_CNFG 0x0e000000 /* Config mem timeouts */
178 #define XINE_REG_AER 0x0e000004 /* Address error register */
179 #define XINE_REG_TIMEOUT 0x0e00000c /* I/O write timeout reg */
180 
181 #define XINE_REG_SCSI_DMAPTR ( XINE_SYS_ASIC + IOASIC_SCSI_DMAPTR )
182 #define XINE_REG_SCSI_DMANPTR ( XINE_SYS_ASIC + IOASIC_SCSI_NEXTPTR )
183 #define XINE_REG_LANCE_DMAPTR ( XINE_SYS_ASIC + IOASIC_LANCE_DMAPTR )
184 #define XINE_REG_SCC_T1_DMAPTR ( XINE_SYS_ASIC + IOASIC_SCC_T1_DMAPTR )
185 #define XINE_REG_SCC_R1_DMAPTR ( XINE_SYS_ASIC + IOASIC_SCC_R1_DMAPTR )
186 #define XINE_REG_DTOP_T_DMAPTR ( XINE_SYS_ASIC + IOASIC_SCC_T2_DMAPTR )
187 #define XINE_REG_DTOP_R_DMAPTR ( XINE_SYS_ASIC + IOASIC_SCC_R2_DMAPTR )
188 #define XINE_FLOPPY_DMAPTR ( XINE_SYS_ASIC + IOASIC_FLOPPY_DMAPTR )
189 #define XINE_ISDN_X_DMAPTR ( XINE_SYS_ASIC + IOASIC_ISDN_X_DMAPTR )
190 #define XINE_ISDN_X_NEXTPTR ( XINE_SYS_ASIC + IOASIC_ISDN_X_NEXTPTR )
191 #define XINE_ISDN_R_DMAPTR ( XINE_SYS_ASIC + IOASIC_ISDN_R_DMAPTR )
192 #define XINE_ISDN_R_NEXTPTR ( XINE_SYS_ASIC + IOASIC_ISDN_R_NEXTPTR )
193 #define XINE_REG_CSR ( XINE_SYS_ASIC + IOASIC_CSR )
194 #define XINE_REG_INTR ( XINE_SYS_ASIC + IOASIC_INTR )
195 #define XINE_REG_IMSK ( XINE_SYS_ASIC + IOASIC_IMSK )
196 #define XINE_REG_CURADDR ( XINE_SYS_ASIC + IOASIC_CURADDR )
197 #define XINE_ISDN_X_DATA ( XINE_SYS_ASIC + IOASIC_ISDN_X_DATA )
198 #define XINE_ISDN_R_DATA ( XINE_SYS_ASIC + IOASIC_ISDN_R_DATA )
199 
200 #define XINE_REG_LANCE_DECODE ( XINE_SYS_ASIC + IOASIC_LANCE_DECODE )
201 #define XINE_REG_SCSI_DECODE ( XINE_SYS_ASIC + IOASIC_SCSI_DECODE )
202 #define XINE_REG_SCC0_DECODE ( XINE_SYS_ASIC + IOASIC_SCC0_DECODE )
203 #define XINE_REG_DTOP_DECODE ( XINE_SYS_ASIC + IOASIC_SCC1_DECODE )
204 #define XINE_REG_FLOPPY_DECODE ( XINE_SYS_ASIC + IOASIC_FLOPPY_DECODE )
205 # define XINE_LANCE_CONFIG 3
206 # define XINE_SCSI_CONFIG 14
207 # define XINE_SCC0_CONFIG (0x10|4)
208 # define XINE_DTOP_CONFIG 10
209 # define XINE_FLOPPY_CONFIG 13
210 
211 #define XINE_REG_SCSI_SCR ( XINE_SYS_ASIC + IOASIC_SCSI_SCR )
212 #define XINE_REG_SCSI_SDR0 ( XINE_SYS_ASIC + IOASIC_SCSI_SDR0 )
213 #define XINE_REG_SCSI_SDR1 ( XINE_SYS_ASIC + IOASIC_SCSI_SDR1 )
214 
215 /*
216  * System registers defines (MREG and CREG)
217  */
218 /* Memory error register */
219 #define XINE_MER_xxx 0xf7fe30ff /* undefined */
220 #define XINE_MER_10_1_MS_IP 0x08000000 /* rw: Periodic interrupt */
221 #define XINE_MER_PAGE_BRY 0x00010000 /* rw: Page boundary error */
222 #define XINE_MER_TLEN 0x00008000 /* rw: Xfer length error */
223 #define XINE_MER_PARDIS 0x00004000 /* rw: Dis parity err intr */
224 #define XINE_MER_LASTBYTE 0x00000f00 /* rz: Last byte in error: */
225 # define XINE_LASTB31 0x00000800 /* upper byte of word */
226 # define XINE_LASTB23 0x00000400 /* .. through .. */
227 # define XINE_LASTB15 0x00000200 /* .. the .. */
228 # define XINE_LASTB07 0x00000100 /* .. lower byte */
229 
230 /* Memory size register */
231 #define XINE_MSR_xxx 0xffffdfff /* undefined */
232 #define XINE_MSR_10_1_MS_EN 0x04000000 /* rw: enable periodic intr */
233 #define XINE_MSR_10_1_MS 0x02000000 /* rw: intr. freq. (0->1ms) */
234 #define XINE_MSR_PFORCE 0x01e00000 /* rw: force parity errors */
235 #define XINE_MSR_MABEN 0x00100000 /* rw: VRAM ignores SIZE */
236 #define XINE_MSR_LAST_BANK 0x000e0000 /* rw: map baseboard mem */
237 # define XINE_BANK_0 0x00020000 /* .. at bank 0, .. */
238 # define XINE_BANK_1 0x00040000 /* .. at bank 1, .. */
239 # define XINE_BANK_2 0x00080000 /* .. or at bank 2 */
240 #define XINE_MSR_SIZE_16Mb 0x00002000 /* rw: using 16Mb mem banks */
241 
242 /* FI register */
243 #define XINE_FI_VALUE 0x00001000
244 
245 /* NOTES
246 
247  Memory access priority is, from higher to lower:
248  - VRAM/DRAM refresh
249  - IO DMA (IO Control ASIC)
250  - Slot 0 DMA
251  - Processor
252  - Slot 1 DMA
253 
254  Memory performance is (with 80ns mem cycles)
255  - single word read 5 cyc 10.0 Mb/s
256  - word write 3 cyc 16.7 Mb/s
257  - single byte write 3 cyc 4.2 Mb/s
258  - 64w DMA read 68 cyc 47.1 Mb/s
259  - 64w DMA write 66 cyc 48.5 Mb/s
260  - Refresh 5 cyc N/A
261  */
262 
263 /* Timeout config register */
264 #define XINE_CNFG_VALUE 121
265 
266 /* Address error register */
267 #define XINE_AER_ADDR_MASK 0x1ffffffc /* ro: phys addr in error */
268 
269 /* Memory access timeout interrupt register */
270 #define XINE_TIMEO_INTR 0x00000001 /* rc: intr pending */
271 
272 /*
273  * More system registers defines (IO Control ASIC)
274  */
275 /* (re)defines for the system Status and Control register (SSR) */
276 /* high-order 16 bits 0xFFFF0000 same on all DECstation IOASICs */
277 #define XINE_CSR_DIAGDN 0x00008000 /* rw */
278 #define XINE_CSR_ISDN_ENABLE 0x00001000 /* rw */
279 #define XINE_CSR_SCC_ENABLE 0x00000800 /* rw */
280 #define XINE_CSR_RTC_ENABLE 0x00000400 /* rw */
281 #define XINE_CSR_SCSI_ENABLE 0x00000200 /* rw */
282 #define XINE_CSR_LANCE_ENABLE 0x00000100 /* rw */
283 #define XINE_CSR_FLOPPY_ENABLE 0x00000080 /* rw */
284 #define XINE_CSR_VDAC_ENABLE 0x00000040 /* rw */
285 #define XINE_CSR_DTOP_ENABLE 0x00000020 /* rw */
286 #define XINE_CSR_LED 0x00000001 /* rw */
287 
288 /* (re)defines for the System Interrupt and Mask Registers */
289 /* high-order 16 bits 0xFFFF0000 same on all DECstation IOASICs */
290 #define XINE_INTR_xxxx 0x00002808 /* ro */
291 #define XINE_INTR_FLOPPY 0x00008000 /* ro */
292 #define XINE_INTR_NVR_JUMPER 0x00004000 /* ro */
293 #define XINE_INTR_POWERUP 0x00002000 /* ro */
294 #define XINE_INTR_TC_0 0x00001000 /* ro */
295 #define XINE_INTR_ISDN 0x00000800 /* ro */
296 #define XINE_INTR_NRMOD_JUMPER 0x00000400 /* ro */
297 #define XINE_INTR_SCSI 0x00000200 /* ro */
298 #define XINE_INTR_LANCE 0x00000100 /* ro */
299 #define XINE_INTR_FLOPPY_HDS 0x00000080 /* ro */
300 #define XINE_INTR_SCC_0 0x00000040 /* ro */
301 #define XINE_INTR_TC_1 0x00000020 /* ro */
302 #define XINE_INTR_FLOPPY_XDS 0x00000010 /* ro */
303 #define XINE_INTR_VINT 0x00000008 /* ro */
304 #define XINE_INTR_N_VINT 0x00000004 /* ro */
305 #define XINE_INTR_DTOP_TX 0x00000002 /* ro */
306 #define XINE_INTR_DTOP_RX 0x00000001 /* ro */
307 #define XINE_INTR_ASIC 0xffff0000
308 #define XINE_INTR_DTOP 0x00000003
309 #define XINE_IM0 0xffff9b6b /* all good ones enabled */
310 
311 #endif /* MIPS_XINE_H */

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