59 #define ARM_REG_NAMES { \ 60 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \ 61 "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" } 63 #define ARM_CONDITION_STRINGS { \ 64 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", \ 65 "hi", "ls", "ge", "lt", "gt", "le", "" , "(INVALID)" } 68 #define ARM_DPI_NAMES { \ 69 "and", "eor", "sub", "rsb", "add", "adc", "sbc", "rsc", \ 70 "tst", "teq", "cmp", "cmn", "orr", "mov", "bic", "mvn" } 72 #define ARM_IC_ENTRIES_SHIFT 10 74 #define ARM_N_IC_ARGS 3 75 #define ARM_INSTR_ALIGNMENT_SHIFT 2 76 #define ARM_IC_ENTRIES_PER_PAGE (1 << ARM_IC_ENTRIES_SHIFT) 77 #define ARM_PC_TO_IC_ENTRY(a) (((a)>>ARM_INSTR_ALIGNMENT_SHIFT) \ 78 & (ARM_IC_ENTRIES_PER_PAGE-1)) 79 #define ARM_ADDR_TO_PAGENR(a) ((a) >> (ARM_IC_ENTRIES_SHIFT \ 80 + ARM_INSTR_ALIGNMENT_SHIFT)) 87 #define ARM_FLAG_N 0x80000000 88 #define ARM_FLAG_Z 0x40000000 89 #define ARM_FLAG_C 0x20000000 90 #define ARM_FLAG_V 0x10000000 91 #define ARM_FLAG_Q 0x08000000 92 #define ARM_FLAG_I 0x00000080 93 #define ARM_FLAG_F 0x00000040 94 #define ARM_FLAG_T 0x00000020 96 #define ARM_FLAG_MODE 0x0000001f 97 #define ARM_MODE_USR26 0x00 98 #define ARM_MODE_FIQ26 0x01 99 #define ARM_MODE_IRQ26 0x02 100 #define ARM_MODE_SVC26 0x03 101 #define ARM_MODE_USR32 0x10 102 #define ARM_MODE_FIQ32 0x11 103 #define ARM_MODE_IRQ32 0x12 104 #define ARM_MODE_SVC32 0x13 105 #define ARM_MODE_ABT32 0x17 106 #define ARM_MODE_UND32 0x1b 107 #define ARM_MODE_SYS32 0x1f 109 #define ARM_EXCEPTION_TO_MODE { \ 110 ARM_MODE_SVC32, ARM_MODE_UND32, ARM_MODE_SVC32, ARM_MODE_ABT32, \ 111 ARM_MODE_ABT32, 0, ARM_MODE_IRQ32, ARM_MODE_FIQ32 } 113 #define N_ARM_EXCEPTIONS 8 115 #define ARM_EXCEPTION_RESET 0 116 #define ARM_EXCEPTION_UND 1 117 #define ARM_EXCEPTION_SWI 2 118 #define ARM_EXCEPTION_PREF_ABT 3 119 #define ARM_EXCEPTION_DATA_ABT 4 121 #define ARM_EXCEPTION_IRQ 6 122 #define ARM_EXCEPTION_FIQ 7 126 #define ARM_MAX_VPH_TLB_ENTRIES 384 136 void (*coproc[16])(
struct cpu *,
int opcode1,
137 int opcode2,
int l_bit,
int crn,
int crm,
150 uint32_t default_r8_r14[7];
151 uint32_t fiq_r8_r14[7];
152 uint32_t irq_r13_r14[2];
153 uint32_t svc_r13_r14[2];
154 uint32_t abt_r13_r14[2];
155 uint32_t und_r13_r14[2];
244 #define ARM_CONTROL_MMU 0x0001 245 #define ARM_CONTROL_ALIGN 0x0002 246 #define ARM_CONTROL_CACHE 0x0004 247 #define ARM_CONTROL_WBUFFER 0x0008 248 #define ARM_CONTROL_PROG32 0x0010 249 #define ARM_CONTROL_DATA32 0x0020 250 #define ARM_CONTROL_BIG 0x0080 251 #define ARM_CONTROL_S 0x0100 252 #define ARM_CONTROL_R 0x0200 253 #define ARM_CONTROL_F 0x0400 254 #define ARM_CONTROL_Z 0x0800 255 #define ARM_CONTROL_ICACHE 0x1000 256 #define ARM_CONTROL_V 0x2000 257 #define ARM_CONTROL_RR 0x4000 258 #define ARM_CONTROL_L4 0x8000 261 #define ARM_AUXCTRL_MD 0x30 262 #define ARM_AUXCTRL_MD_SHIFT 4 263 #define ARM_AUXCTRL_P 0x02 264 #define ARM_AUXCTRL_K 0x01 267 #define ARM_CACHETYPE_CLASS 0x1e000000 268 #define ARM_CACHETYPE_CLASS_SHIFT 25 269 #define ARM_CACHETYPE_HARVARD 0x01000000 270 #define ARM_CACHETYPE_HARVARD_SHIFT 24 271 #define ARM_CACHETYPE_DSIZE 0x001c0000 272 #define ARM_CACHETYPE_DSIZE_SHIFT 18 273 #define ARM_CACHETYPE_DASSOC 0x00038000 274 #define ARM_CACHETYPE_DASSOC_SHIFT 15 275 #define ARM_CACHETYPE_DLINE 0x00003000 276 #define ARM_CACHETYPE_DLINE_SHIFT 12 277 #define ARM_CACHETYPE_ISIZE 0x000001c0 278 #define ARM_CACHETYPE_ISIZE_SHIFT 6 279 #define ARM_CACHETYPE_IASSOC 0x00000038 280 #define ARM_CACHETYPE_IASSOC_SHIFT 3 281 #define ARM_CACHETYPE_ILINE 0x00000003 282 #define ARM_CACHETYPE_ILINE_SHIFT 0 293 unsigned char *host_page,
int writeflag, uint64_t paddr_page);
299 unsigned char *
data,
size_t len,
int writeflag,
int cache_flags);
304 int crn,
int crm,
int rd);
306 int crn,
int crm,
int rd);
308 int crn,
int crm,
int rd);
312 uint64_t *return_addr,
int flags);
314 uint64_t *return_addr,
int flags);
#define DYNTRANS_MISC_DECLARATIONS(arch, ARCH, addrtype)
int arm_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr, unsigned char *data, size_t len, int writeflag, int cache_flags)
void arm_invalidate_code_translation(struct cpu *cpu, uint64_t, int)
void arm_load_register_bank(struct cpu *cpu)
void arm_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, unsigned char *host_page, int writeflag, uint64_t paddr_page)
void arm_coproc_i80321_6(struct cpu *cpu, int opcode1, int opcode2, int l_bit, int crn, int crm, int rd)
void arm_setup_initial_translation_table(struct cpu *cpu, uint32_t ttb_addr)
int arm_run_instr(struct cpu *cpu)
#define DYNTRANS_ITC(arch)
void arm_coproc_xscale_14(struct cpu *cpu, int opcode1, int opcode2, int l_bit, int crn, int crm, int rd)
int arm_cpu_family_init(struct cpu_family *)
#define VPH32_16BITVPHENTRIES(arch, ARCH)
int arm_translate_v2p_mmu(struct cpu *cpu, uint64_t vaddr, uint64_t *return_addr, int flags)
void arm_translation_table_set_l1(struct cpu *cpu, uint32_t vaddr, uint32_t paddr)
void arm_save_register_bank(struct cpu *cpu)
#define VPH_TLBS(arch, ARCH)
void arm_exception(struct cpu *, int)
void arm_translation_table_set_l1_b(struct cpu *cpu, uint32_t vaddr, uint32_t paddr)
void arm_coproc_15(struct cpu *cpu, int opcode1, int opcode2, int l_bit, int crn, int crm, int rd)
void arm_invalidate_translation_caches(struct cpu *cpu, uint64_t, int)
unsigned char * translation_table
int arm_translate_v2p(struct cpu *cpu, uint64_t vaddr, uint64_t *return_addr, int flags)