68 #define INITIAL_PC 0xffffffffbfc00000ULL 69 #define INITIAL_STACK_POINTER (0xffffffffa0008000ULL - 256) 78 #define N_MIPS_COPROC_REGS 32 91 #define N_MIPS_FCRS 32 92 #define MIPS_FPU_FCIR 0 93 #define MIPS_FPU_FCCR 25 94 #define MIPS_FPU_FCSR 31 95 #define MIPS_FCSR_FCC0_SHIFT 23 96 #define MIPS_FCSR_FCC1_SHIFT 25 98 #define N_VADDR_TO_TLB_INDEX_ENTRIES (1 << 20) 113 #define N_MIPS_COPROCS 4 115 #define N_MIPS_GPRS 32 116 #define N_MIPS_FPRS 32 128 #define MIPS_REGISTER_NAMES { \ 129 "zr", "at", "v0", "v1", "a0", "a1", "a2", "a3", \ 130 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", \ 131 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \ 132 "t8", "t9", "k0", "k1", "gp", "sp", "fp", "ra" } 134 #define MIPS_GPR_ZERO 0 135 #define MIPS_GPR_AT 1 136 #define MIPS_GPR_V0 2 137 #define MIPS_GPR_V1 3 138 #define MIPS_GPR_A0 4 139 #define MIPS_GPR_A1 5 140 #define MIPS_GPR_A2 6 141 #define MIPS_GPR_A3 7 142 #define MIPS_GPR_T0 8 143 #define MIPS_GPR_T1 9 144 #define MIPS_GPR_T2 10 145 #define MIPS_GPR_T3 11 146 #define MIPS_GPR_T4 12 147 #define MIPS_GPR_T5 13 148 #define MIPS_GPR_T6 14 149 #define MIPS_GPR_T7 15 150 #define MIPS_GPR_S0 16 151 #define MIPS_GPR_S1 17 152 #define MIPS_GPR_S2 18 153 #define MIPS_GPR_S3 19 154 #define MIPS_GPR_S4 20 155 #define MIPS_GPR_S5 21 156 #define MIPS_GPR_S6 22 157 #define MIPS_GPR_S7 23 158 #define MIPS_GPR_T8 24 159 #define MIPS_GPR_T9 25 160 #define MIPS_GPR_K0 26 161 #define MIPS_GPR_K1 27 162 #define MIPS_GPR_GP 28 163 #define MIPS_GPR_SP 29 164 #define MIPS_GPR_FP 30 165 #define MIPS_GPR_RA 31 173 #define IMPOSSIBLE_PADDR 0x1212343456566767ULL 175 #define DEFAULT_PCACHE_SIZE 15 176 #define DEFAULT_PCACHE_LINESIZE 5 182 #define R3000_TAG_VALID 1 183 #define R3000_TAG_DIRTY 2 186 #define MIPS_IC_ENTRIES_SHIFT 10 188 #define MIPS_N_IC_ARGS 3 189 #define MIPS_INSTR_ALIGNMENT_SHIFT 2 190 #define MIPS_IC_ENTRIES_PER_PAGE (1 << MIPS_IC_ENTRIES_SHIFT) 191 #define MIPS_PC_TO_IC_ENTRY(a) (((a)>>MIPS_INSTR_ALIGNMENT_SHIFT) \ 192 & (MIPS_IC_ENTRIES_PER_PAGE-1)) 193 #define MIPS_ADDR_TO_PAGENR(a) ((a) >> (MIPS_IC_ENTRIES_SHIFT \ 194 + MIPS_INSTR_ALIGNMENT_SHIFT)) 199 #define MIPS_MAX_VPH_TLB_ENTRIES 192 266 unsigned char *cache[2];
268 uint64_t cache_last_paddr[2];
270 int cache_linesize[2];
291 int writeflag, uint64_t *valuep,
int *match_register);
294 int running, uint64_t
addr);
296 int coproc_nr, uint64_t vaddr_vpn2,
297 int vaddr_asid,
int x_64);
307 uint64_t vaddr, uint64_t paddr0, uint64_t paddr1,
308 int valid0,
int valid1,
int dirty0,
int dirty1,
int global,
int asid,
309 int cachealgo0,
int cachealgo1);
311 struct mips_coproc *cp,
int reg_nr, uint64_t *ptr,
int select);
313 struct mips_coproc *cp,
int reg_nr, uint64_t *ptr,
int flag64,
320 uint32_t
function,
int unassemble_only,
int running);
325 int writeflag,
size_t len,
unsigned char *
data);
327 unsigned char *
data,
size_t len,
int writeflag,
int cache_flags);
330 uint64_t *return_addr,
int flags);
332 uint64_t *return_addr,
int flags);
334 uint64_t *return_addr,
int flags);
336 uint64_t *return_addr,
int flags);
338 uint64_t *return_addr,
int flags);
343 int is_left,
int wlen,
int store);
348 unsigned char *host_page,
int writeflag, uint64_t paddr_page);
353 unsigned char *host_page,
int writeflag, uint64_t paddr_page);
#define DYNTRANS_MISC_DECLARATIONS(arch, ARCH, addrtype)
int cache_secondary_linesize
void coproc_rfe(struct cpu *cpu)
void coproc_register_read(struct cpu *cpu, struct mips_coproc *cp, int reg_nr, uint64_t *ptr, int select)
struct arm_instr_call * ic
int translate_v2p_mmu4100(struct cpu *cpu, uint64_t vaddr, uint64_t *return_addr, int flags)
void coproc_tlbpr(struct cpu *cpu, int readflag)
int mips_cpu_run(struct emul *emul, struct machine *machine)
void mips_unaligned_loadstore(struct cpu *cpu, struct mips_instr_call *ic, int is_left, int wlen, int store)
int mips32_run_instr(struct cpu *cpu)
int cache_pdcache_linesize
void mips32_invalidate_translation_caches(struct cpu *cpu, uint64_t, int)
void mips_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, unsigned char *host_page, int writeflag, uint64_t paddr_page)
int32_t count_register_read_count
int mips_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr, unsigned char *data, size_t len, int writeflag, int cache_flags)
int cache_picache_linesize
int mips_cpu_disassemble_instr(struct cpu *cpu, unsigned char *instr, int running, uint64_t addr)
#define DYNTRANS_ITC(arch)
void coproc_eret(struct cpu *cpu)
struct mips_coproc * mips_coproc_new(struct cpu *cpu, int coproc_nr)
int compare_interrupts_pending
void mips_cpu_interrupt_assert(struct interrupt *interrupt)
void coproc_function(struct cpu *cpu, struct mips_coproc *cp, int cpnr, uint32_t function, int unassemble_only, int running)
void mips_cpu_exception(struct cpu *cpu, int exccode, int tlb, uint64_t vaddr, int coproc_nr, uint64_t vaddr_vpn2, int vaddr_asid, int x_64)
int translate_v2p_mmu3k(struct cpu *cpu, uint64_t vaddr, uint64_t *return_addr, int flags)
#define N_MIPS_COPROC_REGS
void mips_invalidate_code_translation(struct cpu *cpu, uint64_t, int)
int mips_run_instr(struct cpu *cpu)
int translate_v2p_mmu8k(struct cpu *cpu, uint64_t vaddr, uint64_t *return_addr, int flags)
int mips_cpu_instruction_has_delayslot(struct cpu *cpu, unsigned char *ib)
void mips32_invalidate_code_translation(struct cpu *cpu, uint64_t, int)
int memory_cache_R3000(struct cpu *cpu, int cache, uint64_t paddr, int writeflag, size_t len, unsigned char *data)
void mips_cpu_register_match(struct machine *m, char *name, int writeflag, uint64_t *valuep, int *match_register)
uint64_t cop0_config_select1
void mips_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs)
int translate_v2p_mmu10k(struct cpu *cpu, uint64_t vaddr, uint64_t *return_addr, int flags)
void coproc_tlbwri(struct cpu *cpu, int randomflag)
void mips_cpu_tlbdump(struct machine *m, int x, int rawflag)
void mips_invalidate_translation_caches(struct cpu *cpu, uint64_t, int)
#define VPH_TLBS(arch, ARCH)
void mips32_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, unsigned char *host_page, int writeflag, uint64_t paddr_page)
int mips_cpu_family_init(struct cpu_family *)
void mips_coproc_tlb_set_entry(struct cpu *cpu, int entrynr, int size, uint64_t vaddr, uint64_t paddr0, uint64_t paddr1, int valid0, int valid1, int dirty0, int dirty1, int global, int asid, int cachealgo0, int cachealgo1)
void mips_cpu_dumpinfo(struct cpu *cpu)
#define VPH64(arch, ARCH)
void coproc_register_write(struct cpu *cpu, struct mips_coproc *cp, int reg_nr, uint64_t *ptr, int flag64, int select)
void mips_cpu_interrupt_deassert(struct interrupt *interrupt)
#define DYNTRANS_MISC64_DECLARATIONS(arch, ARCH, tlbindextype)
#define VPH32(arch, ARCH)
void mips_cpu_list_available_types(void)
int translate_v2p_generic(struct cpu *cpu, uint64_t vaddr, uint64_t *return_addr, int flags)
int last_written_tlb_index