63 int IB, DB, SB,
IC, DC, SC, IA, DA;
86 IB = IB < 0? 0 : (IB > 7? 7 : IB);
88 DB = DB < 0? 0 : (DB > 7? 7 : DB);
121 IB = IB < 0? 0 : (IB > 1? 1 : IB);
123 DB = DB < 0? 0 : (DB > 1? 1 : DB);
125 SB = SB < 0? 0 : (SB > 3? 3 : SB);
127 IC = IC < 0? 0 : (IC > 7? 7 :
IC);
129 DC = DC < 0? 0 : (DC > 7? 7 : DC);
163 IB = IB < 0? 0 : (IB > 1? 1 : IB);
165 DB = DB < 0? 0 : (DB > 1? 1 : DB);
167 IC = IC < 0? 0 : (IC > 7? 7 :
IC);
169 DC = DC < 0? 0 : (DC > 7? 7 : DC);
234 IC = IC < 0? 0 : (IC > 7? 7 :
IC);
236 DC = DC < 0? 0 : (DC > 7? 7 : DC);
238 SC = SC < 0? 0 : (SC > 7? 7 : SC);
302 default:
fatal(
"Internal error: No initialization code for" 314 static void initialize_cop1(
struct cpu *cpu,
struct mips_coproc *c)
317 uint64_t other_stuff = 0;
365 if (coproc_nr == 0) {
402 initialize_cop0_config(cpu, c);
409 initialize_cop1(cpu, c);
418 static void mips_timer_tick(
struct timer *
timer,
void *extra)
420 struct cpu *cpu = (
struct cpu *) extra;
439 uint64_t vaddr, uint64_t paddr0, uint64_t paddr1,
440 int valid0,
int valid1,
int dirty0,
int dirty1,
int global,
int asid,
441 int cachealgo0,
int cachealgo1)
444 printf(
"mips_coproc_tlb_set_entry(): invalid entry nr: %i\n",
452 printf(
"mips_coproc_tlb_set_entry(): invalid pagesize " 453 "(%i) for MMU3K\n", size);
478 (vaddr & ENTRYHI_R_MASK) |
483 (2*size - 1) & ~0x1fff;
494 (dirty1? ENTRYLO_D : 0) |
496 (global? ENTRYLO_G : 0) |
512 static void invalidate_asid(
struct cpu *cpu,
unsigned int asid)
519 for (i = 0; i < ntlbs; i++)
528 for (i = 0; i < ntlbs; i++) {
533 uint64_t pagesize = 0x1000;
534 uint64_t tmp = mask >> 13;
543 oldvaddr = cp->
tlbs[i].
hi &
546 if (oldvaddr & 0x80000000000ULL)
547 oldvaddr |= 0x3ffff00000000000ULL;
551 oldvaddr = (int32_t)oldvaddr;
554 oldvaddr = cp->
tlbs[i].
hi &
557 if (oldvaddr & 0x8000000000ULL)
558 oldvaddr |= 0x3fffff0000000000ULL;
567 for (uint64_t ofs = 0; ofs < pagesize; ofs += 0x1000)
570 if (cp->
tlbs[i].
lo1 & ENTRYLO_V)
571 for (uint64_t ofs = 0; ofs < pagesize; ofs += 0x1000)
584 struct mips_coproc *cp,
int reg_nr, uint64_t *ptr,
int select)
613 default:
fatal(
"coproc_register_read(): unimplemented" 614 " config register select %i\n", select);
641 fatal(
"cpu%i: warning: read from unimplemented coproc%i" 643 cp->
coproc_nr==0? cop0_names[reg_nr] :
"?");
650 *ptr = cp->
reg[reg_nr];
660 struct mips_coproc *cp,
int reg_nr, uint64_t *ptr,
int flag64,
666 uint64_t tmp2 = 0, old;
668 unsigned int old_asid;
738 fatal(
"[ cpu%i: trying to write an invalid" 739 " pagemask 0x%08lx to COP0_PAGEMASK ]\n",
745 fatal(
"[ cpu%i: r2k/r3k wired register must " 746 "always be 8 ]\n", cpu->
cpu_id);
754 if (tmp != (uint64_t)(int64_t)(int32_t)tmp)
755 fatal(
"[ WARNING: trying to write a 64-bit value" 756 " to the COUNT register! ]\n");
757 tmp = (int64_t)(int32_t)tmp;
762 int32_t compare_diff = tmp -
766 if (compare_diff < 0)
769 if (compare_diff == 0)
773 / (
double)compare_diff;
779 hz, mips_timer_tick, cpu);
794 if (tmp != (uint64_t)(int64_t)(int32_t)tmp)
795 fatal(
"[ WARNING: trying to write a 64-bit value" 796 " to the COMPARE register! ]\n");
798 tmp = (int64_t)(int32_t)tmp;
825 invalidate_asid(cpu, old_asid);
864 default:
fatal(
"[ coproc_register_write(): unimpl" 865 "emented config register select " 876 cp->
reg[reg_nr] &= ~(0x3); cp->
reg[reg_nr] |= tmp;
895 if (tmp & MIPS1_ISOL_CACHES) {
954 fatal(
"[ cpu%i: warning: write to unimplemented coproc%i " 955 "register %i (%s), data = 0x%016llx ]\n", cpu->
cpu_id,
957 cop0_names[reg_nr] :
"?", (
long long)tmp);
965 fatal(
"[ cpu%i: warning: write to READONLY coproc%i register " 970 cp->
reg[reg_nr] = tmp;
973 cp->
reg[reg_nr] = (int64_t)(int32_t)cp->
reg[reg_nr];
982 static int mips_fmt_to_ieee_fmt[32] = {
983 0, 0, 0, 0, 0, 0, 0, 0,
984 0, 0, 0, 0, 0, 0, 0, 0,
987 0, 0, 0, 0, 0, 0, 0, 0 };
989 static const char *fmtname[32] = {
990 "0",
"1",
"2",
"3",
"4",
"5",
"6",
"7",
991 "8",
"9",
"10",
"11",
"12",
"13",
"14",
"15",
992 "s",
"d",
"18",
"19",
"w",
"l",
"ps",
"23",
993 "24",
"25",
"26",
"27",
"28",
"29",
"30",
"31" };
995 static const char *ccname[16] = {
996 "f",
"un",
"eq",
"ueq",
"olt",
"ult",
"ole",
"ule",
997 "sf",
"ngle",
"seq",
"ngl",
"lt",
"nge",
"le",
"ngt" };
1000 #define FPU_OP_SUB 2 1001 #define FPU_OP_MUL 3 1002 #define FPU_OP_DIV 4 1003 #define FPU_OP_SQRT 5 1004 #define FPU_OP_MOV 6 1005 #define FPU_OP_CVT 7 1007 #define FPU_OP_ABS 9 1008 #define FPU_OP_NEG 10 1017 static void fpu_store_float_value(
struct mips_coproc *cp,
int fd,
1018 double nf,
int fmt,
int nan)
1020 int ieee_fmt = mips_fmt_to_ieee_fmt[fmt];
1028 cp->
reg[fd] = r & 0xffffffffULL;
1029 cp->
reg[(fd+1) & 31] = (r >> 32) & 0xffffffffULL;
1031 if (cp->
reg[fd] & 0x80000000ULL)
1032 cp->
reg[fd] |= 0xffffffff00000000ULL;
1033 if (cp->
reg[fd+1] & 0x80000000ULL)
1034 cp->
reg[fd+1] |= 0xffffffff00000000ULL;
1036 cp->
reg[fd] = r & 0xffffffffULL;
1038 if (cp->
reg[fd] & 0x80000000ULL)
1039 cp->
reg[fd] |= 0xffffffff00000000ULL;
1053 static int fpu_op(
struct cpu *cpu,
struct mips_coproc *cp,
int op,
int fmt,
1054 int ft,
int fs,
int fd,
int cond,
int output_fmt)
1058 int unordered,
nan, ieee_fmt = mips_fmt_to_ieee_fmt[fmt];
1067 fs_v = (fs_v & 0xffffffffULL) +
1068 (cp->
reg[(fs + 1) & 31] << 32);
1072 uint64_t v = cp->
reg[ft];
1076 v = (v & 0xffffffffULL) +
1077 (cp->
reg[(ft + 1) & 31] << 32);
1083 nf = float_value[0].
f + float_value[1].
f;
1086 fpu_store_float_value(cp, fd, nf, output_fmt,
1087 float_value[0].nan || float_value[1].nan);
1090 nf = float_value[0].
f - float_value[1].
f;
1093 fpu_store_float_value(cp, fd, nf, output_fmt,
1094 float_value[0].nan || float_value[1].nan);
1097 nf = float_value[0].
f * float_value[1].
f;
1100 fpu_store_float_value(cp, fd, nf, output_fmt,
1101 float_value[0].nan || float_value[1].nan);
1104 nan = float_value[0].
nan || float_value[1].
nan;
1105 if (fabs(float_value[1].
f) > 0.00000000001)
1106 nf = float_value[0].
f / float_value[1].
f;
1108 fatal(
"DIV by zero !!!! TODO\n");
1116 fpu_store_float_value(cp, fd, nf, output_fmt, nan);
1119 nan = float_value[0].
nan;
1120 if (float_value[0].f >= 0.0)
1121 nf = sqrt(float_value[0].f);
1123 fatal(
"SQRT by less than zero, %f !!!!\n",
1129 fpu_store_float_value(cp, fd, nf, output_fmt, nan);
1132 nf = fabs(float_value[0].f);
1134 fpu_store_float_value(cp, fd, nf, output_fmt,
1135 float_value[0].nan);
1138 nf = - float_value[0].
f;
1140 fpu_store_float_value(cp, fd, nf, output_fmt,
1141 float_value[0].nan);
1144 nf = float_value[0].
f;
1146 fpu_store_float_value(cp, fd, nf, output_fmt,
1147 float_value[0].nan);
1156 cp->
reg[fd] = fs_v & 0xffffffffULL;
1157 cp->
reg[(fd+1) & 31] = (fs_v >> 32) & 0xffffffffULL;
1158 if (cp->
reg[fd] & 0x80000000ULL)
1159 cp->
reg[fd] |= 0xffffffff00000000ULL;
1160 if (cp->
reg[fd+1] & 0x80000000ULL)
1161 cp->
reg[fd+1] |= 0xffffffff00000000ULL;
1163 cp->
reg[fd] = fs_v & 0xffffffffULL;
1164 if (cp->
reg[fd] & 0x80000000ULL)
1165 cp->
reg[fd] |= 0xffffffff00000000ULL;
1172 if (float_value[0].nan || float_value[1].nan)
1177 return (float_value[0].f == float_value[1].f);
1179 return (float_value[0].f < float_value[1].f)
1182 return (float_value[0].f < float_value[1].f)
1185 return (float_value[0].f <= float_value[1].f)
1188 return (float_value[0].f <= float_value[1].f)
1191 return (float_value[0].f < float_value[1].f);
1193 return (float_value[0].f <= float_value[1].f);
1200 case 3:
return (float_value[0].f == float_value[1].f);
1204 case 10:
return (float_value[0].f == float_value[1].f);
1205 case 11:
return (float_value[0].f == float_value[1].f);
1207 case 13:
return !(float_value[0].
f >= float_value[1].
f);
1209 case 15:
return !(float_value[0].
f > float_value[1].
f);
1213 fatal(
"fpu_op(): unimplemented condition " 1214 "code %i. see cpu_mips_coproc.c\n", cond);
1218 fatal(
"fpu_op(): unimplemented op %i\n", op);
1231 static int fpu_function(
struct cpu *cpu,
struct mips_coproc *cp,
1232 uint32_t
function,
int unassemble_only)
1234 int fd, fs, ft, fmt,
cond, cc;
1236 fmt = (
function >> 21) & 31;
1237 ft = (
function >> 16) & 31;
1238 fs = (
function >> 11) & 31;
1239 cc = (
function >> 8) & 7;
1240 fd = (
function >> 6) & 31;
1241 cond = (
function >> 0) & 15;
1245 if ((
function & 0x03e00000) == 0x01000000) {
1247 const char *instr_mnem;
1250 cc = (
function >> 18) & 7;
1251 nd = (
function >> 17) & 1;
1252 tf = (
function >> 16) & 1;
1253 imm =
function & 65535;
1258 if (nd == 0 && tf == 0) instr_mnem =
"bc1f";
1259 if (nd == 0 && tf == 1) instr_mnem =
"bc1t";
1260 if (nd == 1 && tf == 0) instr_mnem =
"bc1fl";
1261 if (nd == 1 && tf == 1) instr_mnem =
"bc1tl";
1264 debug(
"%s\t%i,0x%016llx\n", instr_mnem, cc,
1265 (
long long) (cpu->
pc + 4 + (imm << 2)));
1266 if (unassemble_only)
1269 fatal(
"INTERNAL ERROR: MIPS coprocessor branches should not" 1270 " be implemented in cpu_mips_coproc.c, but in" 1271 " cpu_mips_instr.c!\n");
1276 if ((
function & 0x0000003f) == 0x00000000) {
1278 debug(
"add.%s\tr%i,r%i,r%i\n",
1279 fmtname[fmt], fd, fs, ft);
1280 if (unassemble_only)
1283 fpu_op(cpu, cp,
FPU_OP_ADD, fmt, ft, fs, fd, -1, fmt);
1288 if ((
function & 0x0000003f) == 0x00000001) {
1290 debug(
"sub.%s\tr%i,r%i,r%i\n",
1291 fmtname[fmt], fd, fs, ft);
1292 if (unassemble_only)
1295 fpu_op(cpu, cp,
FPU_OP_SUB, fmt, ft, fs, fd, -1, fmt);
1300 if ((
function & 0x0000003f) == 0x00000002) {
1302 debug(
"mul.%s\tr%i,r%i,r%i\n",
1303 fmtname[fmt], fd, fs, ft);
1304 if (unassemble_only)
1307 fpu_op(cpu, cp,
FPU_OP_MUL, fmt, ft, fs, fd, -1, fmt);
1312 if ((
function & 0x0000003f) == 0x00000003) {
1314 debug(
"div.%s\tr%i,r%i,r%i\n",
1315 fmtname[fmt], fd, fs, ft);
1316 if (unassemble_only)
1319 fpu_op(cpu, cp,
FPU_OP_DIV, fmt, ft, fs, fd, -1, fmt);
1324 if ((
function & 0x001f003f) == 0x00000004) {
1326 debug(
"sqrt.%s\tr%i,r%i\n", fmtname[fmt], fd, fs);
1327 if (unassemble_only)
1330 fpu_op(cpu, cp,
FPU_OP_SQRT, fmt, -1, fs, fd, -1, fmt);
1335 if ((
function & 0x001f003f) == 0x00000005) {
1337 debug(
"abs.%s\tr%i,r%i\n", fmtname[fmt], fd, fs);
1338 if (unassemble_only)
1341 fpu_op(cpu, cp,
FPU_OP_ABS, fmt, -1, fs, fd, -1, fmt);
1346 if ((
function & 0x0000003f) == 0x00000006) {
1348 debug(
"mov.%s\tr%i,r%i\n", fmtname[fmt], fd, fs);
1349 if (unassemble_only)
1352 fpu_op(cpu, cp,
FPU_OP_MOV, fmt, -1, fs, fd, -1, fmt);
1357 if ((
function & 0x001f003f) == 0x00000007) {
1359 debug(
"neg.%s\tr%i,r%i\n", fmtname[fmt], fd, fs);
1360 if (unassemble_only)
1363 fpu_op(cpu, cp,
FPU_OP_NEG, fmt, -1, fs, fd, -1, fmt);
1368 if ((
function & 0x001f003f) == 0x00000009) {
1370 debug(
"trunc.l.%s\tr%i,r%i\n", fmtname[fmt], fd, fs);
1371 if (unassemble_only)
1381 if ((
function & 0x001f003f) == 0x0000000d) {
1383 debug(
"trunc.w.%s\tr%i,r%i\n", fmtname[fmt], fd, fs);
1384 if (unassemble_only)
1394 if ((
function & 0x000000f0) == 0x00000030) {
1399 debug(
"c.%s.%s\tcc%i,r%i,r%i\n", ccname[cond],
1400 fmtname[fmt], cc, fs, ft);
1401 if (unassemble_only)
1404 cond_true = fpu_op(cpu, cp,
FPU_OP_C, fmt,
1405 ft, fs, -1, cond, fmt);
1432 if ((
function & 0x001f003f) == 0x00000020) {
1434 debug(
"cvt.s.%s\tr%i,r%i\n", fmtname[fmt], fd, fs);
1435 if (unassemble_only)
1443 if ((
function & 0x001f003f) == 0x00000021) {
1445 debug(
"cvt.d.%s\tr%i,r%i\n", fmtname[fmt], fd, fs);
1446 if (unassemble_only)
1454 if ((
function & 0x001f003f) == 0x00000024) {
1456 debug(
"cvt.w.%s\tr%i,r%i\n", fmtname[fmt], fd, fs);
1457 if (unassemble_only)
1476 int i, found, g_bit;
1477 uint64_t vpn2, xmask;
1486 fatal(
"[ warning: tlbr from index %i (too " 1498 fatal(
"[ warning: tlbr from index %i (too " 1559 uint64_t a = vpn2 & ~cp->
tlbs[i].
mask;
1560 uint64_t b = (cp->
tlbs[i].
hi & xmask) &
1583 0xffffffff00000000ULL;
1620 fatal(
"warning: tlb index %i too high (max is %i)\n",
1629 fatal(
"{ old TLB entry at index %02x:", index);
1631 fatal(
" hi=%08" PRIx32, (uint32_t)cp->
tlbs[index].
hi);
1632 fatal(
" lo=%08" PRIx32, (uint32_t)cp->
tlbs[index].
lo0);
1636 fatal(
" hi=%08" PRIx32, (uint32_t)cp->
tlbs[index].
hi);
1637 fatal(
" lo0=%08" PRIx32, (uint32_t)cp->
tlbs[index].
lo0);
1638 fatal(
" lo1=%08" PRIx32, (uint32_t)cp->
tlbs[index].
lo1);
1662 oldvaddr = (int32_t) oldvaddr;
1674 oldvaddr = cp->
tlbs[index].
hi &
1677 if (oldvaddr & 0x80000000000ULL)
1678 oldvaddr |= 0x3ffff00000000000ULL;
1682 oldvaddr = (int32_t)oldvaddr;
1685 oldvaddr = cp->
tlbs[index].
hi &
1688 if (oldvaddr & 0x8000000000ULL)
1689 oldvaddr |= 0x3fffff0000000000ULL;
1693 uint64_t mask = cp->
tlbs[index].
mask;
1694 uint64_t pagesize = 0x1000;
1695 uint64_t tmp = mask >> 13;
1707 for (uint64_t ofs = 0; ofs < pagesize; ofs += 0x1000)
1710 if (cp->
tlbs[index].
lo1 & ENTRYLO_V)
1711 for (uint64_t ofs = 0; ofs < pagesize; ofs += 0x1000)
1727 uint64_t vaddr1, vaddr2;
1738 if (i == index && !randomflag)
1745 vaddr2 = cp->
tlbs[i].
hi &
1747 if (vaddr1 == vaddr2 && ((cp->
tlbs[i].
lo0 &
1749 fatal(
"\n[ WARNING! tlbw%s to index 0x%02x " 1750 "vaddr=0x%llx (asid 0x%02x) is already in" 1751 " the TLB (entry 0x%02x) ! ]\n\n",
1752 randomflag?
"r" :
"i", index,
1753 (
long long)vaddr1, asid, i);
1761 uint32_t vaddr, paddr;
1763 unsigned char *memblock = NULL;
1784 fatal(
"Wow! Interesting case; tlbw* while caches" 1785 " are isolated. TODO\n");
1793 if (memblock != NULL &&
1799 unsigned char *memblock = NULL;
1800 int pfn_shift = 12, vpn_shift = 12;
1802 uint64_t vaddr0, vaddr1, paddr0, paddr1, ptmp;
1824 fatal(
"1KB pages don't work with dyntrans.\n");
1829 case 0x0001fff:
break;
1830 case 0x0007fff: vpn_shift = 14;
break;
1831 case 0x001ffff: vpn_shift = 16;
break;
1832 case 0x007ffff: vpn_shift = 18;
break;
1833 case 0x01fffff: vpn_shift = 20;
break;
1834 case 0x07fffff: vpn_shift = 22;
break;
1835 case 0x1ffffff: vpn_shift = 24;
break;
1836 case 0x7ffffff: vpn_shift = 26;
break;
1837 default:
fatal(
"Unimplemented MASK = 0x%016x\n", mask);
1841 pfn_shift = vpn_shift;
1845 >> vpn_shift << vpn_shift;
1848 >> vpn_shift << vpn_shift;
1851 vaddr0 = cp->
tlbs[index].
hi &
1854 if (vaddr0 & 0x80000000000ULL)
1855 vaddr0 |= 0x3ffff00000000000ULL;
1859 vaddr0 = (int32_t)vaddr0;
1862 vaddr0 = cp->
tlbs[index].
hi &
1865 if (vaddr0 & 0x8000000000ULL)
1866 vaddr0 |= 0x3fffff0000000000ULL;
1869 vaddr1 = vaddr0 | (1 << vpn_shift);
1891 psize = 1 << pfn_shift;
1894 for (ptmp = 0; ptmp < psize; ptmp += 0x1000)
1899 for (ptmp = 0; ptmp < psize; ptmp += 0x1000)
1914 if (psize == 0x1000) {
1961 uint32_t
function,
int unassemble_only,
int running)
1963 int co_bit,
op, rt, rd, fs, copz;
1967 if (unassemble_only) {
1968 debug(
"cop%i\t0x%08x (coprocessor not available)\n",
1969 cpnr, (
int)
function);
1972 fatal(
"[ pc=0x%016llx cop%i\t0x%08x (coprocessor not " 1973 "available)\n", (
long long)cpu->
pc, cpnr, (
int)
function);
1984 copz = (
function >> 21) & 31;
1985 rt = (
function >> 16) & 31;
1986 rd = (
function >> 11) & 31;
1988 if (cpnr < 2 && (((
function & 0x03e007f8) == (
COPz_MFCz << 21))
1989 || ((
function & 0x03e007f8) == (
COPz_DMFCz << 21)))) {
1990 if (unassemble_only) {
1992 cpnr, regnames[rt]);
1994 debug(
"%s", cop0_names[rd]);
1998 debug(
",%i", (
int)(
function & 7));
2003 rd, &tmpvalue,
function & 7);
2008 if (cpu->
cd.
mips.
gpr[rt] & 0x80000000ULL)
2009 cpu->
cd.
mips.
gpr[rt] |= 0xffffffff00000000ULL;
2014 if (cpnr < 2 && (((
function & 0x03e007f8) == (
COPz_MTCz << 21))
2015 || ((
function & 0x03e007f8) == (
COPz_DMTCz << 21)))) {
2016 if (unassemble_only) {
2018 cpnr, regnames[rt]);
2020 debug(
"%s", cop0_names[rd]);
2024 debug(
",%i", (
int)(
function & 7));
2031 tmpvalue &= 0xffffffffULL;
2032 if (tmpvalue & 0x80000000ULL)
2033 tmpvalue |= 0xffffffff00000000ULL;
2036 &tmpvalue, copz ==
COPz_DMTCz,
function & 7);
2040 if (cpnr <= 1 && (((
function & 0x03e007ff) == (
COPz_CFCz << 21))
2041 || ((
function & 0x03e007ff) == (
COPz_CTCz << 21)))) {
2044 rt = (
function >> 16) & 31;
2045 fs = (
function >> 11) & 31;
2046 if (unassemble_only) {
2047 debug(
"cfc%i\t%s,r%i\n", cpnr,
2056 rt = (
function >> 16) & 31;
2057 fs = (
function >> 11) & 31;
2058 if (unassemble_only) {
2059 debug(
"ctc%i\t%s,r%i\n", cpnr,
2066 fatal(
"[ warning: unimplemented ctc%i, " 2067 "0x%08x -> ctl reg %i ]\n", cpnr,
2072 fatal(
"[ Attempt to write to FPU " 2073 "control register 0 (?) ]\n");
2086 0x017fffffULL) | ((tmp & 1)
2088 | (((tmp & 0xfe) >> 1) <<
2094 0xffffff00ULL) | ((tmp >>
2117 if (fpu_function(cpu, cp,
function, unassemble_only))
2124 if ((
function & 0xfffff) ==
COP0_EI) {
2125 if (unassemble_only) {
2134 if ((
function & 0xfffff) ==
COP0_DI) {
2135 if (unassemble_only) {
2145 co_bit = (
function >> 25) & 1;
2149 if (!unassemble_only) {
2150 fatal(
"FATAL INTERNAL ERROR: Should be implemented" 2151 " with dyntrans instead.\n");
2157 if ((
function & 0x03e0ffdf) == 0x01606000) {
2158 debug(
"%ci",
function & 0x20?
'e' :
'd');
2160 debug(
"\t%s", regnames[rt]);
2166 op = (
function) & 0xff;
2181 debug(
"\tindex=%08llx",
2183 debug(
", random=%08llx",
2185 debug(
", mask=%016llx",
2187 debug(
", hi=%016llx",
2189 debug(
", lo0=%016llx",
2191 debug(
", lo1=%016llx\n",
2210 int code = (
function >> 6) & 0x7ffff;
2213 debug(
"\t0x%x", code);
2224 debug(
"hibernate\n");
2235 if (unassemble_only) {
2236 debug(
"decstation_r2020_writeback\n");
2243 if (unassemble_only) {
2244 debug(
"cop%i\t0x%08x (unimplemented)\n", cpnr, (
int)
function);
2248 fatal(
"cpu%i: UNIMPLEMENTED coproc%i function %08" PRIx32
" " 2250 (uint32_t)
function, cpu->
pc);
#define MIPS_REGISTER_NAMES
void * zeroed_alloc(size_t s)
void fatal(const char *fmt,...)
int cache_secondary_linesize
#define ENTRYHI_VPN2_MASK_R10K
void mips_coproc_tlb_set_entry(struct cpu *cpu, int entrynr, int size, uint64_t vaddr, uint64_t paddr0, uint64_t paddr1, int valid0, int valid1, int dirty0, int dirty1, int global, int asid, int cachealgo0, int cachealgo1)
#define COP1_REVISION_SINGLE
#define R2K3K_ENTRYHI_ASID_MASK
#define MIPS1_ISOL_CACHES
void coproc_function(struct cpu *cpu, struct mips_coproc *cp, int cpnr, uint32_t function, int unassemble_only, int running)
#define R2K3K_ENTRYLO_PFN_MASK
void coproc_tlbwri(struct cpu *cpu, int randomflag)
uint64_t fcr[N_MIPS_FCRS]
void f(int s, int func, int only_name)
#define R2K3K_INDEX_SHIFT
void ieee_interpret_float_value(uint64_t x, struct ieee_float_value *fvp, int fmt)
#define R2K3K_ENTRYHI_ASID_SHIFT
#define CONTEXT_BADVPN2_MASK_R4100
#define ENTRYHI_VPN2_MASK
int cache_pdcache_linesize
int32_t count_register_read_count
#define CHECK_ALLOCATION(ptr)
void timer_update_frequency(struct timer *t, double new_freq)
uint64_t reg[N_MIPS_COPROC_REGS]
int cache_picache_linesize
#define R2K3K_ENTRYHI_VPN_MASK
void coproc_eret(struct cpu *cpu)
int compare_interrupts_pending
struct timer * timer_add(double freq, void(*timer_tick)(struct timer *timer, void *extra), void *extra)
#define ENTRYLO_PFN_SHIFT
void mips_cpu_exception(struct cpu *cpu, int exccode, int tlb, uint64_t vaddr, int coproc_nr, uint64_t vaddr_vpn2, int vaddr_asid, int x_64)
#define R2K3K_RANDOM_SHIFT
struct mips_coproc * coproc[N_MIPS_COPROCS]
#define MIPS_FCSR_FCC0_SHIFT
#define CONTEXT_BADVPN2_MASK
void coproc_register_write(struct cpu *cpu, struct mips_coproc *cp, int reg_nr, uint64_t *ptr, int flag64, int select)
struct mips_coproc * mips_coproc_new(struct cpu *cpu, int coproc_nr)
#define R2K3K_RANDOM_MASK
uint64_t cop0_config_select1
uint64_t ieee_store_float_value(double nf, int fmt, int nan)
void(* update_translation_table)(struct cpu *, uint64_t vaddr_page, unsigned char *host_page, int writeflag, uint64_t paddr_page)
uint64_t gpr[N_MIPS_GPRS]
void coproc_register_read(struct cpu *cpu, struct mips_coproc *cp, int reg_nr, uint64_t *ptr, int select)
addr & if(addr >=0x24 &&page !=NULL)
void(* invalidate_code_translation)(struct cpu *, uint64_t paddr, int flags)
struct mips_cpu_type_def cpu_type
#define R2K3K_CONTEXT_BADVPN_MASK
void(* invalidate_translation_caches)(struct cpu *, uint64_t paddr, int flags)
#define MIPS_FCSR_FCC1_SHIFT
int last_written_tlb_index
void coproc_tlbpr(struct cpu *cpu, int readflag)
unsigned char * memory_paddr_to_hostaddr(struct memory *mem, uint64_t paddr, int writeflag)
#define COP1_REVISION_DOUBLE