sgi_macereg.h Source File
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Go to the documentation of this file. 38 #define MACE_BASE 0x1f000000 42 #define MACE_PCI_ERROR_ADDR 0x00 43 #define MACE_PCI_ERROR_FLAGS 0x04 45 #define MACE_PCI_CONTROL 0x08 46 #define MACE_PCI_CONTROL_INT_MASK 0x000000ff 47 #define MACE_PCI_CONTROL_SERR_ENA 0x00000100 48 #define MACE_PCI_CONTROL_ARB_N6 0x00000200 49 #define MACE_PCI_CONTROL_PARITY_ERR 0x00000400 50 #define MACE_PCI_CONTROL_MRMRA_ENA 0x00000800 51 #define MACE_PCI_CONTROL_ARB_N3 0x00001000 52 #define MACE_PCI_CONTROL_ARB_N4 0x00002000 53 #define MACE_PCI_CONTROL_ARB_N5 0x00004000 54 #define MACE_PCI_CONTROL_PARK_LIU 0x00008000 56 #define MACE_PCI_CONTROL_INV_INT_MASK 0x00ff0000 57 #define MACE_PCI_CONTROL_OVERRUN_INT 0x01000000 58 #define MACE_PCI_CONTROL_PARITY_INT 0x02000000 59 #define MACE_PCI_CONTROL_SERR_INT 0x04000000 60 #define MACE_PCI_CONTROL_IT_INT 0x08000000 61 #define MACE_PCI_CONTROL_RE_INT 0x10000000 62 #define MACE_PCI_CONTROL_DPED_INT 0x20000000 63 #define MACE_PCI_CONTROL_TAR_INT 0x40000000 64 #define MACE_PCI_CONTROL_MAR_INT 0x80000000 67 #define MACE_PCI_REV_INFO_R 0x0c 68 #define MACE_PCI_FLUSH_W 0x0c 69 #define MACE_PCI_CONFIG_ADDR 0xcf8 70 #define MACE_PCI_CONFIG_DATA 0xcfc 71 #define MACE_PCI_LOW_MEMORY 0x1a000000 72 #define MACE_PCI_LOW_IO 0x18000000 73 #define MACE_PCI_NATIVE_VIEW 0x40000000 74 #define MACE_PCI_IO 0x80000000 75 #define MACE_PCI_HI_MEMORY 0x280000000 76 #define MACE_PCI_HI_IO 0x100000000 78 #define MACE_VIN1 0x100000 79 #define MACE_VIN2 0x180000 80 #define MACE_VOUT 0x200000 81 #define MACE_PERIF 0x300000 82 #define MACE_ISA_EXT 0x380000 90 #define MACE_UST_MSC 0 92 #define MACE_AUDIO (MACE_PERIF + 0x00000) 93 #define MACE_ISA (MACE_PERIF + 0x10000) 94 #define MACE_KBDMS (MACE_PERIF + 0x20000) 95 #define MACE_I2C (MACE_PERIF + 0x30000) 96 #define MACE_UST_MSC (MACE_PERIF + 0x40000) 103 #define MACE_PERR_MASTER_ABORT 0x80000000 104 #define MACE_PERR_TARGET_ABORT 0x40000000 105 #define MACE_PERR_DATA_PARITY_ERR 0x20000000 106 #define MACE_PERR_RETRY_ERR 0x10000000 107 #define MACE_PERR_ILLEGAL_CMD 0x08000000 108 #define MACE_PERR_SYSTEM_ERR 0x04000000 109 #define MACE_PERR_INTERRUPT_TEST 0x02000000 110 #define MACE_PERR_PARITY_ERR 0x01000000 111 #define MACE_PERR_OVERRUN 0x00800000 112 #define MACE_PERR_RSVD 0x00400000 113 #define MACE_PERR_MEMORY_ADDR 0x00200000 114 #define MACE_PERR_CONFIG_ADDR 0x00100000 115 #define MACE_PERR_MASTER_ABORT_ADDR_VALID 0x00080000 116 #define MACE_PERR_TARGET_ABORT_ADDR_VALID 0x00040000 117 #define MACE_PERR_DATA_PARITY_ADDR_VALID 0x00020000 118 #define MACE_PERR_RETRY_ADDR_VALID 0x00010000 124 #define MACE_ISA_EPP_BASE (MACE_ISA_EXT + 0x00000) 125 #define MACE_ISA_ECP_BASE (MACE_ISA_EXT + 0x08000) 126 #define MACE_ISA_SER1_BASE (MACE_ISA_EXT + 0x10000) 127 #define MACE_ISA_SER2_BASE (MACE_ISA_EXT + 0x18000) 128 #define MACE_ISA_RTC_BASE (MACE_ISA_EXT + 0x20000) 129 #define MACE_ISA_GAME_BASE (MACE_ISA_EXT + 0x30000) 138 #define MACE_ISA_RINGBASE (MACE_ISA + 0x0000) 142 #define MACE_ISA_FLASH_NIC_REG (MACE_ISA + 0x0008) 143 #define MACE_ISA_FLASH_WE 0x01 144 #define MACE_ISA_PWD_CLEAR 0x02 145 #define MACE_ISA_NIC_DEASSERT 0x04 146 #define MACE_ISA_NIC_DATA 0x08 147 #define MACE_ISA_LED_RED 0x10 148 #define MACE_ISA_LED_GREEN 0x20 149 #define MACE_ISA_DP_RAM_ENABLE 0x40 153 #define MACE_ISA_INT_STATUS (MACE_ISA + 0x0010) 154 #define MACE_ISA_INT_MASK (MACE_ISA + 0x0018) 157 #define MACE_ISA_INT_RTC_IRQ 0x00000100 165 #define MACE_UST (MACE_UST_MSC + 0x00) 166 #define MACE_COMPARE1 (MACE_UST_MSC + 0x08) 167 #define MACE_COMPARE2 (MACE_UST_MSC + 0x10) 168 #define MACE_COMPARE3 (MACE_UST_MSC + 0x18) 169 #define MACE_UST_PERIOD 960 171 #define MACE_AIN_MSC_UST (MACE_UST_MSC + 0x20) 172 #define MACE_AOUT1_MSC_UST (MACE_UST_MSC + 0x28) 173 #define MACE_AOUT2_MSC_UST (MACE_UST_MSC + 0x30) 174 #define MACE_VIN1_MSC_UST (MACE_UST_MSC + 0x38) 175 #define MACE_VIN2_MSC_UST (MACE_UST_MSC + 0x40) 176 #define MACE_VOUT_MSC_UST (MACE_UST_MSC + 0x48)
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