gtreg.h Source File

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gtreg.h
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1 /* GXemul: $Id: gtreg.h,v 1.3 2006-09-23 03:52:10 debug Exp $ */
2 /* $NetBSD: gtreg.h,v 1.2 2005/12/24 20:07:03 perry Exp $ */
3 
4 /*
5  * This is basically malta/dev/gtreg.h from NetBSD, with additional
6  * defines that Linux uses. Symbol names are practically the same in
7  * NetBSD and Linux, which simplifies things.
8  *
9  * Also parts from cobalt/dev/gtreg.h from NetBSD.
10  *
11  * TODO: Find a better gtreg.h.
12  */
13 
14 #ifndef GTREG_H
15 #define GTREG_H
16 
17 #define GT_REGVAL(x) *((volatile u_int32_t *) \
18  (MIPS_PHYS_TO_KSEG1(MALTA_CORECTRL_BASE + (x))))
19 
20 /* CPU Configuration Register Map */
21 #define GT_CPU_INT 0x000
22 #define GT_MULTIGT 0x120
23 
24 /* CPU Address Decode Register Map */
25 #define GT_PCI0IOLD_OFS 0x048
26 #define GT_PCI0IOHD_OFS 0x050
27 #define GT_PCI0M0LD_OFS 0x058
28 #define GT_PCI0M0HD_OFS 0x060
29 #define GT_PCI0M1LD_OFS 0x080
30 #define GT_PCI0M1HD_OFS 0x088
31 #define GT_PCI0IOREMAP_OFS 0x0f0
32 #define GT_PCI0M0REMAP_OFS 0x0f8
33 #define GT_PCI0M1REMAP_OFS 0x100
34 
35 #define GT_N_DECODE_REGS (0x108 / 8)
36 
37 /* CPU Error Report Register Map */
38 
39 /* CPU Sync Barrier Register Map */
40 
41 /* SDRAM and Device Address Decode Register Map */
42 
43 /* SDRAM Configuration Register Map */
44 
45 /* SDRAM Parameters Register Map */
46 
47 /* ECC Register Map */
48 
49 /* Device Parameters Register Map */
50 
51 /* DMA Record Register Map */
52 
53 /* DMA Arbiter Register Map */
54 
55 /* Timer/Counter Register Map */
56 #define GT_TIMER_COUNTER0 0x850
57 #define GT_TIMER_COUNTER1 0x854
58 #define GT_TIMER_COUNTER2 0x858
59 #define GT_TIMER_COUNTER3 0x85c
60 
61 #define GT_TIMER_CTRL 0x864
62 #define ENTC0 0x01
63 #define TCSEL0 0x02
64 #define ENTC1 0x04
65 #define TCSEL1 0x08
66 #define ENTC2 0x10
67 #define TCSEL2 0x20
68 #define ENTC3 0x40
69 #define TCSEL3 0x80
70 
71 /* PCI Internal Register Map */
72 #define GT_PCI0_CMD_OFS 0xc00
73 #define GT_PCI0_CFG_ADDR 0xcf8
74 #define GT_PCI0_CFG_DATA 0xcfc
75 #define GT_PCI0_INTR_ACK 0xc34
76 
77 /* Interrupts Register Map */
78 #define GT_INTR_CAUSE 0xc18
79 #define GTIC_INTSUM 0x00000001
80 #define GTIC_MEMOUT 0x00000002
81 #define GTIC_DMAOUT 0x00000004
82 #define GTIC_CPUOUT 0x00000008
83 #define GTIC_DMA0COMP 0x00000010
84 #define GTIC_DMA1COMP 0x00000020
85 #define GTIC_DMA2COMP 0x00000040
86 #define GTIC_DMA3COMP 0x00000080
87 #define GTIC_T0EXP 0x00000100
88 #define GTIC_T1EXP 0x00000200
89 #define GTIC_T2EXP 0x00000400
90 #define GTIC_T3EXP 0x00000800
91 #define GTIC_MASRDERR0 0x00001000
92 #define GTIC_SLVWRERR0 0x00002000
93 #define GTIC_MASWRERR0 0x00004000
94 #define GTIC_SLVRDERR0 0x00008000
95 #define GTIC_ADDRERR0 0x00010000
96 #define GTIC_MEMERR 0x00020000
97 #define GTIC_MASABORT0 0x00040000
98 #define GTIC_TARABORT0 0x00080000
99 #define GTIC_RETRYCNT0 0x00100000
100 #define GTIC_PMCINT_0 0x00200000
101 #define GTIC_CPUINT 0x0c300000
102 #define GTIC_PCINT 0xc3000000
103 #define GTIC_CPUINTSUM 0x40000000
104 #define GTIC_PCIINTSUM 0x80000000
105 
106 /* PCI Configuration Register Map */
107 //#define GT_PCICONFIGBASE 0
108 //#define GT_PCIDID BONITO(GT_PCICONFIGBASE + 0x00)
109 //#define GT_PCICMD BONITO(GT_PCICONFIGBASE + 0x04)
110 //#define GT_PCICLASS BONITO(GT_PCICONFIGBASE + 0x08)
111 //#define GT_PCILTIMER BONITO(GT_PCICONFIGBASE + 0x0c)
112 //#define GT_PCIBASE0 BONITO(GT_PCICONFIGBASE + 0x10)
113 //#define GT_PCIBASE1 BONITO(GT_PCICONFIGBASE + 0x14)
114 //#define GT_PCIBASE2 BONITO(GT_PCICONFIGBASE + 0x18)
115 //#define GT_PCIEXPRBASE BONITO(GT_PCICONFIGBASE + 0x30)
116 //#define GT_PCIINT BONITO(GT_PCICONFIGBASE + 0x3c)
117 
118 /* PCI Configuration, Function 1, Register Map */
119 
120 /* I2O Support Register Map */
121 
122 #endif /* !GTREG_H */

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