dev_sgi_ip30.cc Source File

Back to the index.

dev_sgi_ip30.cc
Go to the documentation of this file.
1 /*
2  * Copyright (C) 2004-2009 Anders Gavare. All rights reserved.
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions are met:
6  *
7  * 1. Redistributions of source code must retain the above copyright
8  * notice, this list of conditions and the following disclaimer.
9  * 2. Redistributions in binary form must reproduce the above copyright
10  * notice, this list of conditions and the following disclaimer in the
11  * documentation and/or other materials provided with the distribution.
12  * 3. The name of the author may not be used to endorse or promote products
13  * derived from this software without specific prior written permission.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25  * SUCH DAMAGE.
26  *
27  *
28  * COMMENT: SGI IP30 stuff
29  *
30  * NOTE/TODO: This is just comprised of hardcoded guesses so far. (Ugly.)
31  */
32 
33 #include <stdio.h>
34 #include <stdlib.h>
35 #include <string.h>
36 
37 #include "cpu.h"
38 #include "device.h"
39 #include "machine.h"
40 #include "memory.h"
41 #include "misc.h"
42 
43 
44 #define DEV_SGI_IP30_LENGTH 0x80000
45 
46 struct sgi_ip30_data {
47  /* ip30: */
48  uint64_t imask0; /* 0x10000 */
49  uint64_t reg_0x10018;
50  uint64_t isr; /* 0x10030 */
51  uint64_t reg_0x20000;
52  uint64_t reg_0x30000;
53 
54  /* ip30_2: */
55  uint64_t reg_0x0029c;
56 
57  /* ip30_3: */
58  uint64_t reg_0x00284;
59 
60  /* ip30_4: */
61  uint64_t reg_0x000b0;
62 
63  /* ip30_5: */
64  uint64_t reg_0x00000;
65 };
66 
67 
68 DEVICE_TICK(sgi_ip30)
69 {
70  struct sgi_ip30_data *d = (struct sgi_ip30_data *) extra;
71 
72  d->reg_0x20000 += 1000;
73 
74  if (d->imask0 & ((int64_t)1<<50)) {
75  /* TODO: Only interrupt if reg 0x20000 (the counter)
76  has passed the compare (0x30000). */
77 fatal("IP30 legacy interrupt rewrite: TODO\n");
78 abort();
79 // cpu_interrupt(cpu, 8+1 + 50);
80  }
81 }
82 
83 
84 DEVICE_ACCESS(sgi_ip30)
85 {
86  struct sgi_ip30_data *d = (struct sgi_ip30_data *) extra;
87  uint64_t idata = 0, odata = 0;
88 
89  if (writeflag == MEM_WRITE)
90  idata = memory_readmax64(cpu, data, len);
91 
92  switch (relative_addr) {
93 
94  case 0x20:
95  /* Memory bank configuration: */
96  odata = 0x80010000ULL;
97  break;
98 
99  case 0x10000: /* Interrupt mask register 0: */
100  if (writeflag == MEM_WRITE) {
101  d->imask0 = idata;
102  } else {
103  odata = d->imask0;
104  }
105  break;
106 
107  case 0x10018:
108  /*
109  * If this is not implemented, the IP30 PROM complains during
110  * bootup:
111  *
112  * *FAILED*
113  * Address: 0xffffffffaff10018, Expected:
114  * 0x0000000000000001, Received: 0x0000000000000000
115  */
116  if (writeflag == MEM_WRITE) {
117  d->reg_0x10018 = idata;
118  } else {
119  odata = d->reg_0x10018;
120  }
121  break;
122 
123  case 0x10020: /* Set ISR, according to Linux/IP30 */
124  d->isr = idata;
125  /* Recalculate CPU interrupt assertions: */
126 fatal("IP30 legacy interrupt rewrite: TODO\n");
127 abort();
128 // cpu_interrupt(cpu, 8);
129  break;
130 
131  case 0x10028: /* Clear ISR, according to Linux/IP30 */
132  d->isr &= ~idata;
133  /* Recalculate CPU interrupt assertions: */
134 fatal("IP30 legacy interrupt rewrite: TODO\n");
135 abort();
136 // cpu_interrupt(cpu, 8);
137  break;
138 
139  case 0x10030: /* Interrupt Status Register */
140  if (writeflag == MEM_WRITE) {
141  /* Clear-on-write (TODO: is this correct?) */
142  d->isr &= ~idata;
143  /* Recalculate CPU interrupt assertions: */
144 fatal("IP30 legacy interrupt rewrite: TODO\n");
145 abort();
146 // cpu_interrupt(cpu, 8);
147  } else {
148  odata = d->isr;
149  }
150  break;
151 
152  case 0x20000:
153  /* A counter */
154  if (writeflag == MEM_WRITE) {
155  d->reg_0x20000 = idata;
156  } else {
157  odata = d->reg_0x20000;
158  }
159  break;
160 
161  case 0x30000:
162  if (writeflag == MEM_WRITE) {
163  d->reg_0x30000 = idata;
164  } else {
165  odata = d->reg_0x30000;
166  }
167  break;
168 
169  default:
170  if (writeflag == MEM_WRITE) {
171  debug("[ sgi_ip30: unimplemented write to address "
172  "0x%x, data=0x%02x ]\n", (int)relative_addr,
173  (int)idata);
174  } else {
175  debug("[ sgi_ip30: unimplemented read from address"
176  " 0x%x ]\n", (int)relative_addr);
177  }
178  }
179 
180  if (writeflag == MEM_READ)
181  memory_writemax64(cpu, data, len, odata);
182 
183  return 1;
184 }
185 
186 
187 DEVICE_ACCESS(sgi_ip30_2)
188 {
189  struct sgi_ip30_data *d = (struct sgi_ip30_data *) extra;
190  uint64_t idata = 0, odata = 0;
191 
192  idata = memory_readmax64(cpu, data, len);
193 
194  switch (relative_addr) {
195 
196  /* 0x114 + 0x40 * (wid - 8): 0x80000000 for "alive",
197  according to Linux/IP30 */
198 
199  case 0x114 + 0x40 * (12 - 8):
200  fatal("[ IP30: asdvasdvnb ]\n");
201  odata = 0x80000000;
202  break;
203 
204  case 0x0029c:
205  /*
206  * If this is not implemented, the IP30 PROM complains during
207  * bootup:
208  *
209  * *FAILED*
210  * Address: 0xffffffffb000029c, Expected:
211  * 0x0000000000000001, Received: 0x0000000000000000
212  */
213  if (writeflag == MEM_WRITE) {
214  d->reg_0x0029c = idata;
215  } else {
216  odata = d->reg_0x0029c;
217  }
218  break;
219  default:
220  if (writeflag == MEM_WRITE) {
221  debug("[ sgi_ip30_2: unimplemented write to "
222  "address 0x%x, data=0x%02x ]\n",
223  (int)relative_addr, (int)idata);
224  } else {
225  debug("[ sgi_ip30_2: unimplemented read from address "
226  "0x%x ]\n", (int)relative_addr);
227  }
228  }
229 
230  if (writeflag == MEM_READ)
231  memory_writemax64(cpu, data, len, odata);
232 
233  return 1;
234 }
235 
236 
237 DEVICE_ACCESS(sgi_ip30_3)
238 {
239  struct sgi_ip30_data *d = (struct sgi_ip30_data *) extra;
240  uint64_t idata = 0, odata = 0;
241 
242  idata = memory_readmax64(cpu, data, len);
243 
244  switch (relative_addr) {
245 
246  case 0xb4:
247  if (writeflag == MEM_WRITE) {
248  debug("[ sgi_ip30_3: unimplemented write to "
249  "address 0x%x, data=0x%02x ]\n",
250  (int)relative_addr, (int)idata);
251  } else {
252  odata = 2; /* should be 2, or Irix loops */
253  }
254  break;
255 
256  case 0x00104:
257  if (writeflag == MEM_WRITE) {
258  debug("[ sgi_ip30_3: unimplemented write to address "
259  "0x%x, data=0x%02x ]\n", (int)relative_addr,
260  (int)idata);
261  } else {
262  odata = 64; /* should be 64, or the PROM
263  complains */
264  }
265  break;
266 
267  case 0x00284:
268  /*
269  * If this is not implemented, the IP30 PROM complains during
270  * bootup:
271  *
272  * *FAILED*
273  * Address: 0xffffffffbf000284, Expected:
274  * 0x0000000000000001, Received: 0x0000000000000000
275  */
276  if (writeflag == MEM_WRITE) {
277  d->reg_0x00284 = idata;
278  } else {
279  odata = d->reg_0x00284;
280  }
281  break;
282 
283  default:
284  if (writeflag == MEM_WRITE) {
285  debug("[ sgi_ip30_3: unimplemented write to address "
286  "0x%x, data=0x%02x ]\n", (int)relative_addr,
287  (int)idata);
288  } else {
289  debug("[ sgi_ip30_3: unimplemented read from "
290  "address 0x%x ]\n", (int)relative_addr);
291  }
292  }
293 
294  if (writeflag == MEM_READ)
295  memory_writemax64(cpu, data, len, odata);
296 
297  return 1;
298 }
299 
300 
301 DEVICE_ACCESS(sgi_ip30_4)
302 {
303  struct sgi_ip30_data *d = (struct sgi_ip30_data *) extra;
304  uint64_t idata = 0, odata = 0;
305 
306  idata = memory_readmax64(cpu, data, len);
307 
308  switch (relative_addr) {
309 
310  case 0x000b0:
311  /*
312  * If this is not implemented, the IP30 PROM complains during
313  * bootup:
314  *
315  * *FAILED*
316  * Address: 0xffffffffbf6000b0, Expected:
317  * 0x0000000000000001, Received: 0x0000000000000000
318  */
319  if (writeflag == MEM_WRITE) {
320  d->reg_0x000b0 = idata;
321  } else {
322  odata = d->reg_0x000b0;
323  }
324  break;
325 
326  default:
327  if (writeflag == MEM_WRITE) {
328  debug("[ sgi_ip30_4: unimplemented write to address"
329  " 0x%x, data=0x%02x ]\n",
330  (int)relative_addr, (int)idata);
331  } else {
332  debug("[ sgi_ip30_4: unimplemented read from address"
333  " 0x%x ]\n", (int)relative_addr);
334  }
335  }
336 
337  if (writeflag == MEM_READ)
338  memory_writemax64(cpu, data, len, odata);
339 
340  return 1;
341 }
342 
343 
344 DEVICE_ACCESS(sgi_ip30_5)
345 {
346  struct sgi_ip30_data *d = (struct sgi_ip30_data *) extra;
347  uint64_t idata = 0, odata = 0;
348 
349  idata = memory_readmax64(cpu, data, len);
350 
351  switch (relative_addr) {
352 
353  case 0x00000:
354  if (writeflag == MEM_WRITE) {
355  d->reg_0x00000 = idata;
356  } else {
357  odata = d->reg_0x00000;
358  }
359  break;
360 
361  default:
362  if (writeflag == MEM_WRITE) {
363  debug("[ sgi_ip30_5: unimplemented write to address "
364  "0x%x, data=0x%02x ]\n", (int)relative_addr,
365  (int)idata);
366  } else {
367  debug("[ sgi_ip30_5: unimplemented read from address "
368  "0x%x ]\n", (int)relative_addr);
369  }
370  }
371 
372  if (writeflag == MEM_READ)
373  memory_writemax64(cpu, data, len, odata);
374 
375  return 1;
376 }
377 
378 
379 DEVINIT(sgi_ip30)
380 {
381  struct sgi_ip30_data *d;
382 
383  CHECK_ALLOCATION(d = (struct sgi_ip30_data *) malloc(sizeof(struct sgi_ip30_data)));
384  memset(d, 0, sizeof(struct sgi_ip30_data));
385 
387  devinit->addr, DEV_SGI_IP30_LENGTH, dev_sgi_ip30_access, (void *)d,
388  DM_DEFAULT, NULL);
389  memory_device_register(devinit->machine->memory, "sgi_ip30_2",
390  0x10000000, 0x10000, dev_sgi_ip30_2_access, (void *)d, DM_DEFAULT,
391  NULL);
393  0x1f000000, 0x10000, dev_sgi_ip30_3_access, (void *)d, DM_DEFAULT,
394  NULL);
396  0x1f600000, 0x10000, dev_sgi_ip30_4_access, (void *)d, DM_DEFAULT,
397  NULL);
399  0x1f6c0000, 0x10000, dev_sgi_ip30_5_access, (void *)d, DM_DEFAULT,
400  NULL);
401 
403  dev_sgi_ip30_tick, d, 16);
404 
405  return 1;
406 }
407 
uint64_t memory_readmax64(struct cpu *cpu, unsigned char *buf, int len)
Definition: memory.cc:55
void fatal(const char *fmt,...)
Definition: main.cc:152
#define DM_DEFAULT
Definition: memory.h:130
DEVINIT(sgi_ip30)
uint64_t reg_0x30000
Definition: dev_sgi_ip30.cc:52
DEVICE_ACCESS(sgi_ip30)
Definition: dev_sgi_ip30.cc:84
uint64_t reg_0x00000
Definition: dev_sgi_ip30.cc:64
#define MEM_READ
Definition: memory.h:116
uint64_t imask0
Definition: dev_sgi_ip30.cc:48
struct memory * memory
Definition: machine.h:126
#define CHECK_ALLOCATION(ptr)
Definition: misc.h:239
uint64_t reg_0x00284
Definition: dev_sgi_ip30.cc:58
u_short data
Definition: siireg.h:79
uint64_t reg_0x20000
Definition: dev_sgi_ip30.cc:51
#define MEM_WRITE
Definition: memory.h:117
Definition: device.h:40
DEVICE_TICK(sgi_ip30)
Definition: dev_sgi_ip30.cc:68
#define debug
Definition: dev_adb.cc:57
Definition: cpu.h:326
struct machine * machine
Definition: device.h:41
uint64_t isr
Definition: dev_sgi_ip30.cc:50
void memory_writemax64(struct cpu *cpu, unsigned char *buf, int len, uint64_t data)
Definition: memory.cc:89
#define DEV_SGI_IP30_LENGTH
Definition: dev_sgi_ip30.cc:44
void memory_device_register(struct memory *mem, const char *, uint64_t baseaddr, uint64_t len, int(*f)(struct cpu *, struct memory *, uint64_t, unsigned char *, size_t, int, void *), void *extra, int flags, unsigned char *dyntrans_data)
Definition: memory.cc:339
uint64_t addr
Definition: device.h:46
void machine_add_tickfunction(struct machine *machine, void(*func)(struct cpu *, void *), void *extra, int clockshift)
Definition: machine.cc:280
uint64_t reg_0x000b0
Definition: dev_sgi_ip30.cc:61
uint64_t reg_0x0029c
Definition: dev_sgi_ip30.cc:55
uint64_t reg_0x10018
Definition: dev_sgi_ip30.cc:49

Generated on Sun Sep 30 2018 16:05:18 for GXemul by doxygen 1.8.13