AddressDataBus Class Reference

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AddressDataBus Class Referenceabstract

An interface for implementing components that read/write data via an address bus. More...

#include <AddressDataBus.h>

Inheritance diagram for AddressDataBus:
CacheComponent CPUComponent MainbusComponent RAMComponent CPUDyntransComponent I960_CPUComponent M88K_CPUComponent MIPS_CPUComponent

Public Member Functions

 AddressDataBus ()
 Constructs an AddressDataBus instance. More...
 
virtual ~AddressDataBus ()
 
virtual void AddressSelect (uint64_t address)=0
 Place an address on the bus. More...
 
virtual bool ReadData (uint8_t &data, Endianness endianness=BigEndian)=0
 Reads 8-bit data from the currently selected address. More...
 
virtual bool ReadData (uint16_t &data, Endianness endianness)=0
 Reads 16-bit data from the currently selected address. More...
 
virtual bool ReadData (uint32_t &data, Endianness endianness)=0
 Reads 32-bit data from the currently selected address. More...
 
virtual bool ReadData (uint64_t &data, Endianness endianness)=0
 Reads 64-bit data from the currently selected address. More...
 
virtual bool WriteData (const uint8_t &data, Endianness endianness=BigEndian)=0
 Writes 8-bit data to the currently selected address. More...
 
virtual bool WriteData (const uint16_t &data, Endianness endianness)=0
 Writes 16-bit data to the currently selected address. More...
 
virtual bool WriteData (const uint32_t &data, Endianness endianness)=0
 Writes 32-bit data to the currently selected address. More...
 
virtual bool WriteData (const uint64_t &data, Endianness endianness)=0
 Writes 64-bit data to the currently selected address. More...
 

Detailed Description

An interface for implementing components that read/write data via an address bus.

Any component which allows data to be read or written by using an address as an index/offset should implement this interface.

A typical example of a Component which implements the functions of this class is the RAMComponent.

Definition at line 44 of file AddressDataBus.h.

Constructor & Destructor Documentation

◆ AddressDataBus()

AddressDataBus::AddressDataBus ( )
inline

Constructs an AddressDataBus instance.

Definition at line 50 of file AddressDataBus.h.

◆ ~AddressDataBus()

virtual AddressDataBus::~AddressDataBus ( )
inlinevirtual

Definition at line 52 of file AddressDataBus.h.

References AddressSelect(), BigEndian, data, ReadData(), and WriteData().

Member Function Documentation

◆ AddressSelect()

virtual void AddressDataBus::AddressSelect ( uint64_t  address)
pure virtual

◆ ReadData() [1/4]

virtual bool AddressDataBus::ReadData ( uint8_t &  data,
Endianness  endianness = BigEndian 
)
pure virtual

Reads 8-bit data from the currently selected address.

Parameters
dataA reference to a variable which will receive the data.
endiannessSelects the endianness of the operation. Ignored for 8-bit reads and writes.
Returns
True if the access was successful, false otherwise (e.g. because of a timeout).

Implemented in RAMComponent, CacheComponent, CPUComponent, and MainbusComponent.

Referenced by FileLoader::Load(), MainbusComponent::ReadData(), CPUComponent::ReadData(), MainbusComponent::WriteData(), RAMComponent::WriteData(), and ~AddressDataBus().

◆ ReadData() [2/4]

virtual bool AddressDataBus::ReadData ( uint16_t &  data,
Endianness  endianness 
)
pure virtual

Reads 16-bit data from the currently selected address.

Parameters
dataA reference to a variable which will receive the data.
endiannessSelects the endianness of the operation.
Returns
True if the access was successful, false otherwise (e.g. because of a timeout).

Implemented in RAMComponent, CacheComponent, CPUComponent, and MainbusComponent.

◆ ReadData() [3/4]

virtual bool AddressDataBus::ReadData ( uint32_t &  data,
Endianness  endianness 
)
pure virtual

Reads 32-bit data from the currently selected address.

Parameters
dataA reference to a variable which will receive the data.
endiannessSelects the endianness of the operation.
Returns
True if the access was successful, false otherwise (e.g. because of a timeout).

Implemented in RAMComponent, CacheComponent, CPUComponent, and MainbusComponent.

◆ ReadData() [4/4]

virtual bool AddressDataBus::ReadData ( uint64_t &  data,
Endianness  endianness 
)
pure virtual

Reads 64-bit data from the currently selected address.

Parameters
dataA reference to a variable which will receive the data.
endiannessSelects the endianness of the operation.
Returns
True if the access was successful, false otherwise (e.g. because of a timeout).

Implemented in RAMComponent, CacheComponent, CPUComponent, and MainbusComponent.

◆ WriteData() [1/4]

virtual bool AddressDataBus::WriteData ( const uint8_t &  data,
Endianness  endianness = BigEndian 
)
pure virtual

Writes 8-bit data to the currently selected address.

Parameters
dataA reference to a variable which contains the data.
endiannessSelects the endianness of the operation. Ignored for 8-bit reads and writes.
Returns
True if the access was successful, false otherwise (e.g. because of a timeout).

Implemented in RAMComponent, CacheComponent, CPUComponent, and MainbusComponent.

Referenced by DYNTRANS_INSTR(), FileLoader_raw::LoadIntoComponent(), MainbusComponent::WriteData(), CPUComponent::WriteData(), RAMComponent::WriteData(), and ~AddressDataBus().

◆ WriteData() [2/4]

virtual bool AddressDataBus::WriteData ( const uint16_t &  data,
Endianness  endianness 
)
pure virtual

Writes 16-bit data to the currently selected address.

Parameters
dataA reference to a variable which contains the data.
endiannessSelects the endianness of the operation.
Returns
True if the access was successful, false otherwise (e.g. because of a timeout).

Implemented in RAMComponent, CacheComponent, CPUComponent, and MainbusComponent.

◆ WriteData() [3/4]

virtual bool AddressDataBus::WriteData ( const uint32_t &  data,
Endianness  endianness 
)
pure virtual

Writes 32-bit data to the currently selected address.

Parameters
dataA reference to a variable which contains the data.
endiannessSelects the endianness of the operation.
Returns
True if the access was successful, false otherwise (e.g. because of a timeout).

Implemented in RAMComponent, CacheComponent, CPUComponent, and MainbusComponent.

◆ WriteData() [4/4]

virtual bool AddressDataBus::WriteData ( const uint64_t &  data,
Endianness  endianness 
)
pure virtual

Writes 64-bit data to the currently selected address.

Parameters
dataA reference to a variable which contains the data.
endiannessSelects the endianness of the operation.
Returns
True if the access was successful, false otherwise (e.g. because of a timeout).

Implemented in RAMComponent, CacheComponent, CPUComponent, and MainbusComponent.


The documentation for this class was generated from the following file:

Generated on Sun Sep 30 2018 16:05:18 for GXemul by doxygen 1.8.13