cpu_mips_instr_loadstore.cc Source File

Back to the index.

cpu_mips_instr_loadstore.cc
Go to the documentation of this file.
1 /*
2  * Copyright (C) 2006-2009 Anders Gavare. All rights reserved.
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions are met:
6  *
7  * 1. Redistributions of source code must retain the above copyright
8  * notice, this list of conditions and the following disclaimer.
9  * 2. Redistributions in binary form must reproduce the above copyright
10  * notice, this list of conditions and the following disclaimer in the
11  * documentation and/or other materials provided with the distribution.
12  * 3. The name of the author may not be used to endorse or promote products
13  * derived from this software without specific prior written permission.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25  * SUCH DAMAGE.
26  *
27  *
28  * MIPS load/store instructions; the following args are used:
29  *
30  * arg[0] = pointer to the register to load to or store from
31  * arg[1] = pointer to the base register
32  * arg[2] = offset (as an int32_t)
33  *
34  * The GENERIC function always checks for alignment, and supports both big
35  * and little endian byte order.
36  *
37  * The quick function is included twice (big/little endian) for each
38  * GENERIC function.
39  */
40 
41 
42 #ifdef LS_INCLUDE_GENERIC
43 void LS_GENERIC_N(struct cpu *cpu, struct mips_instr_call *ic)
44 {
45  MODE_int_t addr = reg(ic->arg[1]) + (int32_t)ic->arg[2];
46  uint8_t data[LS_SIZE];
47 #ifdef LS_LOAD
48  uint64_t x;
49 #endif
50 
51  /* Synchronize the PC: */
52  int low_pc = ((size_t)ic - (size_t)cpu->cd.mips.cur_ic_page)
53  / sizeof(struct mips_instr_call);
55  cpu->pc += (low_pc << MIPS_INSTR_ALIGNMENT_SHIFT);
56 
57 #ifndef LS_1
58  /* Check alignment: */
59  if (addr & (LS_SIZE - 1)) {
60 #if 1
61  /* Cause an address alignment exception: */
63 #ifdef LS_LOAD
65 #else
67 #endif
68  0, addr, 0, 0, 0, 0);
69 #else
70  fatal("{ mips dyntrans alignment exception, size = %i,"
71  " addr = %016"PRIx64", pc = %016"PRIx64" }\n", LS_SIZE,
72  (uint64_t) addr, cpu->pc);
73 
74  /* TODO: Generalize this into a abort_call, or similar: */
75  cpu->running = 0;
77  cpu->cd.mips.next_ic = &nothing_call;
78 #endif
79  return;
80  }
81 #endif
82 
83 #ifdef LS_LOAD
84  if (!cpu->memory_rw(cpu, cpu->mem, addr, data, sizeof(data),
85  MEM_READ, CACHE_DATA)) {
86  /* Exception. */
87  return;
88  }
89  x = memory_readmax64(cpu, data, LS_SIZE);
90 #ifdef LS_SIGNED
91 #ifdef LS_1
92  x = (int8_t)x;
93 #endif
94 #ifdef LS_2
95  x = (int16_t)x;
96 #endif
97 #ifdef LS_4
98  x = (int32_t)x;
99 #endif
100 #endif
101  reg(ic->arg[0]) = x;
102 #else /* LS_STORE: */
103  memory_writemax64(cpu, data, LS_SIZE, reg(ic->arg[0]));
104  if (!cpu->memory_rw(cpu, cpu->mem, addr, data, sizeof(data),
105  MEM_WRITE, CACHE_DATA)) {
106  /* Exception. */
107  return;
108  }
109 #endif
110 }
111 #endif /* LS_INCLUDE_GENERIC */
112 
113 
114 void LS_N(struct cpu *cpu, struct mips_instr_call *ic)
115 {
116  MODE_uint_t addr = reg(ic->arg[1]) + (int32_t)ic->arg[2];
117  unsigned char *p;
118 #ifdef MODE32
119 #ifdef LS_LOAD
120  p = cpu->cd.mips.host_load[addr >> 12];
121 #else
122  p = cpu->cd.mips.host_store[addr >> 12];
123 #endif
124 #else /* !MODE32 */
125  const uint32_t mask1 = (1 << DYNTRANS_L1N) - 1;
126  const uint32_t mask2 = (1 << DYNTRANS_L2N) - 1;
127  const uint32_t mask3 = (1 << DYNTRANS_L3N) - 1;
128  uint32_t x1, x2, x3;
129  struct DYNTRANS_L2_64_TABLE *l2;
130  struct DYNTRANS_L3_64_TABLE *l3;
131 
132  x1 = (addr >> (64-DYNTRANS_L1N)) & mask1;
133  x2 = (addr >> (64-DYNTRANS_L1N-DYNTRANS_L2N)) & mask2;
134  x3 = (addr >> (64-DYNTRANS_L1N-DYNTRANS_L2N-DYNTRANS_L3N)) & mask3;
135  /* fatal("X3: addr=%016"PRIx64" x1=%x x2=%x x3=%x\n",
136  (uint64_t) addr, (int) x1, (int) x2, (int) x3); */
137  l2 = cpu->cd.DYNTRANS_ARCH.l1_64[x1];
138  /* fatal(" l2 = %p\n", l2); */
139  l3 = l2->l3[x2];
140  /* fatal(" l3 = %p\n", l3); */
141 #ifdef LS_LOAD
142  p = l3->host_load[x3];
143 #else
144  p = l3->host_store[x3];
145 #endif
146  /* fatal(" p = %p\n", p); */
147 #endif
148 
149  if (p == NULL
150 #ifndef LS_1
151  || addr & (LS_SIZE - 1)
152 #endif
153  ) {
154  LS_GENERIC_N(cpu, ic);
155  return;
156  }
157 
158  addr &= 0xfff;
159 
160 #ifdef LS_LOAD
161  /* Load: */
162 
163 #ifdef LS_1
164  reg(ic->arg[0]) =
165 #ifdef LS_SIGNED
166  (int8_t)
167 #endif
168  p[addr];
169 #endif /* LS_1 */
170 
171 #ifdef LS_2
172  reg(ic->arg[0]) =
173 #ifdef LS_SIGNED
174  (int16_t)
175 #endif
176 #ifdef LS_BE
177 #ifdef HOST_BIG_ENDIAN
178  ( *(uint16_t *)(p + addr) );
179 #else
180  ((p[addr]<<8) + p[addr+1]);
181 #endif
182 #else
183 #ifdef HOST_LITTLE_ENDIAN
184  ( *(uint16_t *)(p + addr) );
185 #else
186  (p[addr] + (p[addr+1]<<8));
187 #endif
188 #endif
189 #endif /* LS_2 */
190 
191 #ifdef LS_4
192  reg(ic->arg[0]) =
193 #ifdef LS_SIGNED
194  (int32_t)
195 #else
196  (uint32_t)
197 #endif
198 #ifdef LS_BE
199 #ifdef HOST_BIG_ENDIAN
200  ( *(uint32_t *)(p + addr) );
201 #else
202  ((p[addr]<<24) + (p[addr+1]<<16) + (p[addr+2]<<8) + p[addr+3]);
203 #endif
204 #else
205 #ifdef HOST_LITTLE_ENDIAN
206  ( *(uint32_t *)(p + addr) );
207 #else
208  (p[addr] + (p[addr+1]<<8) + (p[addr+2]<<16) + (p[addr+3]<<24));
209 #endif
210 #endif
211 #endif /* LS_4 */
212 
213 #ifdef LS_8
214  *((uint64_t *)ic->arg[0]) =
215 #ifdef LS_BE
216 #ifdef HOST_BIG_ENDIAN
217  ( *(uint64_t *)(p + addr) );
218 #else
219  ((uint64_t)p[addr] << 56) + ((uint64_t)p[addr+1] << 48) +
220  ((uint64_t)p[addr+2] << 40) + ((uint64_t)p[addr+3] << 32) +
221  ((uint64_t)p[addr+4] << 24) +
222  (p[addr+5] << 16) + (p[addr+6] << 8) + p[addr+7];
223 #endif
224 #else
225 #ifdef HOST_LITTLE_ENDIAN
226  ( *(uint64_t *)(p + addr) );
227 #else
228  p[addr+0] + (p[addr+1] << 8) + (p[addr+2] << 16) +
229  ((uint64_t)p[addr+3] << 24) + ((uint64_t)p[addr+4] << 32) +
230  ((uint64_t)p[addr+5] << 40) + ((uint64_t)p[addr+6] << 48) +
231  ((uint64_t)p[addr+7] << 56);
232 #endif
233 #endif
234 #endif /* LS_8 */
235 
236 #else
237  /* Store: */
238 
239 #ifdef LS_1
240  p[addr] = reg(ic->arg[0]);
241 #endif
242 #ifdef LS_2
243  { uint32_t x = reg(ic->arg[0]);
244 #ifdef LS_BE
245 #ifdef HOST_BIG_ENDIAN
246  *((uint16_t *)(p+addr)) = x; }
247 #else
248  p[addr] = x >> 8; p[addr+1] = x; }
249 #endif
250 #else
251 #ifdef HOST_LITTLE_ENDIAN
252  *((uint16_t *)(p+addr)) = x; }
253 #else
254  p[addr] = x; p[addr+1] = x >> 8; }
255 #endif
256 #endif
257 #endif /* LS_2 */
258 #ifdef LS_4
259  { uint32_t x = reg(ic->arg[0]);
260 #ifdef LS_BE
261 #ifdef HOST_BIG_ENDIAN
262  *((uint32_t *)(p+addr)) = x; }
263 #else
264  p[addr] = x >> 24; p[addr+1] = x >> 16;
265  p[addr+2] = x >> 8; p[addr+3] = x; }
266 #endif
267 #else
268 #ifdef HOST_LITTLE_ENDIAN
269  *((uint32_t *)(p+addr)) = x; }
270 #else
271  p[addr] = x; p[addr+1] = x >> 8;
272  p[addr+2] = x >> 16; p[addr+3] = x >> 24; }
273 #endif
274 #endif
275 #endif /* LS_4 */
276 #ifdef LS_8
277  { uint64_t x = *(uint64_t *)(ic->arg[0]);
278 #ifdef LS_BE
279 #ifdef HOST_BIG_ENDIAN
280  *((uint64_t *)(p+addr)) = x; }
281 #else
282  p[addr] = x >> 56; p[addr+1] = x >> 48; p[addr+2] = x >> 40;
283  p[addr+3] = x >> 32; p[addr+4] = x >> 24; p[addr+5] = x >> 16;
284  p[addr+6] = x >> 8; p[addr+7] = x; }
285 #endif
286 #else
287 #ifdef HOST_LITTLE_ENDIAN
288  *((uint64_t *)(p+addr)) = x; }
289 #else
290  p[addr] = x; p[addr+1] = x >> 8; p[addr+2] = x >> 16;
291  p[addr+3] = x >> 24; p[addr+4] = x >> 32; p[addr+5] = x >> 40;
292  p[addr+6] = x >> 48; p[addr+7] = x >> 56; }
293 #endif
294 #endif
295 #endif /* LS_8 */
296 
297 #endif /* store */
298 }
299 
#define EXCEPTION_ADEL
Definition: cop0.h:187
#define LS_SIZE
uint64_t memory_readmax64(struct cpu *cpu, unsigned char *buf, int len)
Definition: memory.cc:55
void fatal(const char *fmt,...)
Definition: main.cc:152
#define CACHE_DATA
Definition: memory.h:121
#define MODE_uint_t
#define EXCEPTION_ADES
Definition: cop0.h:188
struct arm_instr_call * ic
union cpu::@1 cd
struct memory * mem
Definition: cpu.h:362
#define LS_BE
#define LS_1
#define MEM_READ
Definition: memory.h:116
#define DYNTRANS_L2_64_TABLE
void LS_N(struct cpu *cpu, struct mips_instr_call *ic)
#define LS_LOAD
#define reg(x)
int debugger_n_steps_left_before_interaction
Definition: debugger.cc:73
#define MIPS_INSTR_ALIGNMENT_SHIFT
Definition: cpu_mips.h:189
uint64_t pc
Definition: cpu.h:383
int(* memory_rw)(struct cpu *cpu, struct memory *mem, uint64_t vaddr, unsigned char *data, size_t len, int writeflag, int cache_flags)
Definition: cpu.h:365
#define DYNTRANS_L2N
u_short data
Definition: siireg.h:79
void LS_GENERIC_N(struct cpu *cpu, struct ppc_instr_call *ic)
uint8_t running
Definition: cpu.h:353
void mips_cpu_exception(struct cpu *cpu, int exccode, int tlb, uint64_t vaddr, int coproc_nr, uint64_t vaddr_vpn2, int vaddr_asid, int x_64)
Definition: cpu_mips.cc:1714
#define MEM_WRITE
Definition: memory.h:117
uint32_t addr
Definition: cpu.h:326
#define MODE_int_t
#define DYNTRANS_L1N
Definition: cpu.h:222
void memory_writemax64(struct cpu *cpu, unsigned char *buf, int len, uint64_t data)
Definition: memory.cc:89
#define DYNTRANS_L3N
struct mips_cpu mips
Definition: cpu.h:443
#define DYNTRANS_L3_64_TABLE
#define MIPS_IC_ENTRIES_PER_PAGE
Definition: cpu_mips.h:190

Generated on Sun Sep 30 2018 16:05:18 for GXemul by doxygen 1.8.13