sh4_exception.h Source File

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sh4_exception.h
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1 /* $NetBSD: exception.h,v 1.8 2006/03/04 01:55:03 uwe Exp $ */
2 
3 /*-
4  * Copyright (c) 2002 The NetBSD Foundation, Inc.
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  * notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  * notice, this list of conditions and the following disclaimer in the
14  * documentation and/or other materials provided with the distribution.
15  * 3. All advertising materials mentioning features or use of this software
16  * must display the following acknowledgement:
17  * This product includes software developed by the NetBSD
18  * Foundation, Inc. and its contributors.
19  * 4. Neither the name of The NetBSD Foundation nor the names of its
20  * contributors may be used to endorse or promote products derived
21  * from this software without specific prior written permission.
22  *
23  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
24  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
25  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
26  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
27  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
33  * POSSIBILITY OF SUCH DAMAGE.
34  */
35 
36 #ifndef _SH3_EXCEPTION_H_
37 #define _SH3_EXCEPTION_H_
38 /*
39  * SH3/SH4 Exception handling.
40  */
41 /* #include <sh3/devreg.h> */
42 
43 /* #ifdef _KERNEL */
44 #define SH3_TRA 0xffffffd0 /* 32bit */
45 #define SH3_EXPEVT 0xffffffd4 /* 32bit */
46 #define SH3_INTEVT 0xffffffd8 /* 32bit */
47 #define SH7709_INTEVT2 0xa4000000 /* 32bit */
48 
49 #define SH4_TRA 0xff000020 /* 32bit */
50 #define SH4_EXPEVT 0xff000024 /* 32bit */
51 #define SH4_INTEVT 0xff000028 /* 32bit */
52 
53 /*
54  * EXPEVT
55  */
56 /* Reset exception */
57 #define EXPEVT_RESET_POWER 0x000 /* Power-On reset */
58 #define EXPEVT_RESET_MANUAL 0x020 /* Manual reset */
59 #define EXPEVT_RESET_TLB_MULTI_HIT 0x140 /* SH4 only */
60 
61 /* General exception */
62 #define EXPEVT_TLB_MISS_LD 0x040 /* TLB miss (load) */
63 #define EXPEVT_TLB_MISS_ST 0x060 /* TLB miss (store) */
64 #define EXPEVT_TLB_MOD 0x080 /* Initial page write */
65 #define EXPEVT_TLB_PROT_LD 0x0a0 /* Protection violation (load) */
66 #define EXPEVT_TLB_PROT_ST 0x0c0 /* Protection violation (store)*/
67 #define EXPEVT_ADDR_ERR_LD 0x0e0 /* Address error (load) */
68 #define EXPEVT_ADDR_ERR_ST 0x100 /* Address error (store) */
69 #define EXPEVT_FPU 0x120 /* FPU exception */
70 #define EXPEVT_TRAPA 0x160 /* Unconditional trap (TRAPA) */
71 #define EXPEVT_RES_INST 0x180 /* Illegal instruction */
72 #define EXPEVT_SLOT_INST 0x1a0 /* Illegal slot instruction */
73 #define EXPEVT_BREAK 0x1e0 /* User break */
74 #define EXPEVT_FPU_DISABLE 0x800 /* FPU disabled */
75 #define EXPEVT_FPU_SLOT_DISABLE 0x820 /* Slot FPU disabled */
76 
77 /* Software bit */
78 #define EXP_USER 0x001 /* exception from user-mode */
79 
80 #define _SH_TRA_BREAK 0xc3 /* magic number for debugger */
81 
82 /*
83  * INTEVT/INTEVT2
84  */
85 /* External interrupt */
86 #define SH_INTEVT_NMI 0x1c0
87 
88 #define SH_INTEVT_TMU0_TUNI0 0x400
89 #define SH_INTEVT_TMU1_TUNI1 0x420
90 #define SH_INTEVT_TMU2_TUNI2 0x440
91 #define SH_INTEVT_TMU2_TICPI2 0x460
92 
93 #define SH_INTEVT_SCI_ERI 0x4e0
94 #define SH_INTEVT_SCI_RXI 0x500
95 #define SH_INTEVT_SCI_TXI 0x520
96 #define SH_INTEVT_SCI_TEI 0x540
97 
98 #define SH_INTEVT_WDT_ITI 0x560
99 
100 #define SH_INTEVT_IRL9 0x320
101 #define SH_INTEVT_IRL11 0x360
102 #define SH_INTEVT_IRL13 0x3a0
103 
104 #define SH4_INTEVT_SCIF_ERI 0x700
105 #define SH4_INTEVT_SCIF_RXI 0x720
106 #define SH4_INTEVT_SCIF_BRI 0x740
107 #define SH4_INTEVT_SCIF_TXI 0x760
108 
109 #define SH7709_INTEVT2_IRQ0 0x600
110 #define SH7709_INTEVT2_IRQ1 0x620
111 #define SH7709_INTEVT2_IRQ2 0x640
112 #define SH7709_INTEVT2_IRQ3 0x660
113 #define SH7709_INTEVT2_IRQ4 0x680
114 #define SH7709_INTEVT2_IRQ5 0x6a0
115 
116 #define SH7709_INTEVT2_PINT07 0x700
117 #define SH7709_INTEVT2_PINT8F 0x720
118 
119 #define SH7709_INTEVT2_DEI0 0x800
120 #define SH7709_INTEVT2_DEI1 0x820
121 #define SH7709_INTEVT2_DEI2 0x840
122 #define SH7709_INTEVT2_DEI3 0x860
123 
124 #define SH7709_INTEVT2_IRDA_ERI 0x880
125 #define SH7709_INTEVT2_IRDA_RXI 0x8a0
126 #define SH7709_INTEVT2_IRDA_BRI 0x8c0
127 #define SH7709_INTEVT2_IRDA_TXI 0x8e0
128 
129 #define SH7709_INTEVT2_SCIF_ERI 0x900
130 #define SH7709_INTEVT2_SCIF_RXI 0x920
131 #define SH7709_INTEVT2_SCIF_BRI 0x940
132 #define SH7709_INTEVT2_SCIF_TXI 0x960
133 
134 #define SH7709_INTEVT2_ADC 0x980
135 
136 /* SH7750R, SH7751, SH7751R */
137 #define SH4_INTEVT_IRL0 0x240
138 #define SH4_INTEVT_IRL1 0x2a0
139 #define SH4_INTEVT_IRL2 0x300
140 #define SH4_INTEVT_IRL3 0x360
141 
142 #define SH4_INTEVT_IRQ0 0x200
143 #define SH4_INTEVT_IRQ1 0x220
144 #define SH4_INTEVT_IRQ2 0x240
145 #define SH4_INTEVT_IRQ3 0x260
146 #define SH4_INTEVT_IRQ4 0x280
147 #define SH4_INTEVT_IRQ5 0x2a0
148 #define SH4_INTEVT_IRQ6 0x2c0
149 #define SH4_INTEVT_IRQ7 0x2e0
150 #define SH4_INTEVT_IRQ8 0x300
151 #define SH4_INTEVT_IRQ9 0x320
152 #define SH4_INTEVT_IRQ10 0x340
153 #define SH4_INTEVT_IRQ11 0x360
154 #define SH4_INTEVT_IRQ12 0x380
155 #define SH4_INTEVT_IRQ13 0x3a0
156 #define SH4_INTEVT_IRQ14 0x3c0
157 #define SH4_INTEVT_IRQ15 0x3e0
158 
159 #define SH4_INTEVT_TMU3 0xb00
160 #define SH4_INTEVT_TMU4 0xb80
161 
162 #define SH4_INTEVT_PCISERR 0xa00
163 #define SH4_INTEVT_PCIERR 0xae0
164 #define SH4_INTEVT_PCIPWDWN 0xac0
165 #define SH4_INTEVT_PCIPWON 0xaa0
166 #define SH4_INTEVT_PCIDMA0 0xa80
167 #define SH4_INTEVT_PCIDMA1 0xa60
168 #define SH4_INTEVT_PCIDMA2 0xa40
169 #define SH4_INTEVT_PCIDMA3 0xa20
170 
171 #ifndef _LOCORE
172 #if defined(SH3) && defined(SH4)
173 extern uint32_t __sh_TRA;
174 extern uint32_t __sh_EXPEVT;
175 extern uint32_t __sh_INTEVT;
176 #endif /* SH3 && SH4 */
177 #endif /* !_LOCORE */
178 /* #endif KERNEL */
179 #endif /* !_SH3_EXCEPTION_H_ */

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