dev_m8820x.cc Source File

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dev_m8820x.cc
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1 /*
2  * Copyright (C) 2007-2009 Anders Gavare. All rights reserved.
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions are met:
6  *
7  * 1. Redistributions of source code must retain the above copyright
8  * notice, this list of conditions and the following disclaimer.
9  * 2. Redistributions in binary form must reproduce the above copyright
10  * notice, this list of conditions and the following disclaimer in the
11  * documentation and/or other materials provided with the distribution.
12  * 3. The name of the author may not be used to endorse or promote products
13  * derived from this software without specific prior written permission.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25  * SUCH DAMAGE.
26  *
27  *
28  * COMMENT: M88200/M88204 CMMU (Cache/Memory Management Unit)
29  */
30 
31 #include <stdio.h>
32 #include <stdlib.h>
33 #include <string.h>
34 
35 #include "cpu.h"
36 #include "device.h"
37 #include "emul.h"
38 #include "machine.h"
39 #include "memory.h"
40 #include "misc.h"
41 
42 #include "thirdparty/m8820x.h"
43 #include "thirdparty/m8820x_pte.h"
44 
45 
46 struct m8820x_data {
47  int cmmu_nr;
48 };
49 
50 
51 /*
52  * m8820x_command():
53  *
54  * Handle M8820x commands written to the System Command Register.
55  */
56 static void m8820x_command(struct cpu *cpu, struct m8820x_data *d)
57 {
58  uint32_t *regs = cpu->cd.m88k.cmmu[d->cmmu_nr]->reg;
59  int cmd = regs[CMMU_SCR];
60  uint32_t sar = regs[CMMU_SAR];
61  size_t i;
62  uint32_t super, all;
63 
64  switch (cmd) {
65 
75  /* TODO */
76  break;
77 
82  /* TODO: Segment invalidation. */
83 
84  all = super = 0;
85  if (cmd == CMMU_FLUSH_USER_ALL ||
86  cmd == CMMU_FLUSH_SUPER_ALL)
87  all = 1;
88  if (cmd == CMMU_FLUSH_SUPER_ALL ||
89  cmd == CMMU_FLUSH_SUPER_PAGE)
91 
92  /* TODO: Don't invalidate EVERYTHING like this! */
94 
95  for (i=0; i<N_M88200_PATC_ENTRIES; i++) {
96  uint32_t v = cpu->cd.m88k.cmmu[d->cmmu_nr]
97  ->patc_v_and_control[i];
98  uint32_t p = cpu->cd.m88k.cmmu[d->cmmu_nr]
100 
101  /* Already invalid? Then skip this entry. */
102  if (!(v & PG_V))
103  continue;
104 
105  /* Super/user mismatch? Then skip the entry. */
106  if ((p & M8820X_PATC_SUPERVISOR_BIT) != super)
107  continue;
108 
109  /* If not all pages are to be invalidated, there
110  must be a virtual address match: */
111  if (!all && (sar & 0xfffff000) != (v & 0xfffff000))
112  continue;
113 
114  /* Finally, invalidate the entry: */
115  cpu->cd.m88k.cmmu[d->cmmu_nr]->patc_v_and_control[i]
116  = v & ~PG_V;
117  }
118 
119  break;
120 
121  default:
122  fatal("[ m8820x_command: FATAL ERROR! unimplemented "
123  "command 0x%02x ]\n", cmd);
124  exit(1);
125  }
126 }
127 
128 
130 {
131  uint64_t idata = 0, odata = 0;
132  struct m8820x_data *d = (struct m8820x_data *) extra;
133  uint32_t *regs = cpu->cd.m88k.cmmu[d->cmmu_nr]->reg;
134  uint32_t *batc = cpu->cd.m88k.cmmu[d->cmmu_nr]->batc;
135 
136  if (writeflag == MEM_WRITE)
137  idata = memory_readmax64(cpu, data, len);
138 
139  if (writeflag == MEM_READ)
140  odata = regs[relative_addr / sizeof(uint32_t)];
141 
142  switch (relative_addr / sizeof(uint32_t)) {
143 
144  case CMMU_IDR:
145  if (writeflag == MEM_WRITE) {
146  fatal("m8820x: write to CMMU_IDR: TODO\n");
147  exit(1);
148  }
149  break;
150 
151  case CMMU_SCR:
152  if (writeflag == MEM_READ) {
153  fatal("m8820x: read from CMMU_SCR: TODO\n");
154  exit(1);
155  } else {
156  regs[relative_addr / sizeof(uint32_t)] = idata;
157  m8820x_command(cpu, d);
158  }
159  break;
160 
161  case CMMU_SSR:
162  if (writeflag == MEM_WRITE) {
163  fatal("m8820x: write to CMMU_SSR: TODO\n");
164  exit(1);
165  }
166  break;
167 
168  case CMMU_PFSR:
169  case CMMU_PFAR:
170  case CMMU_SAR:
171  case CMMU_SCTR:
172  case CMMU_SAPR: /* TODO: Invalidate something for */
173  case CMMU_UAPR: /* SAPR and UAPR writes? */
174  /* TODO: Don't invalidate everything. */
176  if (writeflag == MEM_WRITE)
177  regs[relative_addr / sizeof(uint32_t)] = idata;
178  break;
179 
180  case CMMU_BWP0:
181  case CMMU_BWP1:
182  case CMMU_BWP2:
183  case CMMU_BWP3:
184  case CMMU_BWP4:
185  case CMMU_BWP5:
186  case CMMU_BWP6:
187  case CMMU_BWP7:
188  if (writeflag == MEM_WRITE) {
189  uint32_t old;
190  int i = (relative_addr / sizeof(uint32_t)) - CMMU_BWP0;
191 
192  regs[relative_addr / sizeof(uint32_t)] = idata;
193 
194  /* Also write to the specific batc registers: */
195  old = batc[i];
196  batc[i] = idata;
197  if (old != idata) {
198  /* TODO: Don't invalidate everything? */
200  cpu, 0, INVALIDATE_ALL);
201  }
202  }
203  break;
204 
205  case CMMU_CSSP0:
206  /* TODO: Actually care about cache details. */
207  break;
208 
209  default:fatal("[ m8820x: unimplemented %s offset 0x%x",
210  writeflag == MEM_WRITE? "write to" : "read from",
211  (int) relative_addr);
212  if (writeflag == MEM_WRITE)
213  fatal(": 0x%x", (int)idata);
214  fatal(" ]\n");
215  exit(1);
216  }
217 
218  if (writeflag == MEM_READ)
219  memory_writemax64(cpu, data, len, odata);
220 
221  return 1;
222 }
223 
224 
225 DEVINIT(m8820x)
226 {
227  struct m8820x_data *d;
228 
229  CHECK_ALLOCATION(d = (struct m8820x_data *) malloc(sizeof(struct m8820x_data)));
230  memset(d, 0, sizeof(struct m8820x_data));
231 
232  d->cmmu_nr = devinit->addr2;
233 
235  devinit->addr, M8820X_LENGTH, dev_m8820x_access, (void *)d,
236  DM_DEFAULT, NULL);
237 
238  return 1;
239 }
240 
uint64_t addr2
Definition: device.h:47
uint64_t memory_readmax64(struct cpu *cpu, unsigned char *buf, int len)
Definition: memory.cc:55
#define CMMU_SAR
Definition: m8820x.h:63
void fatal(const char *fmt,...)
Definition: main.cc:152
#define DM_DEFAULT
Definition: memory.h:130
DEVICE_ACCESS(m8820x)
Definition: dev_m8820x.cc:129
#define CMMU_BWP2
Definition: m8820x.h:71
#define CMMU_FLUSH_CACHE_CBI_SEGMENT
Definition: m8820x.h:104
#define CMMU_FLUSH_CACHE_CB_LINE
Definition: m8820x.h:98
#define INVALIDATE_ALL
Definition: cpu.h:478
uint32_t patc_v_and_control[N_M88200_PATC_ENTRIES]
char * name
Definition: device.h:43
union cpu::@1 cd
#define CMMU_FLUSH_USER_ALL
Definition: m8820x.h:111
#define MEM_READ
Definition: memory.h:116
struct memory * memory
Definition: machine.h:126
#define CMMU_BWP5
Definition: m8820x.h:74
#define CMMU_CSSP0
Definition: m8820x.h:86
#define PG_V
Definition: m8820x_pte.h:124
#define CMMU_FLUSH_CACHE_CB_PAGE
Definition: m8820x.h:99
uint32_t patc_p_and_supervisorbit[N_M88200_PATC_ENTRIES]
#define CMMU_FLUSH_CACHE_INV_PAGE
Definition: m8820x.h:95
#define CMMU_PFSR
Definition: m8820x.h:65
#define M8820X_LENGTH
#define CMMU_SCTR
Definition: m8820x.h:64
#define CMMU_BWP3
Definition: m8820x.h:72
#define CMMU_FLUSH_CACHE_INV_LINE
Definition: m8820x.h:94
#define CHECK_ALLOCATION(ptr)
Definition: misc.h:239
#define CMMU_SCR
Definition: m8820x.h:61
#define CMMU_SAPR
Definition: m8820x.h:67
u_short data
Definition: siireg.h:79
#define CMMU_FLUSH_SUPER_PAGE
Definition: m8820x.h:113
#define CMMU_FLUSH_USER_PAGE
Definition: m8820x.h:109
#define CMMU_FLUSH_CACHE_CBI_PAGE
Definition: m8820x.h:103
#define CMMU_SSR
Definition: m8820x.h:62
#define MEM_WRITE
Definition: memory.h:117
#define M8820X_PATC_SUPERVISOR_BIT
#define CMMU_IDR
Definition: m8820x.h:60
Definition: device.h:40
#define N_M88200_PATC_ENTRIES
#define CMMU_BWP1
Definition: m8820x.h:70
#define CMMU_BWP6
Definition: m8820x.h:75
Definition: cpu.h:326
struct machine * machine
Definition: device.h:41
#define CMMU_UAPR
Definition: m8820x.h:68
#define CMMU_BWP4
Definition: m8820x.h:73
void memory_writemax64(struct cpu *cpu, unsigned char *buf, int len, uint64_t data)
Definition: memory.cc:89
void memory_device_register(struct memory *mem, const char *, uint64_t baseaddr, uint64_t len, int(*f)(struct cpu *, struct memory *, uint64_t, unsigned char *, size_t, int, void *), void *extra, int flags, unsigned char *dyntrans_data)
Definition: memory.cc:339
DEVINIT(m8820x)
Definition: dev_m8820x.cc:225
#define CMMU_BWP7
Definition: m8820x.h:76
#define CMMU_PFAR
Definition: m8820x.h:66
#define CMMU_FLUSH_CACHE_INV_ALL
Definition: m8820x.h:97
uint32_t reg[M8820X_LENGTH/sizeof(uint32_t)]
#define CMMU_FLUSH_SUPER_ALL
Definition: m8820x.h:115
#define CMMU_FLUSH_CACHE_CBI_ALL
Definition: m8820x.h:105
uint64_t addr
Definition: device.h:46
struct m8820x_cmmu * cmmu[MAX_M8820X_CMMUS]
Definition: cpu_m88k.h:250
uint32_t batc[N_M88200_BATC_REGS]
struct m88k_cpu m88k
Definition: cpu.h:442
#define CMMU_FLUSH_CACHE_CBI_LINE
Definition: m8820x.h:102
#define CMMU_BWP0
Definition: m8820x.h:69
void(* invalidate_translation_caches)(struct cpu *, uint64_t paddr, int flags)
Definition: cpu.h:374

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