bcureg.h File Reference

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Macros
bcureg.h File Reference

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Macros

#define BCUCNT1_REG_W   0x000 /* BCU Control Register 1 */
 
#define BCUCNT1_ROMMASK   (1<<15) /* ROM SIZE (<= 4121,>= 4102) */
 
#define BCUCNT1_ROM64M   (1<<15) /* ROM SIZE 64Mbit*/
 
#define BCUCNT1_ROM32M   (0<<15) /* ROM SIZE 32Mbit*/
 
#define BCUCNT1_DRAMMASK   (1<<14) /* DRAM SIZE (<= 4121,>= 4102) */
 
#define BCUCNT1_DRAM64M   (1<<14) /* DRAM SIZE 64Mbit*/
 
#define BCUCNT1_DRAM32M   (0<<14) /* DRAM SIZE 32Mbit*/
 
#define BCUCNT1_ROMSMASK   (0x3<<14) /* ROM SIZE (=4181) */
 
#define BCUCNT1_ROMS64M   (0x2<<14) /* ROM SIZE 64Mbit */
 
#define BCUCNT1_ROMS32M   (0x1<<14) /* ROM SIZE 32Mbit */
 
#define BCUCNT1_ISAMLCD   (1<<13) /* ISAM/LCD 0x0a000000 to 0xaffffff(>= 4102) */
 
#define BCUCNT1_ISA   (1<<13) /* ISA memory space */
 
#define BCUCNT1_LCD   (0<<13) /* LCD space*/
 
#define BCUCNT1_PAGEMASK   (1<<12) /* Maximum burst access size for Page Rom (<= 4121,>= 4102) */
 
#define BCUCNT1_PAGE128   (1<<12) /* 128bit */
 
#define BCUCNT1_PAGE64   (0<<12) /* 64bit */
 
#define BCUCNT1_PAGESIZEMASK   (3<<12) /* PageROM PAGESIZE (= 4122, 4131) */
 
#define BCUCNT1_PASESIZE32   (2<<12) /* 32 byte */
 
#define BCUCNT1_PASESIZE16   (1<<12) /* 16 byte */
 
#define BCUCNT1_PASESIZE8   (0<<12) /* 8 byte */
 
#define BCUCNT1_PAGE2MASK   (1<<10) /* (<= 4131,>= 4102) */
 
#define BCUCNT1_PAGE2PAGE   (1<<10) /* Page ROM */
 
#define BCUCNT1_PAGE2ORD   (0<<10) /* Prginary ROM */
 
#define BCUCNT1_PAGE0MASK   (1<<8) /* (<= 4131,>= 4102) */
 
#define BCUCNT1_PAGE0PAGE   (1<<8) /* Page ROM */
 
#define BCUCNT1_PAGE0ORD   (0<<8) /* Prginary ROM */
 
#define BCUCNT1_REFMASK   (1<<7) /* DRAM refresh interval (= 4101) */
 
#define BCUCNT1_REF1024   (1<<7) /* 1024 cycles/128ms */
 
#define BCUCNT1_REF4096   (0<<7) /* 4096 cycles/128ms */
 
#define BCUCNT1_ROMWEN2   (1<<6) /* Enable Flash memory write ROM 2 (<= 4131,>= 4102) */
 
#define BCUCNT1_ROMWEN2EN   (1<<6) /* Enable */
 
#define BCUCNT1_ROMWEN2DS   (0<<6) /* Prohibit */
 
#define BCUCNT1_PAGEROM   (1<<6) /* Enable page ROM access (= 4101) */
 
#define BCUCNT1_PAGEROMEN   (1<<6) /* Page ROM */
 
#define BCUCNT1_PAGEROMDIS   (0<<6) /* not Page ROM */
 
#define BCUCNT1_ROMWEN   (1<<5) /* Enable Flash memory write ROM 0 (= 4101) */
 
#define BCUCNT1_ROMWENEN   (1<<5) /* Enable */
 
#define BCUCNT1_ROMWENDS   (0<<5) /* Prohibit */
 
#define BCUCNT1_ROMWEN0   (1<<4) /* Enable Flash memory write ROM 0 (<= 4131,>= 4102, =4181) */
 
#define BCUCNT1_ROMWEN0EN   (1<<4) /* Enable */
 
#define BCUCNT1_ROMWEN0DS   (0<<4) /* Prohibit */
 
#define BCUCNT1_SRFSTAT   (1<<4) /* DRAM refresh mode (= 4101) */
 
#define BCUCNT1_SRFSTATSRF   (1<<4) /* self refresh */
 
#define BCUCNT1_SRFSTATCBR   (0<<4) /* CBR refresh */
 
#define BCUCNT1_BCPUR   (1<<3) /* CPU bus cycle control (= 4101) */
 
#define BCUCNT1_BCPUREN   (1<<3) /* CPU bus cycle control enable */
 
#define BCUCNT1_BCPURDIS   (0<<3) /* CPU bus cycle control disable */
 
#define BCUCNT1_HLD   (1<<2) /* Bus hold enable (= 4122, 4131) */
 
#define BCUCNT1_HLDEN   (1<<2) /* enable */
 
#define BCUCNT1_HLDDIS   (1<<2) /* disable */
 
#define BCUCNT1_BUSHERR   (1<<1) /* Bus Timeout detection enable (<= 4121,>= 4102) */
 
#define BCUCNT1_BUSHERREN   (1<<1) /* Enable */
 
#define BCUCNT1_BUSHERRDS   (0<<1) /* Prohibit */
 
#define BCUCNT1_RTYPE   (0x3<<1) /* ROM type (=4181) */
 
#define BCUCNT1_RTOROM   (0<<1) /* Odinary ROM */
 
#define BCUCNT1_RTFLASH   (1<<1) /* flash ROM */
 
#define BCUCNT1_RTPAGEROM   (2<<1) /* Page ROM */
 
#define BCUCNT1_RSTOUT   (1) /* RSTOUT control bit */
 
#define BCUCNT1_RSTOUTH   (1) /* RSTOUT high level*/
 
#define BCUCNT1_RSTOUTL   (0) /* RSTOUT low level*/
 
#define BCUCNT2_REG_W   0x002 /* BCU Control Register 2 (<= 4121,>= 4102, =4181) */
 
#define BCUCNT2_GMODE   (1) /* LCD access control */
 
#define BCUCNT2_GMODENOM   (1) /* not invert LCD */
 
#define BCUCNT2_GMODEINV   (0) /* invert LCD */
 
#define BCUBR_REG_W   0x002 /* BCU Bus Restrain Register (= 4101) */
 
#define BCUROMSIZE_REG_W   0x004 /* ROM size setting register (= 4122, 4131) */
 
#define BCUROMSIZE_SIZE3   (7<<12) /* Bank3 size */
 
#define BCUROMSIZE_SIZE3_64   (5<<12) /* 64MB */
 
#define BCUROMSIZE_SIZE3_32   (4<<12) /* 32MB */
 
#define BCUROMSIZE_SIZE3_16   (3<<12) /* 16MB */
 
#define BCUROMSIZE_SIZE3_8   (2<<12) /* 8MB */
 
#define BCUROMSIZE_SIZE3_4   (1<<12) /* 4MB */
 
#define BCUROMSIZE_SIZE2   (7<<8) /* Bank2 size */
 
#define BCUROMSIZE_SIZE2_64   (5<<8) /* 64MB */
 
#define BCUROMSIZE_SIZE2_32   (4<<8) /* 32MB */
 
#define BCUROMSIZE_SIZE2_16   (3<<8) /* 16MB */
 
#define BCUROMSIZE_SIZE2_8   (2<<8) /* 8MB */
 
#define BCUROMSIZE_SIZE2_4   (1<<8) /* 4MB */
 
#define BCUROMSIZE_SIZE1   (7<<4) /* Bank1 size */
 
#define BCUROMSIZE_SIZE1_64   (5<<4) /* 64MB */
 
#define BCUROMSIZE_SIZE1_32   (4<<4) /* 32MB */
 
#define BCUROMSIZE_SIZE1_16   (3<<4) /* 16MB */
 
#define BCUROMSIZE_SIZE1_8   (2<<4) /* 8MB */
 
#define BCUROMSIZE_SIZE1_4   (1<<4) /* 4MB */
 
#define BCUROMSIZE_SIZE0   (7) /* Bank0 size */
 
#define BCUROMSIZE_SIZE0_64   (5) /* 64MB */
 
#define BCUROMSIZE_SIZE0_32   (4) /* 32MB */
 
#define BCUROMSIZE_SIZE0_16   (3) /* 16MB */
 
#define BCUROMSIZE_SIZE0_8   (2) /* 8MB */
 
#define BCUROMSIZE_SIZE0_4   (1) /* 4MB */
 
#define BCUBRCNT_REG_W   0x004 /* BCU Bus Restrain Count Register (= 4101) */
 
#define BCUROMSPEED_REG_W   0x006 /* BCU ROM Speed Register (=4122, 4131) */
 
#define BCUROMSPEED_PATIME   (0x3<<12) /* Page Access time */
 
#define BCUROMSPEED_PATIME_5VT   (0x3<<12) /* 5VTClock */
 
#define BCUROMSPEED_PATIME_4VT   (0x2<<12) /* 4VTClock */
 
#define BCUROMSPEED_PATIME_3VT   (0x1<<12) /* 3VTClock */
 
#define BCUROMSPEED_PATIME_2VT   (0x0<<12) /* 2VTClock */
 
#define BCUROMSPEED_ATIME   (0xf) /* Access time */
 
#define BCUROMSPEED_ATIME_18VT   (0xf) /* 18VTClock */
 
#define BCUROMSPEED_ATIME_17VT   (0xe) /* 17VTClock */
 
#define BCUROMSPEED_ATIME_16VT   (0xd) /* 16VTClock */
 
#define BCUROMSPEED_ATIME_15VT   (0xc) /* 15VTClock */
 
#define BCUROMSPEED_ATIME_14VT   (0xb) /* 14VTClock */
 
#define BCUROMSPEED_ATIME_13VT   (0xa) /* 13VTClock */
 
#define BCUROMSPEED_ATIME_12VT   (0x9) /* 12VTClock */
 
#define BCUROMSPEED_ATIME_11VT   (0x8) /* 11VTClock */
 
#define BCUROMSPEED_ATIME_10VT   (0x7) /* 10VTClock */
 
#define BCUROMSPEED_ATIME_9VT   (0x6) /* 9VTClock */
 
#define BCUROMSPEED_ATIME_8VT   (0x5) /* 8VTClock */
 
#define BCUROMSPEED_ATIME_7VT   (0x4) /* 7VTClock */
 
#define BCUROMSPEED_ATIME_6VT   (0x3) /* 6VTClock */
 
#define BCUROMSPEED_ATIME_5VT   (0x2) /* 5VTClock */
 
#define BCUROMSPEED_ATIME_4VT   (0x1) /* 4VTClock */
 
#define BCUROMSPEED_ATIME_3VT   (0x0) /* 3VTClock */
 
#define BCUBCL_REG_W   0x006 /* BCU CPU Restrain Disable Register (= 4101) */
 
#define BCUIO0SPEED_REG_W   0x008 /* BCU IO0 Speed Register (=4122, 4131) */
 
#define BCUIO0SPEED_RWCS   (0x3<<12) /* R/W - CS time */
 
#define BCUIO0SPEED_RWCS_5VT   (0x3<<12) /* 5VTClock */
 
#define BCUIO0SPEED_RWCS_4VT   (0x2<<12) /* 4VTClock */
 
#define BCUIO0SPEED_RWCS_3VT   (0x1<<12) /* 3VTClock */
 
#define BCUIO0SPEED_RWCS_2VT   (0x0<<12) /* 2VTClock */
 
#define BCUIO0SPEED_RDYRW   (0xf<<8) /* IORDY-R/W time */
 
#define BCUIO0SPEED_RDYRW_18VT   (0xf) /* 18VTClock */
 
#define BCUIO0SPEED_RDYRW_17VT   (0xe) /* 17VTClock */
 
#define BCUIO0SPEED_RDYRW_16VT   (0xd) /* 16VTClock */
 
#define BCUIO0SPEED_RDYRW_15VT   (0xc) /* 15VTClock */
 
#define BCUIO0SPEED_RDYRW_14VT   (0xb) /* 14VTClock */
 
#define BCUIO0SPEED_RDYRW_13VT   (0xa) /* 13VTClock */
 
#define BCUIO0SPEED_RDYRW_12VT   (0x9) /* 12VTClock */
 
#define BCUIO0SPEED_RDYRW_11VT   (0x8) /* 11VTClock */
 
#define BCUIO0SPEED_RDYRW_10VT   (0x7) /* 10VTClock */
 
#define BCUIO0SPEED_RDYRW_9VT   (0x6) /* 9VTClock */
 
#define BCUIO0SPEED_RDYRW_8VT   (0x5) /* 8VTClock */
 
#define BCUIO0SPEED_RDYRW_7VT   (0x4) /* 7VTClock */
 
#define BCUIO0SPEED_RDYRW_6VT   (0x3) /* 6VTClock */
 
#define BCUIO0SPEED_RDYRW_5VT   (0x2) /* 5VTClock */
 
#define BCUIO0SPEED_RDYRW_4VT   (0x1) /* 4VTClock */
 
#define BCUIO0SPEED_RDYRW_3VT   (0x0) /* 3VTClock */
 
#define BCUIO0SPEED_RWRDY   (0xf<<4) /* R/W-IORDY time */
 
#define BCUIO0SPEED_RWRDY_14VT   (0xf) /* 14VTClock */
 
#define BCUIO0SPEED_RWRDY_13VT   (0xe) /* 13VTClock */
 
#define BCUIO0SPEED_RWRDY_12VT   (0xd) /* 12VTClock */
 
#define BCUIO0SPEED_RWRDY_11VT   (0xc) /* 11VTClock */
 
#define BCUIO0SPEED_RWRDY_10VT   (0xb) /* 10VTClock */
 
#define BCUIO0SPEED_RWRDY_9VT   (0xa) /* 9VTClock */
 
#define BCUIO0SPEED_RWRDY_8VT   (0x9) /* 8VTClock */
 
#define BCUIO0SPEED_RWRDY_7VT   (0x8) /* 7VTClock */
 
#define BCUIO0SPEED_RWRDY_6VT   (0x7) /* 6VTClock */
 
#define BCUIO0SPEED_RWRDY_5VT   (0x6) /* 5VTClock */
 
#define BCUIO0SPEED_RWRDY_4VT   (0x5) /* 4VTClock */
 
#define BCUIO0SPEED_RWRDY_3VT   (0x4) /* 3VTClock */
 
#define BCUIO0SPEED_RWRDY_2VT   (0x3) /* 2VTClock */
 
#define BCUIO0SPEED_RWRDY_1VT   (0x2) /* 1VTClock */
 
#define BCUIO0SPEED_RWRDY_0VT   (0x1) /* 0VTClock */
 
#define BCUIO0SPEED_RWRDY_M1VT   (0x0) /* -1VTClock */
 
#define BCUIO0SPEED_CSRW   (0xf<<0) /* IORDY-R/W time */
 
#define BCUIO0SPEED_CSRW_16VT   (0xf) /* 16VTClock */
 
#define BCUIO0SPEED_CSRW_15VT   (0xe) /* 15VTClock */
 
#define BCUIO0SPEED_CSRW_14VT   (0xd) /* 14VTClock */
 
#define BCUIO0SPEED_CSRW_13VT   (0xc) /* 13VTClock */
 
#define BCUIO0SPEED_CSRW_12VT   (0xb) /* 12VTClock */
 
#define BCUIO0SPEED_CSRW_11VT   (0xa) /* 11VTClock */
 
#define BCUIO0SPEED_CSRW_10VT   (0x9) /* 10VTClock */
 
#define BCUIO0SPEED_CSRW_9VT   (0x8) /* 9VTClock */
 
#define BCUIO0SPEED_CSRW_8VT   (0x7) /* 8VTClock */
 
#define BCUIO0SPEED_CSRW_7VT   (0x6) /* 7VTClock */
 
#define BCUIO0SPEED_CSRW_6VT   (0x5) /* 6VTClock */
 
#define BCUIO0SPEED_CSRW_5VT   (0x4) /* 5VTClock */
 
#define BCUIO0SPEED_CSRW_4VT   (0x3) /* 4VTClock */
 
#define BCUIO0SPEED_CSRW_3VT   (0x2) /* 3VTClock */
 
#define BCUIO0SPEED_CSRW_2VT   (0x1) /* 2VTClock */
 
#define BCUIO0SPEED_CSRW_1VT   (0x0) /* 1VTClock */
 
#define BCUBCLCNT_REG_W   0x008 /* BCU CPU Restrain Disable Count Register (= 4101) */
 
#define BCUIO1SPEED_REG_W   0x00A /* BCU IO1 Speed Register (=4122, 4131) */
 
#define BCUIO1SPEED_RWCS   (0x3<<12) /* R/W - CS time */
 
#define BCUIO1SPEED_RWCS_5VT   (0x3<<12) /* 5VTClock */
 
#define BCUIO1SPEED_RWCS_4VT   (0x2<<12) /* 4VTClock */
 
#define BCUIO1SPEED_RWCS_3VT   (0x1<<12) /* 3VTClock */
 
#define BCUIO1SPEED_RWCS_2VT   (0x0<<12) /* 2VTClock */
 
#define BCUIO1SPEED_RDYRW   (0xf<<8) /* IORDY-R/W time */
 
#define BCUIO1SPEED_RDYRW_18VT   (0xf) /* 18VTClock */
 
#define BCUIO1SPEED_RDYRW_17VT   (0xe) /* 17VTClock */
 
#define BCUIO1SPEED_RDYRW_16VT   (0xd) /* 16VTClock */
 
#define BCUIO1SPEED_RDYRW_15VT   (0xc) /* 15VTClock */
 
#define BCUIO1SPEED_RDYRW_14VT   (0xb) /* 14VTClock */
 
#define BCUIO1SPEED_RDYRW_13VT   (0xa) /* 13VTClock */
 
#define BCUIO1SPEED_RDYRW_12VT   (0x9) /* 12VTClock */
 
#define BCUIO1SPEED_RDYRW_11VT   (0x8) /* 11VTClock */
 
#define BCUIO1SPEED_RDYRW_10VT   (0x7) /* 10VTClock */
 
#define BCUIO1SPEED_RDYRW_9VT   (0x6) /* 9VTClock */
 
#define BCUIO1SPEED_RDYRW_8VT   (0x5) /* 8VTClock */
 
#define BCUIO1SPEED_RDYRW_7VT   (0x4) /* 7VTClock */
 
#define BCUIO1SPEED_RDYRW_6VT   (0x3) /* 6VTClock */
 
#define BCUIO1SPEED_RDYRW_5VT   (0x2) /* 5VTClock */
 
#define BCUIO1SPEED_RDYRW_4VT   (0x1) /* 4VTClock */
 
#define BCUIO1SPEED_RDYRW_3VT   (0x0) /* 3VTClock */
 
#define BCUIO1SPEED_RWRDY   (0xf<<4) /* R/W-IORDY time */
 
#define BCUIO1SPEED_RWRDY_14VT   (0xf) /* 14VTClock */
 
#define BCUIO1SPEED_RWRDY_13VT   (0xe) /* 13VTClock */
 
#define BCUIO1SPEED_RWRDY_12VT   (0xd) /* 12VTClock */
 
#define BCUIO1SPEED_RWRDY_11VT   (0xc) /* 11VTClock */
 
#define BCUIO1SPEED_RWRDY_10VT   (0xb) /* 10VTClock */
 
#define BCUIO1SPEED_RWRDY_9VT   (0xa) /* 9VTClock */
 
#define BCUIO1SPEED_RWRDY_8VT   (0x9) /* 8VTClock */
 
#define BCUIO1SPEED_RWRDY_7VT   (0x8) /* 7VTClock */
 
#define BCUIO1SPEED_RWRDY_6VT   (0x7) /* 6VTClock */
 
#define BCUIO1SPEED_RWRDY_5VT   (0x6) /* 5VTClock */
 
#define BCUIO1SPEED_RWRDY_4VT   (0x5) /* 4VTClock */
 
#define BCUIO1SPEED_RWRDY_3VT   (0x4) /* 3VTClock */
 
#define BCUIO1SPEED_RWRDY_2VT   (0x3) /* 2VTClock */
 
#define BCUIO1SPEED_RWRDY_1VT   (0x2) /* 1VTClock */
 
#define BCUIO1SPEED_RWRDY_0VT   (0x1) /* 0VTClock */
 
#define BCUIO1SPEED_RWRDY_M1VT   (0x0) /* -1VTClock */
 
#define BCUIO1SPEED_CSRW   (0xf<<0) /* IORDY-R/W time */
 
#define BCUIO1SPEED_CSRW_16VT   (0xf) /* 16VTClock */
 
#define BCUIO1SPEED_CSRW_15VT   (0xe) /* 15VTClock */
 
#define BCUIO1SPEED_CSRW_14VT   (0xd) /* 14VTClock */
 
#define BCUIO1SPEED_CSRW_13VT   (0xc) /* 13VTClock */
 
#define BCUIO1SPEED_CSRW_12VT   (0xb) /* 12VTClock */
 
#define BCUIO1SPEED_CSRW_11VT   (0xa) /* 11VTClock */
 
#define BCUIO1SPEED_CSRW_10VT   (0x9) /* 10VTClock */
 
#define BCUIO1SPEED_CSRW_9VT   (0x8) /* 9VTClock */
 
#define BCUIO1SPEED_CSRW_8VT   (0x7) /* 8VTClock */
 
#define BCUIO1SPEED_CSRW_7VT   (0x6) /* 7VTClock */
 
#define BCUIO1SPEED_CSRW_6VT   (0x5) /* 6VTClock */
 
#define BCUIO1SPEED_CSRW_5VT   (0x4) /* 5VTClock */
 
#define BCUIO1SPEED_CSRW_4VT   (0x3) /* 4VTClock */
 
#define BCUIO1SPEED_CSRW_3VT   (0x2) /* 3VTClock */
 
#define BCUIO1SPEED_CSRW_2VT   (0x1) /* 2VTClock */
 
#define BCUIO1SPEED_CSRW_1VT   (0x0) /* 1VTClock */
 
#define BCUSPEED_REG_W   0x00A /* BCU Access Cycle Change Register (4121>=4102)*/
 
#define BCUSPD_WPROM   (0x3<<12) /* Page ROM access speed */
 
#define BCUSPD_WPROMRFU   (0x3<<12) /* RFU */
 
#define BCUSPD_WPROM1T   (0x2<<12) /* 1TClock */
 
#define BCUSPD_WPROM2T   (0x1<<12) /* 2TClock */
 
#define BCUSPD_WPROM3T   (0x0<<12) /* 3TClock */
 
#define BCUSPD_WLCDM   (0x7<<8) /* access speed 0x0a000000-0affffff */
 
#define BCUSPD_WLCDRFU   (0x7<<8) /* LCD RFU */
 
#define BCUSPD_WLCDRFU1   (0x6<<8) /* LCD RFU */
 
#define BCUSPD_WLCDRFU2   (0x5<<8) /* LCD RFU */
 
#define BCUSPD_WLCDRFU3   (0x4<<8) /* LCD RFU */
 
#define BCUSPD_WLCD2T   (0x3<<8) /* LCD 2TClock */
 
#define BCUSPD_WLCD4T   (0x2<<8) /* LCD 4TClock */
 
#define BCUSPD_WLCD6T   (0x1<<8) /* LCD 6TClock */
 
#define BCUSPD_WLCD8T   (0x0<<8) /* LCD 8TClock */
 
#define BCUSPD_ISAM1T   (0x7<<8) /* ISAM 1TClock */
 
#define BCUSPD_ISAM2T   (0x6<<8) /* ISAM 2TClock */
 
#define BCUSPD_ISAM3T   (0x5<<8) /* ISAM 3TClock */
 
#define BCUSPD_ISAM4T   (0x4<<8) /* ISAM 4TClock */
 
#define BCUSPD_ISAM5T   (0x3<<8) /* ISAM 5TClock */
 
#define BCUSPD_ISAM6T   (0x2<<8) /* ISAM 6TClock */
 
#define BCUSPD_ISAM7T   (0x1<<8) /* ISAM 7TClock */
 
#define BCUSPD_ISAM8T   (0x0<<8) /* ISAM 8TClock */
 
#define BCUSPD_WISAA   (0x7<<4) /* System Bus Access Speed */
 
#define BCUSPD_WISAA3T   (0x5<<4) /* 3TClock */
 
#define BCUSPD_WISAA4T   (0x4<<4) /* 4TClock */
 
#define BCUSPD_WISAA5T   (0x3<<4) /* 5TClock */
 
#define BCUSPD_WISAA6T   (0x2<<4) /* 6TClock */
 
#define BCUSPD_WISAA7T   (0x1<<4) /* 7TClock */
 
#define BCUSPD_WISAA8T   (0x0<<4) /* 8TClock */
 
#define BCUSPD_WROMA   (0x7<<0) /* System Bus Access Speed */
 
#define BCUSPD_WROMA2T   (0x7<<0) /* 2TClock */
 
#define BCUSPD_WROMA3T   (0x6<<0) /* 3TClock */
 
#define BCUSPD_WROMA4T   (0x5<<0) /* 4TClock */
 
#define BCUSPD_WROMA5T   (0x4<<0) /* 5TClock */
 
#define BCUSPD_WROMA6T   (0x3<<0) /* 6TClock */
 
#define BCUSPD_WROMA7T   (0x2<<0) /* 7TClock */
 
#define BCUSPD_WROMA8T   (0x1<<0) /* 8TClock */
 
#define BCUSPD_WROMA9T   (0x0<<0) /* 9TClock */
 
#define BCUERRST_REG_W   0x00C /* BCU BUS ERROR Status Register (4121>=4102)*/
 
#define BCUERRST_BUSERRMASK   (1) /* Bus error, clear to 0 when 1 is written */
 
#define BCUERRST_BUSERR   (1) /* Bus error */
 
#define BCUERRST_BUSNORM   (0) /* Normal */
 
#define BCU81SPEED_REG_W   0x00C /* BCU Access Cycle Change Register (=4181)*/
 
#define BCU81SPD_WPROM   (0x7<<12) /* Page ROM access speed */
 
#define BCU81SPD_WPROM8T   (0x7<<12) /* 8TClock */
 
#define BCU81SPD_WPROM7T   (0x6<<12) /* 7TClock */
 
#define BCU81SPD_WPROM6T   (0x5<<12) /* 6TClock */
 
#define BCU81SPD_WPROM5T   (0x4<<12) /* 5TClock */
 
#define BCU81SPD_WPROM4T   (0x3<<12) /* 4TClock */
 
#define BCU81SPD_WPROM3T   (0x2<<12) /* 3TClock */
 
#define BCU81SPD_WPROM2T   (0x1<<12) /* 2TClock */
 
#define BCU81SPD_WPROM1T   (0x0<<12) /* 1TClock */
 
#define BCU81SPD_WROMA   (0xf<<0) /* System Bus Access Speed */
 
#define BCU81SPD_WROMA16T   (0xf<<0) /* 16TClock */
 
#define BCU81SPD_WROMA15T   (0xe<<0) /* 15TClock */
 
#define BCU81SPD_WROMA14T   (0xd<<0) /* 14TClock */
 
#define BCU81SPD_WROMA13T   (0xc<<0) /* 13TClock */
 
#define BCU81SPD_WROMA12T   (0xb<<0) /* 12TClock */
 
#define BCU81SPD_WROMA11T   (0xa<<0) /* 11TClock */
 
#define BCU81SPD_WROMA10T   (0x9<<0) /* 10TClock */
 
#define BCU81SPD_WROMA9T   (0x8<<0) /* 9TClock */
 
#define BCU81SPD_WROMA8T   (0x7<<0) /* 8TClock */
 
#define BCU81SPD_WROMA7T   (0x6<<0) /* 7TClock */
 
#define BCU81SPD_WROMA6T   (0x5<<0) /* 6TClock */
 
#define BCU81SPD_WROMA5T   (0x4<<0) /* 5TClock */
 
#define BCU81SPD_WROMA4T   (0x3<<0) /* 4TClock */
 
#define BCU81SPD_WROMA3T   (0x2<<0) /* 3TClock */
 
#define BCU81SPD_WROMA2T   (0x1<<0) /* 2TClock */
 
#define BCU81SPD_WROMA1T   (0x0<<0) /* 1TClock */
 
#define BCURFCNT_REG_W   0x00E /* BCU Refresh Control Register(4121>=4102) */
 
#define BCU81RFCNT_REG_W   0x010 /* BCU Refresh Control Register(=4181) */
 
#define BCURFCNT_MASK   0x3fff /* refresh interval MASK */
 
#define BCUREVID_REG_W   0x010 /* BCU Revision ID Register (4122>=4101)*/
 
#define BCU81REVID_REG_W   0x014 /* BCU Revision ID Register (=4181)*/
 
#define BCUREVID_RIDMASK   (0xf<<12) /* Revision ID */
 
#define BCUREVID_RIDSHFT   (12) /* Revision ID */
 
#define BCUREVID_RID_4131   (0x5) /* VR4131 */
 
#define BCUREVID_RID_4122   (0x4) /* VR4122 */
 
#define BCUREVID_RID_4121   (0x3) /* VR4121 */
 
#define BCUREVID_RID_4111   (0x2) /* VR4111 */
 
#define BCUREVID_RID_4102   (0x1) /* VR4102 */
 
#define BCUREVID_RID_4101   (0x0) /* VR4101 */
 
#define BCUREVID_RID_4181   (0x0) /* VR4181 conflict VR4101 */
 
#define BCUREVID_FIXRID_OFF   (0x10) /* conflict offset */
 
#define BCUREVID_FIXRID_4181   (0x10) /* VR4181 for kernel */
 
#define BCUREVID_MJREVMASK   (0xf<<8) /* Major Revision */
 
#define BCUREVID_MJREVSHFT   (8) /* Major Revision */
 
#define BCUREVID_MNREVMASK   (0xf) /* Minor Revision */
 
#define BCUREVID_MNREVSHFT   (0) /* Minor Revision */
 
#define BCUREFCOUNT_REG_W   0x012 /* BCU Refresh Count Register (>= 4102) */
 
#define BCUREFCOUNT_MASK   0x3fff /* refresh count MASK */
 
#define BCUCLKSPEED_REG_W   0x014 /* Clock Speed Register (>= 4102) */
 
#define BCU81CLKSPEED_REG_W   0x018 /* Clock Speed Register (= 4181) */
 
#define BCUCLKSPEED_DIVT2B   (1<<15) /* (= 4102, 4111) */
 
#define BCUCLKSPEED_DIVT3B   (1<<14) /* (= 4111) */
 
#define BCUCLKSPEED_DIVT4B   (1<<13) /* (= 4111) */
 
#define BCUCLKSPEED_DIVTMASK   (0xf<<12) /* (= 4121) */
 
#define BCUCLKSPEED_DIVT3   0x3
 
#define BCUCLKSPEED_DIVT4   0x4
 
#define BCUCLKSPEED_DIVT5   0x5
 
#define BCUCLKSPEED_DIVT6   0x6
 
#define BCUCLKSPEED_DIVTSHFT   (12)
 
#define BCUCLKSPEED_TDIVMODE   (0x1<<12) /* (= 4122, 4131) */
 
#define BCUCLKSPEED_TDIV4   0x1
 
#define BCUCLKSPEED_TDIV2   0x0
 
#define BCUCLKSPEED_TDIVSHFT   (12)
 
#define BCU81CLKSPEED_DIVTMASK   (0x7<<12) /* (=4181) */
 
#define BCU81CLKSPEED_DIVT1   0x7
 
#define BCU81CLKSPEED_DIVT2   0x3
 
#define BCU81CLKSPEED_DIVT3   0x5
 
#define BCU81CLKSPEED_DIVT4   0x6
 
#define BCU81CLKSPEED_DIVTSHFT   (12)
 
#define BCUCLKSPEED_DIVVTMASK   (0xf<<8) /* (= 4121) */
 
#define BCUCLKSPEED_DIVVT1   0x1
 
#define BCUCLKSPEED_DIVVT2   0x2
 
#define BCUCLKSPEED_DIVVT3   0x3
 
#define BCUCLKSPEED_DIVVT4   0x4
 
#define BCUCLKSPEED_DIVVT5   0x5
 
#define BCUCLKSPEED_DIVVT6   0x6
 
#define BCUCLKSPEED_DIVVT1_5   0x9
 
#define BCUCLKSPEED_DIVVT2_5   0xa
 
#define BCUCLKSPEED_DIVVTSHFT   (8)
 
#define BCUCLKSPEED_VTDIVMODE   (0x7<<8) /* (= 4122, 4131) */
 
#define BCUCLKSPEED_VTDIV6   0x6
 
#define BCUCLKSPEED_VTDIVT5   0x5
 
#define BCUCLKSPEED_VTDIVT4   0x4
 
#define BCUCLKSPEED_VTDIVT3   0x3
 
#define BCUCLKSPEED_VTDIVT2   0x2
 
#define BCUCLKSPEED_VTDIVT1   0x1
 
#define BCUCLKSPEED_VTDIVSHFT   (8)
 
#define BCUCLKSPEED_CLKSPMASK   (0x1f) /* calculate for Clock */
 
#define BCUCLKSPEED_CLKSPSHFT   (0)
 
#define BCUCNT3_REG_W   0x016 /* BCU Control Register 3 (>= 4111) */
 
#define BCUCNT3_EXTROMMASK   (1<<15) /* ROM SIZE (4111,4121)*/
 
#define BCUCNT3_EXTROM64M   (1<<15) /* 64Mbit DRAM */
 
#define BCUCNT3_EXTROM32M   (0<<15) /* 32Mbit DRAM */
 
#define BCUCNT3_EXTDRAMMASK   (1<<14) /* DRAM SIZE (4111,4121)*/
 
#define BCUCNT3_EXTDRAM64M   (1<<14) /* 64Mbit DRAM */
 
#define BCUCNT3_EXTDRAM16M   (0<<14) /* 16Mbit DRAM */
 
#define BCUCNT3_EXTROMCS   (0x3<<12) /* Bank3,2 */
 
#define BCUCNT3_ROMROM   (0x3<<12) /* Bank3 ROM ,2 ROM */
 
#define BCUCNT3_ROMRAM   (0x2<<12) /* Bank3 ROM ,2 RAM */
 
#define BCUCNT3_RAMRAM   (0x0<<12) /* Bank3 RAM ,2 RAM */
 
#define BCUCNT3_EXTMEM   (1<<11) /* EXT MEN enable (4111,4121)*/
 
#define BCUCNT3_EXTMEMEN   (1<<11) /* EXT MEN enable */
 
#define BCUCNT3_EXTMEMDS   (0<<11) /* EXT MEN disable */
 
#define BCUCNT3_LCDSIZE   (1<<7) /* LCD bus size */
 
#define BCUCNT3_LCD32   (1<<7) /* LCD bus 32bit */
 
#define BCUCNT3_LCD16   (0<<7) /* LCD bus 16bit */
 
#define BCUCNT3_SYSDIREN   (1<<3) /* SYSDIR or GPIO6(=4122, 4131)*/
 
#define BCUCNT3_SYSDIR   (1<<3) /* SYSDIR */
 
#define BCUCNT3_GPIO6   (0<<3) /* GPIO6 */
 
#define BCUCNT3_LCDSEL1   (1<<1) /* 0xc00-0xdff area buffer (=4122)*/
 
#define BCUCNT3_LCDSEL1_NOBUF   (1<<1) /* nobuffer */
 
#define BCUCNT3_LCDSEL1_BUF   (0<<1) /* buffer */
 
#define BCUCNT3_LCDSEL0   (1<<1) /* 0xa00-0xbff area buffer (=4122)*/
 
#define BCUCNT3_LCDSEL0_NOBUF   (1<<1) /* nobuffer */
 
#define BCUCNT3_LCDSEL0_BUF   (0<<1) /* buffer */
 

Macro Definition Documentation

◆ BCU81CLKSPEED_DIVT1

#define BCU81CLKSPEED_DIVT1   0x7

Definition at line 457 of file bcureg.h.

◆ BCU81CLKSPEED_DIVT2

#define BCU81CLKSPEED_DIVT2   0x3

Definition at line 458 of file bcureg.h.

◆ BCU81CLKSPEED_DIVT3

#define BCU81CLKSPEED_DIVT3   0x5

Definition at line 459 of file bcureg.h.

◆ BCU81CLKSPEED_DIVT4

#define BCU81CLKSPEED_DIVT4   0x6

Definition at line 460 of file bcureg.h.

◆ BCU81CLKSPEED_DIVTMASK

#define BCU81CLKSPEED_DIVTMASK   (0x7<<12) /* (=4181) */

Definition at line 456 of file bcureg.h.

◆ BCU81CLKSPEED_DIVTSHFT

#define BCU81CLKSPEED_DIVTSHFT   (12)

Definition at line 461 of file bcureg.h.

◆ BCU81CLKSPEED_REG_W

#define BCU81CLKSPEED_REG_W   0x018 /* Clock Speed Register (= 4181) */

Definition at line 438 of file bcureg.h.

◆ BCU81REVID_REG_W

#define BCU81REVID_REG_W   0x014 /* BCU Revision ID Register (=4181)*/

Definition at line 411 of file bcureg.h.

◆ BCU81RFCNT_REG_W

#define BCU81RFCNT_REG_W   0x010 /* BCU Refresh Control Register(=4181) */

Definition at line 406 of file bcureg.h.

◆ BCU81SPD_WPROM

#define BCU81SPD_WPROM   (0x7<<12) /* Page ROM access speed */

Definition at line 377 of file bcureg.h.

◆ BCU81SPD_WPROM1T

#define BCU81SPD_WPROM1T   (0x0<<12) /* 1TClock */

Definition at line 385 of file bcureg.h.

◆ BCU81SPD_WPROM2T

#define BCU81SPD_WPROM2T   (0x1<<12) /* 2TClock */

Definition at line 384 of file bcureg.h.

◆ BCU81SPD_WPROM3T

#define BCU81SPD_WPROM3T   (0x2<<12) /* 3TClock */

Definition at line 383 of file bcureg.h.

◆ BCU81SPD_WPROM4T

#define BCU81SPD_WPROM4T   (0x3<<12) /* 4TClock */

Definition at line 382 of file bcureg.h.

◆ BCU81SPD_WPROM5T

#define BCU81SPD_WPROM5T   (0x4<<12) /* 5TClock */

Definition at line 381 of file bcureg.h.

◆ BCU81SPD_WPROM6T

#define BCU81SPD_WPROM6T   (0x5<<12) /* 6TClock */

Definition at line 380 of file bcureg.h.

◆ BCU81SPD_WPROM7T

#define BCU81SPD_WPROM7T   (0x6<<12) /* 7TClock */

Definition at line 379 of file bcureg.h.

◆ BCU81SPD_WPROM8T

#define BCU81SPD_WPROM8T   (0x7<<12) /* 8TClock */

Definition at line 378 of file bcureg.h.

◆ BCU81SPD_WROMA

#define BCU81SPD_WROMA   (0xf<<0) /* System Bus Access Speed */

Definition at line 387 of file bcureg.h.

◆ BCU81SPD_WROMA10T

#define BCU81SPD_WROMA10T   (0x9<<0) /* 10TClock */

Definition at line 394 of file bcureg.h.

◆ BCU81SPD_WROMA11T

#define BCU81SPD_WROMA11T   (0xa<<0) /* 11TClock */

Definition at line 393 of file bcureg.h.

◆ BCU81SPD_WROMA12T

#define BCU81SPD_WROMA12T   (0xb<<0) /* 12TClock */

Definition at line 392 of file bcureg.h.

◆ BCU81SPD_WROMA13T

#define BCU81SPD_WROMA13T   (0xc<<0) /* 13TClock */

Definition at line 391 of file bcureg.h.

◆ BCU81SPD_WROMA14T

#define BCU81SPD_WROMA14T   (0xd<<0) /* 14TClock */

Definition at line 390 of file bcureg.h.

◆ BCU81SPD_WROMA15T

#define BCU81SPD_WROMA15T   (0xe<<0) /* 15TClock */

Definition at line 389 of file bcureg.h.

◆ BCU81SPD_WROMA16T

#define BCU81SPD_WROMA16T   (0xf<<0) /* 16TClock */

Definition at line 388 of file bcureg.h.

◆ BCU81SPD_WROMA1T

#define BCU81SPD_WROMA1T   (0x0<<0) /* 1TClock */

Definition at line 403 of file bcureg.h.

◆ BCU81SPD_WROMA2T

#define BCU81SPD_WROMA2T   (0x1<<0) /* 2TClock */

Definition at line 402 of file bcureg.h.

◆ BCU81SPD_WROMA3T

#define BCU81SPD_WROMA3T   (0x2<<0) /* 3TClock */

Definition at line 401 of file bcureg.h.

◆ BCU81SPD_WROMA4T

#define BCU81SPD_WROMA4T   (0x3<<0) /* 4TClock */

Definition at line 400 of file bcureg.h.

◆ BCU81SPD_WROMA5T

#define BCU81SPD_WROMA5T   (0x4<<0) /* 5TClock */

Definition at line 399 of file bcureg.h.

◆ BCU81SPD_WROMA6T

#define BCU81SPD_WROMA6T   (0x5<<0) /* 6TClock */

Definition at line 398 of file bcureg.h.

◆ BCU81SPD_WROMA7T

#define BCU81SPD_WROMA7T   (0x6<<0) /* 7TClock */

Definition at line 397 of file bcureg.h.

◆ BCU81SPD_WROMA8T

#define BCU81SPD_WROMA8T   (0x7<<0) /* 8TClock */

Definition at line 396 of file bcureg.h.

◆ BCU81SPD_WROMA9T

#define BCU81SPD_WROMA9T   (0x8<<0) /* 9TClock */

Definition at line 395 of file bcureg.h.

◆ BCU81SPEED_REG_W

#define BCU81SPEED_REG_W   0x00C /* BCU Access Cycle Change Register (=4181)*/

Definition at line 375 of file bcureg.h.

◆ BCUBCL_REG_W

#define BCUBCL_REG_W   0x006 /* BCU CPU Restrain Disable Register (= 4101) */

Definition at line 195 of file bcureg.h.

◆ BCUBCLCNT_REG_W

#define BCUBCLCNT_REG_W   0x008 /* BCU CPU Restrain Disable Count Register (= 4101) */

Definition at line 258 of file bcureg.h.

◆ BCUBR_REG_W

#define BCUBR_REG_W   0x002 /* BCU Bus Restrain Register (= 4101) */

Definition at line 137 of file bcureg.h.

◆ BCUBRCNT_REG_W

#define BCUBRCNT_REG_W   0x004 /* BCU Bus Restrain Count Register (= 4101) */

Definition at line 168 of file bcureg.h.

◆ BCUCLKSPEED_CLKSPMASK

#define BCUCLKSPEED_CLKSPMASK   (0x1f) /* calculate for Clock */

Definition at line 483 of file bcureg.h.

◆ BCUCLKSPEED_CLKSPSHFT

#define BCUCLKSPEED_CLKSPSHFT   (0)

Definition at line 484 of file bcureg.h.

◆ BCUCLKSPEED_DIVT2B

#define BCUCLKSPEED_DIVT2B   (1<<15) /* (= 4102, 4111) */

Definition at line 440 of file bcureg.h.

◆ BCUCLKSPEED_DIVT3

#define BCUCLKSPEED_DIVT3   0x3

Definition at line 445 of file bcureg.h.

◆ BCUCLKSPEED_DIVT3B

#define BCUCLKSPEED_DIVT3B   (1<<14) /* (= 4111) */

Definition at line 441 of file bcureg.h.

◆ BCUCLKSPEED_DIVT4

#define BCUCLKSPEED_DIVT4   0x4

Definition at line 446 of file bcureg.h.

◆ BCUCLKSPEED_DIVT4B

#define BCUCLKSPEED_DIVT4B   (1<<13) /* (= 4111) */

Definition at line 442 of file bcureg.h.

◆ BCUCLKSPEED_DIVT5

#define BCUCLKSPEED_DIVT5   0x5

Definition at line 447 of file bcureg.h.

◆ BCUCLKSPEED_DIVT6

#define BCUCLKSPEED_DIVT6   0x6

Definition at line 448 of file bcureg.h.

◆ BCUCLKSPEED_DIVTMASK

#define BCUCLKSPEED_DIVTMASK   (0xf<<12) /* (= 4121) */

Definition at line 444 of file bcureg.h.

◆ BCUCLKSPEED_DIVTSHFT

#define BCUCLKSPEED_DIVTSHFT   (12)

Definition at line 449 of file bcureg.h.

◆ BCUCLKSPEED_DIVVT1

#define BCUCLKSPEED_DIVVT1   0x1

Definition at line 464 of file bcureg.h.

◆ BCUCLKSPEED_DIVVT1_5

#define BCUCLKSPEED_DIVVT1_5   0x9

Definition at line 470 of file bcureg.h.

◆ BCUCLKSPEED_DIVVT2

#define BCUCLKSPEED_DIVVT2   0x2

Definition at line 465 of file bcureg.h.

◆ BCUCLKSPEED_DIVVT2_5

#define BCUCLKSPEED_DIVVT2_5   0xa

Definition at line 471 of file bcureg.h.

◆ BCUCLKSPEED_DIVVT3

#define BCUCLKSPEED_DIVVT3   0x3

Definition at line 466 of file bcureg.h.

◆ BCUCLKSPEED_DIVVT4

#define BCUCLKSPEED_DIVVT4   0x4

Definition at line 467 of file bcureg.h.

◆ BCUCLKSPEED_DIVVT5

#define BCUCLKSPEED_DIVVT5   0x5

Definition at line 468 of file bcureg.h.

◆ BCUCLKSPEED_DIVVT6

#define BCUCLKSPEED_DIVVT6   0x6

Definition at line 469 of file bcureg.h.

◆ BCUCLKSPEED_DIVVTMASK

#define BCUCLKSPEED_DIVVTMASK   (0xf<<8) /* (= 4121) */

Definition at line 463 of file bcureg.h.

◆ BCUCLKSPEED_DIVVTSHFT

#define BCUCLKSPEED_DIVVTSHFT   (8)

Definition at line 472 of file bcureg.h.

◆ BCUCLKSPEED_REG_W

#define BCUCLKSPEED_REG_W   0x014 /* Clock Speed Register (>= 4102) */

Definition at line 437 of file bcureg.h.

◆ BCUCLKSPEED_TDIV2

#define BCUCLKSPEED_TDIV2   0x0

Definition at line 453 of file bcureg.h.

◆ BCUCLKSPEED_TDIV4

#define BCUCLKSPEED_TDIV4   0x1

Definition at line 452 of file bcureg.h.

◆ BCUCLKSPEED_TDIVMODE

#define BCUCLKSPEED_TDIVMODE   (0x1<<12) /* (= 4122, 4131) */

Definition at line 451 of file bcureg.h.

◆ BCUCLKSPEED_TDIVSHFT

#define BCUCLKSPEED_TDIVSHFT   (12)

Definition at line 454 of file bcureg.h.

◆ BCUCLKSPEED_VTDIV6

#define BCUCLKSPEED_VTDIV6   0x6

Definition at line 475 of file bcureg.h.

◆ BCUCLKSPEED_VTDIVMODE

#define BCUCLKSPEED_VTDIVMODE   (0x7<<8) /* (= 4122, 4131) */

Definition at line 474 of file bcureg.h.

◆ BCUCLKSPEED_VTDIVSHFT

#define BCUCLKSPEED_VTDIVSHFT   (8)

Definition at line 481 of file bcureg.h.

◆ BCUCLKSPEED_VTDIVT1

#define BCUCLKSPEED_VTDIVT1   0x1

Definition at line 480 of file bcureg.h.

◆ BCUCLKSPEED_VTDIVT2

#define BCUCLKSPEED_VTDIVT2   0x2

Definition at line 479 of file bcureg.h.

◆ BCUCLKSPEED_VTDIVT3

#define BCUCLKSPEED_VTDIVT3   0x3

Definition at line 478 of file bcureg.h.

◆ BCUCLKSPEED_VTDIVT4

#define BCUCLKSPEED_VTDIVT4   0x4

Definition at line 477 of file bcureg.h.

◆ BCUCLKSPEED_VTDIVT5

#define BCUCLKSPEED_VTDIVT5   0x5

Definition at line 476 of file bcureg.h.

◆ BCUCNT1_BCPUR

#define BCUCNT1_BCPUR   (1<<3) /* CPU bus cycle control (= 4101) */

Definition at line 108 of file bcureg.h.

◆ BCUCNT1_BCPURDIS

#define BCUCNT1_BCPURDIS   (0<<3) /* CPU bus cycle control disable */

Definition at line 110 of file bcureg.h.

◆ BCUCNT1_BCPUREN

#define BCUCNT1_BCPUREN   (1<<3) /* CPU bus cycle control enable */

Definition at line 109 of file bcureg.h.

◆ BCUCNT1_BUSHERR

#define BCUCNT1_BUSHERR   (1<<1) /* Bus Timeout detection enable (<= 4121,>= 4102) */

Definition at line 116 of file bcureg.h.

◆ BCUCNT1_BUSHERRDS

#define BCUCNT1_BUSHERRDS   (0<<1) /* Prohibit */

Definition at line 119 of file bcureg.h.

◆ BCUCNT1_BUSHERREN

#define BCUCNT1_BUSHERREN   (1<<1) /* Enable */

Definition at line 118 of file bcureg.h.

◆ BCUCNT1_DRAM32M

#define BCUCNT1_DRAM32M   (0<<14) /* DRAM SIZE 32Mbit*/

Definition at line 57 of file bcureg.h.

◆ BCUCNT1_DRAM64M

#define BCUCNT1_DRAM64M   (1<<14) /* DRAM SIZE 64Mbit*/

Definition at line 56 of file bcureg.h.

◆ BCUCNT1_DRAMMASK

#define BCUCNT1_DRAMMASK   (1<<14) /* DRAM SIZE (<= 4121,>= 4102) */

Definition at line 55 of file bcureg.h.

◆ BCUCNT1_HLD

#define BCUCNT1_HLD   (1<<2) /* Bus hold enable (= 4122, 4131) */

Definition at line 112 of file bcureg.h.

◆ BCUCNT1_HLDDIS

#define BCUCNT1_HLDDIS   (1<<2) /* disable */

Definition at line 114 of file bcureg.h.

◆ BCUCNT1_HLDEN

#define BCUCNT1_HLDEN   (1<<2) /* enable */

Definition at line 113 of file bcureg.h.

◆ BCUCNT1_ISA

#define BCUCNT1_ISA   (1<<13) /* ISA memory space */

Definition at line 64 of file bcureg.h.

◆ BCUCNT1_ISAMLCD

#define BCUCNT1_ISAMLCD   (1<<13) /* ISAM/LCD 0x0a000000 to 0xaffffff(>= 4102) */

Definition at line 63 of file bcureg.h.

◆ BCUCNT1_LCD

#define BCUCNT1_LCD   (0<<13) /* LCD space*/

Definition at line 65 of file bcureg.h.

◆ BCUCNT1_PAGE0MASK

#define BCUCNT1_PAGE0MASK   (1<<8) /* (<= 4131,>= 4102) */

Definition at line 80 of file bcureg.h.

◆ BCUCNT1_PAGE0ORD

#define BCUCNT1_PAGE0ORD   (0<<8) /* Prginary ROM */

Definition at line 82 of file bcureg.h.

◆ BCUCNT1_PAGE0PAGE

#define BCUCNT1_PAGE0PAGE   (1<<8) /* Page ROM */

Definition at line 81 of file bcureg.h.

◆ BCUCNT1_PAGE128

#define BCUCNT1_PAGE128   (1<<12) /* 128bit */

Definition at line 68 of file bcureg.h.

◆ BCUCNT1_PAGE2MASK

#define BCUCNT1_PAGE2MASK   (1<<10) /* (<= 4131,>= 4102) */

Definition at line 76 of file bcureg.h.

◆ BCUCNT1_PAGE2ORD

#define BCUCNT1_PAGE2ORD   (0<<10) /* Prginary ROM */

Definition at line 78 of file bcureg.h.

◆ BCUCNT1_PAGE2PAGE

#define BCUCNT1_PAGE2PAGE   (1<<10) /* Page ROM */

Definition at line 77 of file bcureg.h.

◆ BCUCNT1_PAGE64

#define BCUCNT1_PAGE64   (0<<12) /* 64bit */

Definition at line 69 of file bcureg.h.

◆ BCUCNT1_PAGEMASK

#define BCUCNT1_PAGEMASK   (1<<12) /* Maximum burst access size for Page Rom (<= 4121,>= 4102) */

Definition at line 67 of file bcureg.h.

◆ BCUCNT1_PAGEROM

#define BCUCNT1_PAGEROM   (1<<6) /* Enable page ROM access (= 4101) */

Definition at line 92 of file bcureg.h.

◆ BCUCNT1_PAGEROMDIS

#define BCUCNT1_PAGEROMDIS   (0<<6) /* not Page ROM */

Definition at line 94 of file bcureg.h.

◆ BCUCNT1_PAGEROMEN

#define BCUCNT1_PAGEROMEN   (1<<6) /* Page ROM */

Definition at line 93 of file bcureg.h.

◆ BCUCNT1_PAGESIZEMASK

#define BCUCNT1_PAGESIZEMASK   (3<<12) /* PageROM PAGESIZE (= 4122, 4131) */

Definition at line 71 of file bcureg.h.

◆ BCUCNT1_PASESIZE16

#define BCUCNT1_PASESIZE16   (1<<12) /* 16 byte */

Definition at line 73 of file bcureg.h.

◆ BCUCNT1_PASESIZE32

#define BCUCNT1_PASESIZE32   (2<<12) /* 32 byte */

Definition at line 72 of file bcureg.h.

◆ BCUCNT1_PASESIZE8

#define BCUCNT1_PASESIZE8   (0<<12) /* 8 byte */

Definition at line 74 of file bcureg.h.

◆ BCUCNT1_REF1024

#define BCUCNT1_REF1024   (1<<7) /* 1024 cycles/128ms */

Definition at line 85 of file bcureg.h.

◆ BCUCNT1_REF4096

#define BCUCNT1_REF4096   (0<<7) /* 4096 cycles/128ms */

Definition at line 86 of file bcureg.h.

◆ BCUCNT1_REFMASK

#define BCUCNT1_REFMASK   (1<<7) /* DRAM refresh interval (= 4101) */

Definition at line 84 of file bcureg.h.

◆ BCUCNT1_REG_W

#define BCUCNT1_REG_W   0x000 /* BCU Control Register 1 */

Definition at line 49 of file bcureg.h.

◆ BCUCNT1_ROM32M

#define BCUCNT1_ROM32M   (0<<15) /* ROM SIZE 32Mbit*/

Definition at line 53 of file bcureg.h.

◆ BCUCNT1_ROM64M

#define BCUCNT1_ROM64M   (1<<15) /* ROM SIZE 64Mbit*/

Definition at line 52 of file bcureg.h.

◆ BCUCNT1_ROMMASK

#define BCUCNT1_ROMMASK   (1<<15) /* ROM SIZE (<= 4121,>= 4102) */

Definition at line 51 of file bcureg.h.

◆ BCUCNT1_ROMS32M

#define BCUCNT1_ROMS32M   (0x1<<14) /* ROM SIZE 32Mbit */

Definition at line 61 of file bcureg.h.

◆ BCUCNT1_ROMS64M

#define BCUCNT1_ROMS64M   (0x2<<14) /* ROM SIZE 64Mbit */

Definition at line 60 of file bcureg.h.

◆ BCUCNT1_ROMSMASK

#define BCUCNT1_ROMSMASK   (0x3<<14) /* ROM SIZE (=4181) */

Definition at line 59 of file bcureg.h.

◆ BCUCNT1_ROMWEN

#define BCUCNT1_ROMWEN   (1<<5) /* Enable Flash memory write ROM 0 (= 4101) */

Definition at line 96 of file bcureg.h.

◆ BCUCNT1_ROMWEN0

#define BCUCNT1_ROMWEN0   (1<<4) /* Enable Flash memory write ROM 0 (<= 4131,>= 4102, =4181) */

Definition at line 100 of file bcureg.h.

◆ BCUCNT1_ROMWEN0DS

#define BCUCNT1_ROMWEN0DS   (0<<4) /* Prohibit */

Definition at line 102 of file bcureg.h.

◆ BCUCNT1_ROMWEN0EN

#define BCUCNT1_ROMWEN0EN   (1<<4) /* Enable */

Definition at line 101 of file bcureg.h.

◆ BCUCNT1_ROMWEN2

#define BCUCNT1_ROMWEN2   (1<<6) /* Enable Flash memory write ROM 2 (<= 4131,>= 4102) */

Definition at line 88 of file bcureg.h.

◆ BCUCNT1_ROMWEN2DS

#define BCUCNT1_ROMWEN2DS   (0<<6) /* Prohibit */

Definition at line 90 of file bcureg.h.

◆ BCUCNT1_ROMWEN2EN

#define BCUCNT1_ROMWEN2EN   (1<<6) /* Enable */

Definition at line 89 of file bcureg.h.

◆ BCUCNT1_ROMWENDS

#define BCUCNT1_ROMWENDS   (0<<5) /* Prohibit */

Definition at line 98 of file bcureg.h.

◆ BCUCNT1_ROMWENEN

#define BCUCNT1_ROMWENEN   (1<<5) /* Enable */

Definition at line 97 of file bcureg.h.

◆ BCUCNT1_RSTOUT

#define BCUCNT1_RSTOUT   (1) /* RSTOUT control bit */

Definition at line 126 of file bcureg.h.

◆ BCUCNT1_RSTOUTH

#define BCUCNT1_RSTOUTH   (1) /* RSTOUT high level*/

Definition at line 127 of file bcureg.h.

◆ BCUCNT1_RSTOUTL

#define BCUCNT1_RSTOUTL   (0) /* RSTOUT low level*/

Definition at line 128 of file bcureg.h.

◆ BCUCNT1_RTFLASH

#define BCUCNT1_RTFLASH   (1<<1) /* flash ROM */

Definition at line 123 of file bcureg.h.

◆ BCUCNT1_RTOROM

#define BCUCNT1_RTOROM   (0<<1) /* Odinary ROM */

Definition at line 122 of file bcureg.h.

◆ BCUCNT1_RTPAGEROM

#define BCUCNT1_RTPAGEROM   (2<<1) /* Page ROM */

Definition at line 124 of file bcureg.h.

◆ BCUCNT1_RTYPE

#define BCUCNT1_RTYPE   (0x3<<1) /* ROM type (=4181) */

Definition at line 121 of file bcureg.h.

◆ BCUCNT1_SRFSTAT

#define BCUCNT1_SRFSTAT   (1<<4) /* DRAM refresh mode (= 4101) */

Definition at line 104 of file bcureg.h.

◆ BCUCNT1_SRFSTATCBR

#define BCUCNT1_SRFSTATCBR   (0<<4) /* CBR refresh */

Definition at line 106 of file bcureg.h.

◆ BCUCNT1_SRFSTATSRF

#define BCUCNT1_SRFSTATSRF   (1<<4) /* self refresh */

Definition at line 105 of file bcureg.h.

◆ BCUCNT2_GMODE

#define BCUCNT2_GMODE   (1) /* LCD access control */

Definition at line 133 of file bcureg.h.

◆ BCUCNT2_GMODEINV

#define BCUCNT2_GMODEINV   (0) /* invert LCD */

Definition at line 135 of file bcureg.h.

◆ BCUCNT2_GMODENOM

#define BCUCNT2_GMODENOM   (1) /* not invert LCD */

Definition at line 134 of file bcureg.h.

◆ BCUCNT2_REG_W

#define BCUCNT2_REG_W   0x002 /* BCU Control Register 2 (<= 4121,>= 4102, =4181) */

Definition at line 131 of file bcureg.h.

◆ BCUCNT3_EXTDRAM16M

#define BCUCNT3_EXTDRAM16M   (0<<14) /* 16Mbit DRAM */

Definition at line 494 of file bcureg.h.

◆ BCUCNT3_EXTDRAM64M

#define BCUCNT3_EXTDRAM64M   (1<<14) /* 64Mbit DRAM */

Definition at line 493 of file bcureg.h.

◆ BCUCNT3_EXTDRAMMASK

#define BCUCNT3_EXTDRAMMASK   (1<<14) /* DRAM SIZE (4111,4121)*/

Definition at line 492 of file bcureg.h.

◆ BCUCNT3_EXTMEM

#define BCUCNT3_EXTMEM   (1<<11) /* EXT MEN enable (4111,4121)*/

Definition at line 501 of file bcureg.h.

◆ BCUCNT3_EXTMEMDS

#define BCUCNT3_EXTMEMDS   (0<<11) /* EXT MEN disable */

Definition at line 503 of file bcureg.h.

◆ BCUCNT3_EXTMEMEN

#define BCUCNT3_EXTMEMEN   (1<<11) /* EXT MEN enable */

Definition at line 502 of file bcureg.h.

◆ BCUCNT3_EXTROM32M

#define BCUCNT3_EXTROM32M   (0<<15) /* 32Mbit DRAM */

Definition at line 490 of file bcureg.h.

◆ BCUCNT3_EXTROM64M

#define BCUCNT3_EXTROM64M   (1<<15) /* 64Mbit DRAM */

Definition at line 489 of file bcureg.h.

◆ BCUCNT3_EXTROMCS

#define BCUCNT3_EXTROMCS   (0x3<<12) /* Bank3,2 */

Definition at line 496 of file bcureg.h.

◆ BCUCNT3_EXTROMMASK

#define BCUCNT3_EXTROMMASK   (1<<15) /* ROM SIZE (4111,4121)*/

Definition at line 488 of file bcureg.h.

◆ BCUCNT3_GPIO6

#define BCUCNT3_GPIO6   (0<<3) /* GPIO6 */

Definition at line 511 of file bcureg.h.

◆ BCUCNT3_LCD16

#define BCUCNT3_LCD16   (0<<7) /* LCD bus 16bit */

Definition at line 507 of file bcureg.h.

◆ BCUCNT3_LCD32

#define BCUCNT3_LCD32   (1<<7) /* LCD bus 32bit */

Definition at line 506 of file bcureg.h.

◆ BCUCNT3_LCDSEL0

#define BCUCNT3_LCDSEL0   (1<<1) /* 0xa00-0xbff area buffer (=4122)*/

Definition at line 517 of file bcureg.h.

◆ BCUCNT3_LCDSEL0_BUF

#define BCUCNT3_LCDSEL0_BUF   (0<<1) /* buffer */

Definition at line 519 of file bcureg.h.

◆ BCUCNT3_LCDSEL0_NOBUF

#define BCUCNT3_LCDSEL0_NOBUF   (1<<1) /* nobuffer */

Definition at line 518 of file bcureg.h.

◆ BCUCNT3_LCDSEL1

#define BCUCNT3_LCDSEL1   (1<<1) /* 0xc00-0xdff area buffer (=4122)*/

Definition at line 513 of file bcureg.h.

◆ BCUCNT3_LCDSEL1_BUF

#define BCUCNT3_LCDSEL1_BUF   (0<<1) /* buffer */

Definition at line 515 of file bcureg.h.

◆ BCUCNT3_LCDSEL1_NOBUF

#define BCUCNT3_LCDSEL1_NOBUF   (1<<1) /* nobuffer */

Definition at line 514 of file bcureg.h.

◆ BCUCNT3_LCDSIZE

#define BCUCNT3_LCDSIZE   (1<<7) /* LCD bus size */

Definition at line 505 of file bcureg.h.

◆ BCUCNT3_RAMRAM

#define BCUCNT3_RAMRAM   (0x0<<12) /* Bank3 RAM ,2 RAM */

Definition at line 499 of file bcureg.h.

◆ BCUCNT3_REG_W

#define BCUCNT3_REG_W   0x016 /* BCU Control Register 3 (>= 4111) */

Definition at line 486 of file bcureg.h.

◆ BCUCNT3_ROMRAM

#define BCUCNT3_ROMRAM   (0x2<<12) /* Bank3 ROM ,2 RAM */

Definition at line 498 of file bcureg.h.

◆ BCUCNT3_ROMROM

#define BCUCNT3_ROMROM   (0x3<<12) /* Bank3 ROM ,2 ROM */

Definition at line 497 of file bcureg.h.

◆ BCUCNT3_SYSDIR

#define BCUCNT3_SYSDIR   (1<<3) /* SYSDIR */

Definition at line 510 of file bcureg.h.

◆ BCUCNT3_SYSDIREN

#define BCUCNT3_SYSDIREN   (1<<3) /* SYSDIR or GPIO6(=4122, 4131)*/

Definition at line 509 of file bcureg.h.

◆ BCUERRST_BUSERR

#define BCUERRST_BUSERR   (1) /* Bus error */

Definition at line 372 of file bcureg.h.

◆ BCUERRST_BUSERRMASK

#define BCUERRST_BUSERRMASK   (1) /* Bus error, clear to 0 when 1 is written */

Definition at line 371 of file bcureg.h.

◆ BCUERRST_BUSNORM

#define BCUERRST_BUSNORM   (0) /* Normal */

Definition at line 373 of file bcureg.h.

◆ BCUERRST_REG_W

#define BCUERRST_REG_W   0x00C /* BCU BUS ERROR Status Register (4121>=4102)*/

Definition at line 369 of file bcureg.h.

◆ BCUIO0SPEED_CSRW

#define BCUIO0SPEED_CSRW   (0xf<<0) /* IORDY-R/W time */

Definition at line 240 of file bcureg.h.

◆ BCUIO0SPEED_CSRW_10VT

#define BCUIO0SPEED_CSRW_10VT   (0x9) /* 10VTClock */

Definition at line 247 of file bcureg.h.

◆ BCUIO0SPEED_CSRW_11VT

#define BCUIO0SPEED_CSRW_11VT   (0xa) /* 11VTClock */

Definition at line 246 of file bcureg.h.

◆ BCUIO0SPEED_CSRW_12VT

#define BCUIO0SPEED_CSRW_12VT   (0xb) /* 12VTClock */

Definition at line 245 of file bcureg.h.

◆ BCUIO0SPEED_CSRW_13VT

#define BCUIO0SPEED_CSRW_13VT   (0xc) /* 13VTClock */

Definition at line 244 of file bcureg.h.

◆ BCUIO0SPEED_CSRW_14VT

#define BCUIO0SPEED_CSRW_14VT   (0xd) /* 14VTClock */

Definition at line 243 of file bcureg.h.

◆ BCUIO0SPEED_CSRW_15VT

#define BCUIO0SPEED_CSRW_15VT   (0xe) /* 15VTClock */

Definition at line 242 of file bcureg.h.

◆ BCUIO0SPEED_CSRW_16VT

#define BCUIO0SPEED_CSRW_16VT   (0xf) /* 16VTClock */

Definition at line 241 of file bcureg.h.

◆ BCUIO0SPEED_CSRW_1VT

#define BCUIO0SPEED_CSRW_1VT   (0x0) /* 1VTClock */

Definition at line 256 of file bcureg.h.

◆ BCUIO0SPEED_CSRW_2VT

#define BCUIO0SPEED_CSRW_2VT   (0x1) /* 2VTClock */

Definition at line 255 of file bcureg.h.

◆ BCUIO0SPEED_CSRW_3VT

#define BCUIO0SPEED_CSRW_3VT   (0x2) /* 3VTClock */

Definition at line 254 of file bcureg.h.

◆ BCUIO0SPEED_CSRW_4VT

#define BCUIO0SPEED_CSRW_4VT   (0x3) /* 4VTClock */

Definition at line 253 of file bcureg.h.

◆ BCUIO0SPEED_CSRW_5VT

#define BCUIO0SPEED_CSRW_5VT   (0x4) /* 5VTClock */

Definition at line 252 of file bcureg.h.

◆ BCUIO0SPEED_CSRW_6VT

#define BCUIO0SPEED_CSRW_6VT   (0x5) /* 6VTClock */

Definition at line 251 of file bcureg.h.

◆ BCUIO0SPEED_CSRW_7VT

#define BCUIO0SPEED_CSRW_7VT   (0x6) /* 7VTClock */

Definition at line 250 of file bcureg.h.

◆ BCUIO0SPEED_CSRW_8VT

#define BCUIO0SPEED_CSRW_8VT   (0x7) /* 8VTClock */

Definition at line 249 of file bcureg.h.

◆ BCUIO0SPEED_CSRW_9VT

#define BCUIO0SPEED_CSRW_9VT   (0x8) /* 9VTClock */

Definition at line 248 of file bcureg.h.

◆ BCUIO0SPEED_RDYRW

#define BCUIO0SPEED_RDYRW   (0xf<<8) /* IORDY-R/W time */

Definition at line 204 of file bcureg.h.

◆ BCUIO0SPEED_RDYRW_10VT

#define BCUIO0SPEED_RDYRW_10VT   (0x7) /* 10VTClock */

Definition at line 213 of file bcureg.h.

◆ BCUIO0SPEED_RDYRW_11VT

#define BCUIO0SPEED_RDYRW_11VT   (0x8) /* 11VTClock */

Definition at line 212 of file bcureg.h.

◆ BCUIO0SPEED_RDYRW_12VT

#define BCUIO0SPEED_RDYRW_12VT   (0x9) /* 12VTClock */

Definition at line 211 of file bcureg.h.

◆ BCUIO0SPEED_RDYRW_13VT

#define BCUIO0SPEED_RDYRW_13VT   (0xa) /* 13VTClock */

Definition at line 210 of file bcureg.h.

◆ BCUIO0SPEED_RDYRW_14VT

#define BCUIO0SPEED_RDYRW_14VT   (0xb) /* 14VTClock */

Definition at line 209 of file bcureg.h.

◆ BCUIO0SPEED_RDYRW_15VT

#define BCUIO0SPEED_RDYRW_15VT   (0xc) /* 15VTClock */

Definition at line 208 of file bcureg.h.

◆ BCUIO0SPEED_RDYRW_16VT

#define BCUIO0SPEED_RDYRW_16VT   (0xd) /* 16VTClock */

Definition at line 207 of file bcureg.h.

◆ BCUIO0SPEED_RDYRW_17VT

#define BCUIO0SPEED_RDYRW_17VT   (0xe) /* 17VTClock */

Definition at line 206 of file bcureg.h.

◆ BCUIO0SPEED_RDYRW_18VT

#define BCUIO0SPEED_RDYRW_18VT   (0xf) /* 18VTClock */

Definition at line 205 of file bcureg.h.

◆ BCUIO0SPEED_RDYRW_3VT

#define BCUIO0SPEED_RDYRW_3VT   (0x0) /* 3VTClock */

Definition at line 220 of file bcureg.h.

◆ BCUIO0SPEED_RDYRW_4VT

#define BCUIO0SPEED_RDYRW_4VT   (0x1) /* 4VTClock */

Definition at line 219 of file bcureg.h.

◆ BCUIO0SPEED_RDYRW_5VT

#define BCUIO0SPEED_RDYRW_5VT   (0x2) /* 5VTClock */

Definition at line 218 of file bcureg.h.

◆ BCUIO0SPEED_RDYRW_6VT

#define BCUIO0SPEED_RDYRW_6VT   (0x3) /* 6VTClock */

Definition at line 217 of file bcureg.h.

◆ BCUIO0SPEED_RDYRW_7VT

#define BCUIO0SPEED_RDYRW_7VT   (0x4) /* 7VTClock */

Definition at line 216 of file bcureg.h.

◆ BCUIO0SPEED_RDYRW_8VT

#define BCUIO0SPEED_RDYRW_8VT   (0x5) /* 8VTClock */

Definition at line 215 of file bcureg.h.

◆ BCUIO0SPEED_RDYRW_9VT

#define BCUIO0SPEED_RDYRW_9VT   (0x6) /* 9VTClock */

Definition at line 214 of file bcureg.h.

◆ BCUIO0SPEED_REG_W

#define BCUIO0SPEED_REG_W   0x008 /* BCU IO0 Speed Register (=4122, 4131) */

Definition at line 197 of file bcureg.h.

◆ BCUIO0SPEED_RWCS

#define BCUIO0SPEED_RWCS   (0x3<<12) /* R/W - CS time */

Definition at line 198 of file bcureg.h.

◆ BCUIO0SPEED_RWCS_2VT

#define BCUIO0SPEED_RWCS_2VT   (0x0<<12) /* 2VTClock */

Definition at line 202 of file bcureg.h.

◆ BCUIO0SPEED_RWCS_3VT

#define BCUIO0SPEED_RWCS_3VT   (0x1<<12) /* 3VTClock */

Definition at line 201 of file bcureg.h.

◆ BCUIO0SPEED_RWCS_4VT

#define BCUIO0SPEED_RWCS_4VT   (0x2<<12) /* 4VTClock */

Definition at line 200 of file bcureg.h.

◆ BCUIO0SPEED_RWCS_5VT

#define BCUIO0SPEED_RWCS_5VT   (0x3<<12) /* 5VTClock */

Definition at line 199 of file bcureg.h.

◆ BCUIO0SPEED_RWRDY

#define BCUIO0SPEED_RWRDY   (0xf<<4) /* R/W-IORDY time */

Definition at line 222 of file bcureg.h.

◆ BCUIO0SPEED_RWRDY_0VT

#define BCUIO0SPEED_RWRDY_0VT   (0x1) /* 0VTClock */

Definition at line 237 of file bcureg.h.

◆ BCUIO0SPEED_RWRDY_10VT

#define BCUIO0SPEED_RWRDY_10VT   (0xb) /* 10VTClock */

Definition at line 227 of file bcureg.h.

◆ BCUIO0SPEED_RWRDY_11VT

#define BCUIO0SPEED_RWRDY_11VT   (0xc) /* 11VTClock */

Definition at line 226 of file bcureg.h.

◆ BCUIO0SPEED_RWRDY_12VT

#define BCUIO0SPEED_RWRDY_12VT   (0xd) /* 12VTClock */

Definition at line 225 of file bcureg.h.

◆ BCUIO0SPEED_RWRDY_13VT

#define BCUIO0SPEED_RWRDY_13VT   (0xe) /* 13VTClock */

Definition at line 224 of file bcureg.h.

◆ BCUIO0SPEED_RWRDY_14VT

#define BCUIO0SPEED_RWRDY_14VT   (0xf) /* 14VTClock */

Definition at line 223 of file bcureg.h.

◆ BCUIO0SPEED_RWRDY_1VT

#define BCUIO0SPEED_RWRDY_1VT   (0x2) /* 1VTClock */

Definition at line 236 of file bcureg.h.

◆ BCUIO0SPEED_RWRDY_2VT

#define BCUIO0SPEED_RWRDY_2VT   (0x3) /* 2VTClock */

Definition at line 235 of file bcureg.h.

◆ BCUIO0SPEED_RWRDY_3VT

#define BCUIO0SPEED_RWRDY_3VT   (0x4) /* 3VTClock */

Definition at line 234 of file bcureg.h.

◆ BCUIO0SPEED_RWRDY_4VT

#define BCUIO0SPEED_RWRDY_4VT   (0x5) /* 4VTClock */

Definition at line 233 of file bcureg.h.

◆ BCUIO0SPEED_RWRDY_5VT

#define BCUIO0SPEED_RWRDY_5VT   (0x6) /* 5VTClock */

Definition at line 232 of file bcureg.h.

◆ BCUIO0SPEED_RWRDY_6VT

#define BCUIO0SPEED_RWRDY_6VT   (0x7) /* 6VTClock */

Definition at line 231 of file bcureg.h.

◆ BCUIO0SPEED_RWRDY_7VT

#define BCUIO0SPEED_RWRDY_7VT   (0x8) /* 7VTClock */

Definition at line 230 of file bcureg.h.

◆ BCUIO0SPEED_RWRDY_8VT

#define BCUIO0SPEED_RWRDY_8VT   (0x9) /* 8VTClock */

Definition at line 229 of file bcureg.h.

◆ BCUIO0SPEED_RWRDY_9VT

#define BCUIO0SPEED_RWRDY_9VT   (0xa) /* 9VTClock */

Definition at line 228 of file bcureg.h.

◆ BCUIO0SPEED_RWRDY_M1VT

#define BCUIO0SPEED_RWRDY_M1VT   (0x0) /* -1VTClock */

Definition at line 238 of file bcureg.h.

◆ BCUIO1SPEED_CSRW

#define BCUIO1SPEED_CSRW   (0xf<<0) /* IORDY-R/W time */

Definition at line 303 of file bcureg.h.

◆ BCUIO1SPEED_CSRW_10VT

#define BCUIO1SPEED_CSRW_10VT   (0x9) /* 10VTClock */

Definition at line 310 of file bcureg.h.

◆ BCUIO1SPEED_CSRW_11VT

#define BCUIO1SPEED_CSRW_11VT   (0xa) /* 11VTClock */

Definition at line 309 of file bcureg.h.

◆ BCUIO1SPEED_CSRW_12VT

#define BCUIO1SPEED_CSRW_12VT   (0xb) /* 12VTClock */

Definition at line 308 of file bcureg.h.

◆ BCUIO1SPEED_CSRW_13VT

#define BCUIO1SPEED_CSRW_13VT   (0xc) /* 13VTClock */

Definition at line 307 of file bcureg.h.

◆ BCUIO1SPEED_CSRW_14VT

#define BCUIO1SPEED_CSRW_14VT   (0xd) /* 14VTClock */

Definition at line 306 of file bcureg.h.

◆ BCUIO1SPEED_CSRW_15VT

#define BCUIO1SPEED_CSRW_15VT   (0xe) /* 15VTClock */

Definition at line 305 of file bcureg.h.

◆ BCUIO1SPEED_CSRW_16VT

#define BCUIO1SPEED_CSRW_16VT   (0xf) /* 16VTClock */

Definition at line 304 of file bcureg.h.

◆ BCUIO1SPEED_CSRW_1VT

#define BCUIO1SPEED_CSRW_1VT   (0x0) /* 1VTClock */

Definition at line 319 of file bcureg.h.

◆ BCUIO1SPEED_CSRW_2VT

#define BCUIO1SPEED_CSRW_2VT   (0x1) /* 2VTClock */

Definition at line 318 of file bcureg.h.

◆ BCUIO1SPEED_CSRW_3VT

#define BCUIO1SPEED_CSRW_3VT   (0x2) /* 3VTClock */

Definition at line 317 of file bcureg.h.

◆ BCUIO1SPEED_CSRW_4VT

#define BCUIO1SPEED_CSRW_4VT   (0x3) /* 4VTClock */

Definition at line 316 of file bcureg.h.

◆ BCUIO1SPEED_CSRW_5VT

#define BCUIO1SPEED_CSRW_5VT   (0x4) /* 5VTClock */

Definition at line 315 of file bcureg.h.

◆ BCUIO1SPEED_CSRW_6VT

#define BCUIO1SPEED_CSRW_6VT   (0x5) /* 6VTClock */

Definition at line 314 of file bcureg.h.

◆ BCUIO1SPEED_CSRW_7VT

#define BCUIO1SPEED_CSRW_7VT   (0x6) /* 7VTClock */

Definition at line 313 of file bcureg.h.

◆ BCUIO1SPEED_CSRW_8VT

#define BCUIO1SPEED_CSRW_8VT   (0x7) /* 8VTClock */

Definition at line 312 of file bcureg.h.

◆ BCUIO1SPEED_CSRW_9VT

#define BCUIO1SPEED_CSRW_9VT   (0x8) /* 9VTClock */

Definition at line 311 of file bcureg.h.

◆ BCUIO1SPEED_RDYRW

#define BCUIO1SPEED_RDYRW   (0xf<<8) /* IORDY-R/W time */

Definition at line 267 of file bcureg.h.

◆ BCUIO1SPEED_RDYRW_10VT

#define BCUIO1SPEED_RDYRW_10VT   (0x7) /* 10VTClock */

Definition at line 276 of file bcureg.h.

◆ BCUIO1SPEED_RDYRW_11VT

#define BCUIO1SPEED_RDYRW_11VT   (0x8) /* 11VTClock */

Definition at line 275 of file bcureg.h.

◆ BCUIO1SPEED_RDYRW_12VT

#define BCUIO1SPEED_RDYRW_12VT   (0x9) /* 12VTClock */

Definition at line 274 of file bcureg.h.

◆ BCUIO1SPEED_RDYRW_13VT

#define BCUIO1SPEED_RDYRW_13VT   (0xa) /* 13VTClock */

Definition at line 273 of file bcureg.h.

◆ BCUIO1SPEED_RDYRW_14VT

#define BCUIO1SPEED_RDYRW_14VT   (0xb) /* 14VTClock */

Definition at line 272 of file bcureg.h.

◆ BCUIO1SPEED_RDYRW_15VT

#define BCUIO1SPEED_RDYRW_15VT   (0xc) /* 15VTClock */

Definition at line 271 of file bcureg.h.

◆ BCUIO1SPEED_RDYRW_16VT

#define BCUIO1SPEED_RDYRW_16VT   (0xd) /* 16VTClock */

Definition at line 270 of file bcureg.h.

◆ BCUIO1SPEED_RDYRW_17VT

#define BCUIO1SPEED_RDYRW_17VT   (0xe) /* 17VTClock */

Definition at line 269 of file bcureg.h.

◆ BCUIO1SPEED_RDYRW_18VT

#define BCUIO1SPEED_RDYRW_18VT   (0xf) /* 18VTClock */

Definition at line 268 of file bcureg.h.

◆ BCUIO1SPEED_RDYRW_3VT

#define BCUIO1SPEED_RDYRW_3VT   (0x0) /* 3VTClock */

Definition at line 283 of file bcureg.h.

◆ BCUIO1SPEED_RDYRW_4VT

#define BCUIO1SPEED_RDYRW_4VT   (0x1) /* 4VTClock */

Definition at line 282 of file bcureg.h.

◆ BCUIO1SPEED_RDYRW_5VT

#define BCUIO1SPEED_RDYRW_5VT   (0x2) /* 5VTClock */

Definition at line 281 of file bcureg.h.

◆ BCUIO1SPEED_RDYRW_6VT

#define BCUIO1SPEED_RDYRW_6VT   (0x3) /* 6VTClock */

Definition at line 280 of file bcureg.h.

◆ BCUIO1SPEED_RDYRW_7VT

#define BCUIO1SPEED_RDYRW_7VT   (0x4) /* 7VTClock */

Definition at line 279 of file bcureg.h.

◆ BCUIO1SPEED_RDYRW_8VT

#define BCUIO1SPEED_RDYRW_8VT   (0x5) /* 8VTClock */

Definition at line 278 of file bcureg.h.

◆ BCUIO1SPEED_RDYRW_9VT

#define BCUIO1SPEED_RDYRW_9VT   (0x6) /* 9VTClock */

Definition at line 277 of file bcureg.h.

◆ BCUIO1SPEED_REG_W

#define BCUIO1SPEED_REG_W   0x00A /* BCU IO1 Speed Register (=4122, 4131) */

Definition at line 260 of file bcureg.h.

◆ BCUIO1SPEED_RWCS

#define BCUIO1SPEED_RWCS   (0x3<<12) /* R/W - CS time */

Definition at line 261 of file bcureg.h.

◆ BCUIO1SPEED_RWCS_2VT

#define BCUIO1SPEED_RWCS_2VT   (0x0<<12) /* 2VTClock */

Definition at line 265 of file bcureg.h.

◆ BCUIO1SPEED_RWCS_3VT

#define BCUIO1SPEED_RWCS_3VT   (0x1<<12) /* 3VTClock */

Definition at line 264 of file bcureg.h.

◆ BCUIO1SPEED_RWCS_4VT

#define BCUIO1SPEED_RWCS_4VT   (0x2<<12) /* 4VTClock */

Definition at line 263 of file bcureg.h.

◆ BCUIO1SPEED_RWCS_5VT

#define BCUIO1SPEED_RWCS_5VT   (0x3<<12) /* 5VTClock */

Definition at line 262 of file bcureg.h.

◆ BCUIO1SPEED_RWRDY

#define BCUIO1SPEED_RWRDY   (0xf<<4) /* R/W-IORDY time */

Definition at line 285 of file bcureg.h.

◆ BCUIO1SPEED_RWRDY_0VT

#define BCUIO1SPEED_RWRDY_0VT   (0x1) /* 0VTClock */

Definition at line 300 of file bcureg.h.

◆ BCUIO1SPEED_RWRDY_10VT

#define BCUIO1SPEED_RWRDY_10VT   (0xb) /* 10VTClock */

Definition at line 290 of file bcureg.h.

◆ BCUIO1SPEED_RWRDY_11VT

#define BCUIO1SPEED_RWRDY_11VT   (0xc) /* 11VTClock */

Definition at line 289 of file bcureg.h.

◆ BCUIO1SPEED_RWRDY_12VT

#define BCUIO1SPEED_RWRDY_12VT   (0xd) /* 12VTClock */

Definition at line 288 of file bcureg.h.

◆ BCUIO1SPEED_RWRDY_13VT

#define BCUIO1SPEED_RWRDY_13VT   (0xe) /* 13VTClock */

Definition at line 287 of file bcureg.h.

◆ BCUIO1SPEED_RWRDY_14VT

#define BCUIO1SPEED_RWRDY_14VT   (0xf) /* 14VTClock */

Definition at line 286 of file bcureg.h.

◆ BCUIO1SPEED_RWRDY_1VT

#define BCUIO1SPEED_RWRDY_1VT   (0x2) /* 1VTClock */

Definition at line 299 of file bcureg.h.

◆ BCUIO1SPEED_RWRDY_2VT

#define BCUIO1SPEED_RWRDY_2VT   (0x3) /* 2VTClock */

Definition at line 298 of file bcureg.h.

◆ BCUIO1SPEED_RWRDY_3VT

#define BCUIO1SPEED_RWRDY_3VT   (0x4) /* 3VTClock */

Definition at line 297 of file bcureg.h.

◆ BCUIO1SPEED_RWRDY_4VT

#define BCUIO1SPEED_RWRDY_4VT   (0x5) /* 4VTClock */

Definition at line 296 of file bcureg.h.

◆ BCUIO1SPEED_RWRDY_5VT

#define BCUIO1SPEED_RWRDY_5VT   (0x6) /* 5VTClock */

Definition at line 295 of file bcureg.h.

◆ BCUIO1SPEED_RWRDY_6VT

#define BCUIO1SPEED_RWRDY_6VT   (0x7) /* 6VTClock */

Definition at line 294 of file bcureg.h.

◆ BCUIO1SPEED_RWRDY_7VT

#define BCUIO1SPEED_RWRDY_7VT   (0x8) /* 7VTClock */

Definition at line 293 of file bcureg.h.

◆ BCUIO1SPEED_RWRDY_8VT

#define BCUIO1SPEED_RWRDY_8VT   (0x9) /* 8VTClock */

Definition at line 292 of file bcureg.h.

◆ BCUIO1SPEED_RWRDY_9VT

#define BCUIO1SPEED_RWRDY_9VT   (0xa) /* 9VTClock */

Definition at line 291 of file bcureg.h.

◆ BCUIO1SPEED_RWRDY_M1VT

#define BCUIO1SPEED_RWRDY_M1VT   (0x0) /* -1VTClock */

Definition at line 301 of file bcureg.h.

◆ BCUREFCOUNT_MASK

#define BCUREFCOUNT_MASK   0x3fff /* refresh count MASK */

Definition at line 434 of file bcureg.h.

◆ BCUREFCOUNT_REG_W

#define BCUREFCOUNT_REG_W   0x012 /* BCU Refresh Count Register (>= 4102) */

Definition at line 432 of file bcureg.h.

◆ BCUREVID_FIXRID_4181

#define BCUREVID_FIXRID_4181   (0x10) /* VR4181 for kernel */

Definition at line 423 of file bcureg.h.

◆ BCUREVID_FIXRID_OFF

#define BCUREVID_FIXRID_OFF   (0x10) /* conflict offset */

Definition at line 422 of file bcureg.h.

◆ BCUREVID_MJREVMASK

#define BCUREVID_MJREVMASK   (0xf<<8) /* Major Revision */

Definition at line 425 of file bcureg.h.

◆ BCUREVID_MJREVSHFT

#define BCUREVID_MJREVSHFT   (8) /* Major Revision */

Definition at line 426 of file bcureg.h.

◆ BCUREVID_MNREVMASK

#define BCUREVID_MNREVMASK   (0xf) /* Minor Revision */

Definition at line 428 of file bcureg.h.

◆ BCUREVID_MNREVSHFT

#define BCUREVID_MNREVSHFT   (0) /* Minor Revision */

Definition at line 429 of file bcureg.h.

◆ BCUREVID_REG_W

#define BCUREVID_REG_W   0x010 /* BCU Revision ID Register (4122>=4101)*/

Definition at line 410 of file bcureg.h.

◆ BCUREVID_RID_4101

#define BCUREVID_RID_4101   (0x0) /* VR4101 */

Definition at line 420 of file bcureg.h.

◆ BCUREVID_RID_4102

#define BCUREVID_RID_4102   (0x1) /* VR4102 */

Definition at line 419 of file bcureg.h.

◆ BCUREVID_RID_4111

#define BCUREVID_RID_4111   (0x2) /* VR4111 */

Definition at line 418 of file bcureg.h.

◆ BCUREVID_RID_4121

#define BCUREVID_RID_4121   (0x3) /* VR4121 */

Definition at line 417 of file bcureg.h.

◆ BCUREVID_RID_4122

#define BCUREVID_RID_4122   (0x4) /* VR4122 */

Definition at line 416 of file bcureg.h.

◆ BCUREVID_RID_4131

#define BCUREVID_RID_4131   (0x5) /* VR4131 */

Definition at line 415 of file bcureg.h.

◆ BCUREVID_RID_4181

#define BCUREVID_RID_4181   (0x0) /* VR4181 conflict VR4101 */

Definition at line 421 of file bcureg.h.

◆ BCUREVID_RIDMASK

#define BCUREVID_RIDMASK   (0xf<<12) /* Revision ID */

Definition at line 413 of file bcureg.h.

◆ BCUREVID_RIDSHFT

#define BCUREVID_RIDSHFT   (12) /* Revision ID */

Definition at line 414 of file bcureg.h.

◆ BCURFCNT_MASK

#define BCURFCNT_MASK   0x3fff /* refresh interval MASK */

Definition at line 408 of file bcureg.h.

◆ BCURFCNT_REG_W

#define BCURFCNT_REG_W   0x00E /* BCU Refresh Control Register(4121>=4102) */

Definition at line 405 of file bcureg.h.

◆ BCUROMSIZE_REG_W

#define BCUROMSIZE_REG_W   0x004 /* ROM size setting register (= 4122, 4131) */

Definition at line 139 of file bcureg.h.

◆ BCUROMSIZE_SIZE0

#define BCUROMSIZE_SIZE0   (7) /* Bank0 size */

Definition at line 161 of file bcureg.h.

◆ BCUROMSIZE_SIZE0_16

#define BCUROMSIZE_SIZE0_16   (3) /* 16MB */

Definition at line 164 of file bcureg.h.

◆ BCUROMSIZE_SIZE0_32

#define BCUROMSIZE_SIZE0_32   (4) /* 32MB */

Definition at line 163 of file bcureg.h.

◆ BCUROMSIZE_SIZE0_4

#define BCUROMSIZE_SIZE0_4   (1) /* 4MB */

Definition at line 166 of file bcureg.h.

◆ BCUROMSIZE_SIZE0_64

#define BCUROMSIZE_SIZE0_64   (5) /* 64MB */

Definition at line 162 of file bcureg.h.

◆ BCUROMSIZE_SIZE0_8

#define BCUROMSIZE_SIZE0_8   (2) /* 8MB */

Definition at line 165 of file bcureg.h.

◆ BCUROMSIZE_SIZE1

#define BCUROMSIZE_SIZE1   (7<<4) /* Bank1 size */

Definition at line 154 of file bcureg.h.

◆ BCUROMSIZE_SIZE1_16

#define BCUROMSIZE_SIZE1_16   (3<<4) /* 16MB */

Definition at line 157 of file bcureg.h.

◆ BCUROMSIZE_SIZE1_32

#define BCUROMSIZE_SIZE1_32   (4<<4) /* 32MB */

Definition at line 156 of file bcureg.h.

◆ BCUROMSIZE_SIZE1_4

#define BCUROMSIZE_SIZE1_4   (1<<4) /* 4MB */

Definition at line 159 of file bcureg.h.

◆ BCUROMSIZE_SIZE1_64

#define BCUROMSIZE_SIZE1_64   (5<<4) /* 64MB */

Definition at line 155 of file bcureg.h.

◆ BCUROMSIZE_SIZE1_8

#define BCUROMSIZE_SIZE1_8   (2<<4) /* 8MB */

Definition at line 158 of file bcureg.h.

◆ BCUROMSIZE_SIZE2

#define BCUROMSIZE_SIZE2   (7<<8) /* Bank2 size */

Definition at line 147 of file bcureg.h.

◆ BCUROMSIZE_SIZE2_16

#define BCUROMSIZE_SIZE2_16   (3<<8) /* 16MB */

Definition at line 150 of file bcureg.h.

◆ BCUROMSIZE_SIZE2_32

#define BCUROMSIZE_SIZE2_32   (4<<8) /* 32MB */

Definition at line 149 of file bcureg.h.

◆ BCUROMSIZE_SIZE2_4

#define BCUROMSIZE_SIZE2_4   (1<<8) /* 4MB */

Definition at line 152 of file bcureg.h.

◆ BCUROMSIZE_SIZE2_64

#define BCUROMSIZE_SIZE2_64   (5<<8) /* 64MB */

Definition at line 148 of file bcureg.h.

◆ BCUROMSIZE_SIZE2_8

#define BCUROMSIZE_SIZE2_8   (2<<8) /* 8MB */

Definition at line 151 of file bcureg.h.

◆ BCUROMSIZE_SIZE3

#define BCUROMSIZE_SIZE3   (7<<12) /* Bank3 size */

Definition at line 140 of file bcureg.h.

◆ BCUROMSIZE_SIZE3_16

#define BCUROMSIZE_SIZE3_16   (3<<12) /* 16MB */

Definition at line 143 of file bcureg.h.

◆ BCUROMSIZE_SIZE3_32

#define BCUROMSIZE_SIZE3_32   (4<<12) /* 32MB */

Definition at line 142 of file bcureg.h.

◆ BCUROMSIZE_SIZE3_4

#define BCUROMSIZE_SIZE3_4   (1<<12) /* 4MB */

Definition at line 145 of file bcureg.h.

◆ BCUROMSIZE_SIZE3_64

#define BCUROMSIZE_SIZE3_64   (5<<12) /* 64MB */

Definition at line 141 of file bcureg.h.

◆ BCUROMSIZE_SIZE3_8

#define BCUROMSIZE_SIZE3_8   (2<<12) /* 8MB */

Definition at line 144 of file bcureg.h.

◆ BCUROMSPEED_ATIME

#define BCUROMSPEED_ATIME   (0xf) /* Access time */

Definition at line 177 of file bcureg.h.

◆ BCUROMSPEED_ATIME_10VT

#define BCUROMSPEED_ATIME_10VT   (0x7) /* 10VTClock */

Definition at line 186 of file bcureg.h.

◆ BCUROMSPEED_ATIME_11VT

#define BCUROMSPEED_ATIME_11VT   (0x8) /* 11VTClock */

Definition at line 185 of file bcureg.h.

◆ BCUROMSPEED_ATIME_12VT

#define BCUROMSPEED_ATIME_12VT   (0x9) /* 12VTClock */

Definition at line 184 of file bcureg.h.

◆ BCUROMSPEED_ATIME_13VT

#define BCUROMSPEED_ATIME_13VT   (0xa) /* 13VTClock */

Definition at line 183 of file bcureg.h.

◆ BCUROMSPEED_ATIME_14VT

#define BCUROMSPEED_ATIME_14VT   (0xb) /* 14VTClock */

Definition at line 182 of file bcureg.h.

◆ BCUROMSPEED_ATIME_15VT

#define BCUROMSPEED_ATIME_15VT   (0xc) /* 15VTClock */

Definition at line 181 of file bcureg.h.

◆ BCUROMSPEED_ATIME_16VT

#define BCUROMSPEED_ATIME_16VT   (0xd) /* 16VTClock */

Definition at line 180 of file bcureg.h.

◆ BCUROMSPEED_ATIME_17VT

#define BCUROMSPEED_ATIME_17VT   (0xe) /* 17VTClock */

Definition at line 179 of file bcureg.h.

◆ BCUROMSPEED_ATIME_18VT

#define BCUROMSPEED_ATIME_18VT   (0xf) /* 18VTClock */

Definition at line 178 of file bcureg.h.

◆ BCUROMSPEED_ATIME_3VT

#define BCUROMSPEED_ATIME_3VT   (0x0) /* 3VTClock */

Definition at line 193 of file bcureg.h.

◆ BCUROMSPEED_ATIME_4VT

#define BCUROMSPEED_ATIME_4VT   (0x1) /* 4VTClock */

Definition at line 192 of file bcureg.h.

◆ BCUROMSPEED_ATIME_5VT

#define BCUROMSPEED_ATIME_5VT   (0x2) /* 5VTClock */

Definition at line 191 of file bcureg.h.

◆ BCUROMSPEED_ATIME_6VT

#define BCUROMSPEED_ATIME_6VT   (0x3) /* 6VTClock */

Definition at line 190 of file bcureg.h.

◆ BCUROMSPEED_ATIME_7VT

#define BCUROMSPEED_ATIME_7VT   (0x4) /* 7VTClock */

Definition at line 189 of file bcureg.h.

◆ BCUROMSPEED_ATIME_8VT

#define BCUROMSPEED_ATIME_8VT   (0x5) /* 8VTClock */

Definition at line 188 of file bcureg.h.

◆ BCUROMSPEED_ATIME_9VT

#define BCUROMSPEED_ATIME_9VT   (0x6) /* 9VTClock */

Definition at line 187 of file bcureg.h.

◆ BCUROMSPEED_PATIME

#define BCUROMSPEED_PATIME   (0x3<<12) /* Page Access time */

Definition at line 171 of file bcureg.h.

◆ BCUROMSPEED_PATIME_2VT

#define BCUROMSPEED_PATIME_2VT   (0x0<<12) /* 2VTClock */

Definition at line 175 of file bcureg.h.

◆ BCUROMSPEED_PATIME_3VT

#define BCUROMSPEED_PATIME_3VT   (0x1<<12) /* 3VTClock */

Definition at line 174 of file bcureg.h.

◆ BCUROMSPEED_PATIME_4VT

#define BCUROMSPEED_PATIME_4VT   (0x2<<12) /* 4VTClock */

Definition at line 173 of file bcureg.h.

◆ BCUROMSPEED_PATIME_5VT

#define BCUROMSPEED_PATIME_5VT   (0x3<<12) /* 5VTClock */

Definition at line 172 of file bcureg.h.

◆ BCUROMSPEED_REG_W

#define BCUROMSPEED_REG_W   0x006 /* BCU ROM Speed Register (=4122, 4131) */

Definition at line 170 of file bcureg.h.

◆ BCUSPD_ISAM1T

#define BCUSPD_ISAM1T   (0x7<<8) /* ISAM 1TClock */

Definition at line 341 of file bcureg.h.

◆ BCUSPD_ISAM2T

#define BCUSPD_ISAM2T   (0x6<<8) /* ISAM 2TClock */

Definition at line 342 of file bcureg.h.

◆ BCUSPD_ISAM3T

#define BCUSPD_ISAM3T   (0x5<<8) /* ISAM 3TClock */

Definition at line 343 of file bcureg.h.

◆ BCUSPD_ISAM4T

#define BCUSPD_ISAM4T   (0x4<<8) /* ISAM 4TClock */

Definition at line 344 of file bcureg.h.

◆ BCUSPD_ISAM5T

#define BCUSPD_ISAM5T   (0x3<<8) /* ISAM 5TClock */

Definition at line 345 of file bcureg.h.

◆ BCUSPD_ISAM6T

#define BCUSPD_ISAM6T   (0x2<<8) /* ISAM 6TClock */

Definition at line 346 of file bcureg.h.

◆ BCUSPD_ISAM7T

#define BCUSPD_ISAM7T   (0x1<<8) /* ISAM 7TClock */

Definition at line 347 of file bcureg.h.

◆ BCUSPD_ISAM8T

#define BCUSPD_ISAM8T   (0x0<<8) /* ISAM 8TClock */

Definition at line 348 of file bcureg.h.

◆ BCUSPD_WISAA

#define BCUSPD_WISAA   (0x7<<4) /* System Bus Access Speed */

Definition at line 350 of file bcureg.h.

◆ BCUSPD_WISAA3T

#define BCUSPD_WISAA3T   (0x5<<4) /* 3TClock */

Definition at line 351 of file bcureg.h.

◆ BCUSPD_WISAA4T

#define BCUSPD_WISAA4T   (0x4<<4) /* 4TClock */

Definition at line 352 of file bcureg.h.

◆ BCUSPD_WISAA5T

#define BCUSPD_WISAA5T   (0x3<<4) /* 5TClock */

Definition at line 353 of file bcureg.h.

◆ BCUSPD_WISAA6T

#define BCUSPD_WISAA6T   (0x2<<4) /* 6TClock */

Definition at line 354 of file bcureg.h.

◆ BCUSPD_WISAA7T

#define BCUSPD_WISAA7T   (0x1<<4) /* 7TClock */

Definition at line 355 of file bcureg.h.

◆ BCUSPD_WISAA8T

#define BCUSPD_WISAA8T   (0x0<<4) /* 8TClock */

Definition at line 356 of file bcureg.h.

◆ BCUSPD_WLCD2T

#define BCUSPD_WLCD2T   (0x3<<8) /* LCD 2TClock */

Definition at line 336 of file bcureg.h.

◆ BCUSPD_WLCD4T

#define BCUSPD_WLCD4T   (0x2<<8) /* LCD 4TClock */

Definition at line 337 of file bcureg.h.

◆ BCUSPD_WLCD6T

#define BCUSPD_WLCD6T   (0x1<<8) /* LCD 6TClock */

Definition at line 338 of file bcureg.h.

◆ BCUSPD_WLCD8T

#define BCUSPD_WLCD8T   (0x0<<8) /* LCD 8TClock */

Definition at line 339 of file bcureg.h.

◆ BCUSPD_WLCDM

#define BCUSPD_WLCDM   (0x7<<8) /* access speed 0x0a000000-0affffff */

Definition at line 329 of file bcureg.h.

◆ BCUSPD_WLCDRFU

#define BCUSPD_WLCDRFU   (0x7<<8) /* LCD RFU */

Definition at line 332 of file bcureg.h.

◆ BCUSPD_WLCDRFU1

#define BCUSPD_WLCDRFU1   (0x6<<8) /* LCD RFU */

Definition at line 333 of file bcureg.h.

◆ BCUSPD_WLCDRFU2

#define BCUSPD_WLCDRFU2   (0x5<<8) /* LCD RFU */

Definition at line 334 of file bcureg.h.

◆ BCUSPD_WLCDRFU3

#define BCUSPD_WLCDRFU3   (0x4<<8) /* LCD RFU */

Definition at line 335 of file bcureg.h.

◆ BCUSPD_WPROM

#define BCUSPD_WPROM   (0x3<<12) /* Page ROM access speed */

Definition at line 323 of file bcureg.h.

◆ BCUSPD_WPROM1T

#define BCUSPD_WPROM1T   (0x2<<12) /* 1TClock */

Definition at line 325 of file bcureg.h.

◆ BCUSPD_WPROM2T

#define BCUSPD_WPROM2T   (0x1<<12) /* 2TClock */

Definition at line 326 of file bcureg.h.

◆ BCUSPD_WPROM3T

#define BCUSPD_WPROM3T   (0x0<<12) /* 3TClock */

Definition at line 327 of file bcureg.h.

◆ BCUSPD_WPROMRFU

#define BCUSPD_WPROMRFU   (0x3<<12) /* RFU */

Definition at line 324 of file bcureg.h.

◆ BCUSPD_WROMA

#define BCUSPD_WROMA   (0x7<<0) /* System Bus Access Speed */

Definition at line 358 of file bcureg.h.

◆ BCUSPD_WROMA2T

#define BCUSPD_WROMA2T   (0x7<<0) /* 2TClock */

Definition at line 359 of file bcureg.h.

◆ BCUSPD_WROMA3T

#define BCUSPD_WROMA3T   (0x6<<0) /* 3TClock */

Definition at line 360 of file bcureg.h.

◆ BCUSPD_WROMA4T

#define BCUSPD_WROMA4T   (0x5<<0) /* 4TClock */

Definition at line 361 of file bcureg.h.

◆ BCUSPD_WROMA5T

#define BCUSPD_WROMA5T   (0x4<<0) /* 5TClock */

Definition at line 362 of file bcureg.h.

◆ BCUSPD_WROMA6T

#define BCUSPD_WROMA6T   (0x3<<0) /* 6TClock */

Definition at line 363 of file bcureg.h.

◆ BCUSPD_WROMA7T

#define BCUSPD_WROMA7T   (0x2<<0) /* 7TClock */

Definition at line 364 of file bcureg.h.

◆ BCUSPD_WROMA8T

#define BCUSPD_WROMA8T   (0x1<<0) /* 8TClock */

Definition at line 365 of file bcureg.h.

◆ BCUSPD_WROMA9T

#define BCUSPD_WROMA9T   (0x0<<0) /* 9TClock */

Definition at line 366 of file bcureg.h.

◆ BCUSPEED_REG_W

#define BCUSPEED_REG_W   0x00A /* BCU Access Cycle Change Register (4121>=4102)*/

Definition at line 321 of file bcureg.h.


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