Go to the source code of this file.
Macros | |
#define | KN02_PHYS_MIN 0x00000000 /* 512 Meg */ |
#define | KN02_PHYS_MAX 0x1fffffff |
#define | KN02_PHYS_MEMORY_START 0x00000000 |
#define | KN02_PHYS_MEMORY_END 0x1dffffff /* 480 Meg in 15 slots */ |
#define | KN02_PHYS_TC_0_START 0x1e000000 /* TURBOchannel, slot 0 */ |
#define | KN02_PHYS_TC_0_END 0x1e3fffff /* 4 Meg, option0 */ |
#define | KN02_PHYS_TC_1_START 0x1e400000 /* TURBOchannel, slot 1 */ |
#define | KN02_PHYS_TC_1_END 0x1e7fffff /* 4 Meg, option1 */ |
#define | KN02_PHYS_TC_2_START 0x1e800000 /* TURBOchannel, slot 2 */ |
#define | KN02_PHYS_TC_2_END 0x1ebfffff /* 4 Meg, option2 */ |
#define | KN02_PHYS_TC_3_START 0x1ec00000 /* TURBOchannel, slot 3 */ |
#define | KN02_PHYS_TC_3_END 0x1effffff /* 4 Meg, reserved*/ |
#define | KN02_PHYS_TC_4_START 0x1f000000 /* TURBOchannel, slot 4 */ |
#define | KN02_PHYS_TC_4_END 0x1f3fffff /* 4 Meg, reserved*/ |
#define | KN02_PHYS_TC_5_START 0x1f400000 /* TURBOchannel, slot 5 */ |
#define | KN02_PHYS_TC_5_END 0x1f7fffff /* 4 Meg, SCSI */ |
#define | KN02_PHYS_TC_6_START 0x1f800000 /* TURBOchannel, slot 6 */ |
#define | KN02_PHYS_TC_6_END 0x1fbfffff /* 4 Meg, ether */ |
#define | KN02_PHYS_TC_7_START 0x1fc00000 /* TURBOchannel, slot 7 */ |
#define | KN02_PHYS_TC_7_END 0x1fffffff /* 4 Meg, system devices */ |
#define | KN02_PHYS_TC_START KN02_PHYS_TC_0_START |
#define | KN02_PHYS_TC_END KN02_PHYS_TC_7_END /* 32 Meg */ |
#define | KN02_TC_NSLOTS 8 |
#define | KN02_TC_MIN 0 |
#define | KN02_TC_MAX 6 /* don't look at system slot */ |
#define | KN02_SYS_ROM_START KN02_PHYS_TC_7_START+0x000000 |
#define | KN02_SYS_ROM_END KN02_PHYS_TC_7_START+0x07ffff |
#define | KN02_SYS_RESERVED KN02_PHYS_TC_7_START+0x080000 |
#define | KN02_SYS_CHKSYN KN02_PHYS_TC_7_START+0x100000 |
#define | KN02_SYS_ERRADR KN02_PHYS_TC_7_START+0x180000 |
#define | KN02_SYS_DZ KN02_PHYS_TC_7_START+0x200000 |
#define | KN02_SYS_CLOCK KN02_PHYS_TC_7_START+0x280000 |
#define | KN02_SYS_CSR KN02_PHYS_TC_7_START+0x300000 |
#define | KN02_SYS_ROM1_START KN02_PHYS_TC_7_START+0x380000 |
#define | KN02_SYS_ROM1_END KN02_PHYS_TC_7_START+0x3fffff |
#define | KN02_INT_FPA IP_LEV7 /* Floating Point coproc */ |
#define | KN02_INT_RES1 IP_LEV6 /* reserved, unused */ |
#define | KN02_INT_MEM IP_LEV5 /* memory controller */ |
#define | KN02_INT_RES2 IP_LEV4 /* reserved, unused */ |
#define | KN02_INT_CLOCK IP_LEV3 /* RTC chip */ |
#define | KN02_INT_IO IP_LEV2 /* I/O slots */ |
#define | KN02_CSR_IOINT 0x000000ff /* ro Interrupt pending */ |
#define | KN02_IP_DZ 0x00000080 /* serial lines */ |
#define | KN02_IP_LANCE 0x00000040 /* thin ethernet */ |
#define | KN02_IP_SCSI 0x00000020 /* ASC scsi controller */ |
#define | KN02_IP_XXXX 0x00000018 /* unused */ |
#define | KN02_IP_SLOT2 0x00000004 /* option slot 2 */ |
#define | KN02_IP_SLOT1 0x00000002 /* option slot 1 */ |
#define | KN02_IP_SLOT0 0x00000001 /* option slot 0 */ |
#define | KN02_CSR_BAUD38 0x00000100 /* rw Max DZ baud rate */ |
#define | KN02_CSR_DIAGDN 0x00000200 /* rw Diag jumper */ |
#define | KN02_CSR_BNK32M 0x00000400 /* rw Memory bank stride */ |
#define | KN02_CSR_TXDIS 0x00000800 /* rw Disable DZ xmit */ |
#define | KN02_CSR_LEDIAG 0x00001000 /* rw Latch ECC */ |
#define | KN02_CSR_CORRECT 0x00002000 /* rw ECC corrects single bit */ |
#define | KN02_CSR_ECCMD 0x0000c000 /* rw ECC logic mode */ |
#define | KN02_CSR_IOINTEN 0x00ff0000 /* rw Interrupt enable */ |
#define | KN02_CSR_IOINTEN_SHIFT 16 |
#define | KN02_CSR_NRMMOD 0x01000000 /* ro Diag jumper state */ |
#define | KN02_CSR_REFEVEN 0x02000000 /* ro Refreshing even mem bank */ |
#define | KN02_CSR_PRSVNVR 0x04000000 /* ro Preserve NVR jumper */ |
#define | KN02_CSR_PSWARN 0x08000000 /* ro PS overheating */ |
#define | KN02_CSR_RRESERVED 0xf0000000 /* rz */ |
#define | KN02_CSR_LEDS 0x000000ff /* wo Diag LEDs */ |
#define | KN02_CSR_WRESERVED 0xff000000 /* wz */ |
#define | KN02_ERR_ADDRESS 0x07ffffff /* phys address */ |
#define | KN02_ERR_RESERVED 0x08000000 /* unused */ |
#define | KN02_ERR_ECCERR 0x10000000 /* ECC error */ |
#define | KN02_ERR_WRITE 0x20000000 /* read/write transaction */ |
#define | KN02_ERR_CPU 0x40000000 /* CPU or device initiator */ |
#define | KN02_ERR_VALID 0x80000000 /* Info is valid */ |
#define | KN02_ECC_SYNLO 0x0000007f /* syndrome, even bank */ |
#define | KN02_ECC_SNGLO 0x00000080 /* single bit err, " */ |
#define | KN02_ECC_CHKLO 0x00007f00 /* check bits, " " */ |
#define | KN02_ECC_VLDLO 0x00008000 /* info valid for " */ |
#define | KN02_ECC_SYNHI 0x007f0000 /* syndrome, odd bank */ |
#define | KN02_ECC_SNGHI 0x00800000 /* single bit err, " */ |
#define | KN02_ECC_CHKHI 0x7f000000 /* check bits, " " */ |
#define | KN02_ECC_VLDHI 0x80000000 /* info valid for " */ |
#define KN02_CSR_BAUD38 0x00000100 /* rw Max DZ baud rate */ |
Definition at line 187 of file dec_kn02.h.
#define KN02_CSR_BNK32M 0x00000400 /* rw Memory bank stride */ |
Definition at line 189 of file dec_kn02.h.
#define KN02_CSR_CORRECT 0x00002000 /* rw ECC corrects single bit */ |
Definition at line 192 of file dec_kn02.h.
#define KN02_CSR_DIAGDN 0x00000200 /* rw Diag jumper */ |
Definition at line 188 of file dec_kn02.h.
#define KN02_CSR_ECCMD 0x0000c000 /* rw ECC logic mode */ |
Definition at line 193 of file dec_kn02.h.
#define KN02_CSR_IOINT 0x000000ff /* ro Interrupt pending */ |
Definition at line 178 of file dec_kn02.h.
#define KN02_CSR_IOINTEN 0x00ff0000 /* rw Interrupt enable */ |
Definition at line 194 of file dec_kn02.h.
#define KN02_CSR_IOINTEN_SHIFT 16 |
Definition at line 195 of file dec_kn02.h.
#define KN02_CSR_LEDIAG 0x00001000 /* rw Latch ECC */ |
Definition at line 191 of file dec_kn02.h.
#define KN02_CSR_LEDS 0x000000ff /* wo Diag LEDs */ |
Definition at line 202 of file dec_kn02.h.
#define KN02_CSR_NRMMOD 0x01000000 /* ro Diag jumper state */ |
Definition at line 196 of file dec_kn02.h.
Referenced by DEVINIT().
#define KN02_CSR_PRSVNVR 0x04000000 /* ro Preserve NVR jumper */ |
Definition at line 198 of file dec_kn02.h.
#define KN02_CSR_PSWARN 0x08000000 /* ro PS overheating */ |
Definition at line 199 of file dec_kn02.h.
#define KN02_CSR_REFEVEN 0x02000000 /* ro Refreshing even mem bank */ |
Definition at line 197 of file dec_kn02.h.
#define KN02_CSR_RRESERVED 0xf0000000 /* rz */ |
Definition at line 200 of file dec_kn02.h.
#define KN02_CSR_TXDIS 0x00000800 /* rw Disable DZ xmit */ |
Definition at line 190 of file dec_kn02.h.
#define KN02_CSR_WRESERVED 0xff000000 /* wz */ |
Definition at line 203 of file dec_kn02.h.
#define KN02_ECC_CHKHI 0x7f000000 /* check bits, " " */ |
Definition at line 220 of file dec_kn02.h.
#define KN02_ECC_CHKLO 0x00007f00 /* check bits, " " */ |
Definition at line 216 of file dec_kn02.h.
#define KN02_ECC_SNGHI 0x00800000 /* single bit err, " */ |
Definition at line 219 of file dec_kn02.h.
#define KN02_ECC_SNGLO 0x00000080 /* single bit err, " */ |
Definition at line 215 of file dec_kn02.h.
#define KN02_ECC_SYNHI 0x007f0000 /* syndrome, odd bank */ |
Definition at line 218 of file dec_kn02.h.
#define KN02_ECC_SYNLO 0x0000007f /* syndrome, even bank */ |
Definition at line 214 of file dec_kn02.h.
#define KN02_ECC_VLDHI 0x80000000 /* info valid for " */ |
Definition at line 221 of file dec_kn02.h.
#define KN02_ECC_VLDLO 0x00008000 /* info valid for " */ |
Definition at line 217 of file dec_kn02.h.
#define KN02_ERR_ADDRESS 0x07ffffff /* phys address */ |
Definition at line 206 of file dec_kn02.h.
#define KN02_ERR_CPU 0x40000000 /* CPU or device initiator */ |
Definition at line 210 of file dec_kn02.h.
#define KN02_ERR_ECCERR 0x10000000 /* ECC error */ |
Definition at line 208 of file dec_kn02.h.
#define KN02_ERR_RESERVED 0x08000000 /* unused */ |
Definition at line 207 of file dec_kn02.h.
#define KN02_ERR_VALID 0x80000000 /* Info is valid */ |
Definition at line 211 of file dec_kn02.h.
#define KN02_ERR_WRITE 0x20000000 /* read/write transaction */ |
Definition at line 209 of file dec_kn02.h.
#define KN02_INT_CLOCK IP_LEV3 /* RTC chip */ |
Definition at line 171 of file dec_kn02.h.
Referenced by MACHINE_SETUP().
#define KN02_INT_FPA IP_LEV7 /* Floating Point coproc */ |
Definition at line 167 of file dec_kn02.h.
Definition at line 172 of file dec_kn02.h.
Definition at line 169 of file dec_kn02.h.
#define KN02_INT_RES1 IP_LEV6 /* reserved, unused */ |
Definition at line 168 of file dec_kn02.h.
#define KN02_INT_RES2 IP_LEV4 /* reserved, unused */ |
Definition at line 170 of file dec_kn02.h.
#define KN02_IP_DZ 0x00000080 /* serial lines */ |
Definition at line 179 of file dec_kn02.h.
#define KN02_IP_LANCE 0x00000040 /* thin ethernet */ |
Definition at line 180 of file dec_kn02.h.
#define KN02_IP_SCSI 0x00000020 /* ASC scsi controller */ |
Definition at line 181 of file dec_kn02.h.
#define KN02_IP_SLOT0 0x00000001 /* option slot 0 */ |
Definition at line 185 of file dec_kn02.h.
#define KN02_IP_SLOT1 0x00000002 /* option slot 1 */ |
Definition at line 184 of file dec_kn02.h.
#define KN02_IP_SLOT2 0x00000004 /* option slot 2 */ |
Definition at line 183 of file dec_kn02.h.
#define KN02_IP_XXXX 0x00000018 /* unused */ |
Definition at line 182 of file dec_kn02.h.
#define KN02_PHYS_MAX 0x1fffffff |
Definition at line 108 of file dec_kn02.h.
#define KN02_PHYS_MEMORY_END 0x1dffffff /* 480 Meg in 15 slots */ |
Definition at line 114 of file dec_kn02.h.
#define KN02_PHYS_MEMORY_START 0x00000000 |
Definition at line 113 of file dec_kn02.h.
#define KN02_PHYS_MIN 0x00000000 /* 512 Meg */ |
Definition at line 107 of file dec_kn02.h.
#define KN02_PHYS_TC_0_END 0x1e3fffff /* 4 Meg, option0 */ |
Definition at line 120 of file dec_kn02.h.
Referenced by MACHINE_SETUP().
#define KN02_PHYS_TC_0_START 0x1e000000 /* TURBOchannel, slot 0 */ |
Definition at line 119 of file dec_kn02.h.
Referenced by MACHINE_SETUP().
#define KN02_PHYS_TC_1_END 0x1e7fffff /* 4 Meg, option1 */ |
Definition at line 123 of file dec_kn02.h.
Referenced by MACHINE_SETUP().
#define KN02_PHYS_TC_1_START 0x1e400000 /* TURBOchannel, slot 1 */ |
Definition at line 122 of file dec_kn02.h.
Referenced by MACHINE_SETUP().
#define KN02_PHYS_TC_2_END 0x1ebfffff /* 4 Meg, option2 */ |
Definition at line 126 of file dec_kn02.h.
Referenced by MACHINE_SETUP().
#define KN02_PHYS_TC_2_START 0x1e800000 /* TURBOchannel, slot 2 */ |
Definition at line 125 of file dec_kn02.h.
Referenced by MACHINE_SETUP().
#define KN02_PHYS_TC_3_END 0x1effffff /* 4 Meg, reserved*/ |
Definition at line 129 of file dec_kn02.h.
#define KN02_PHYS_TC_3_START 0x1ec00000 /* TURBOchannel, slot 3 */ |
Definition at line 128 of file dec_kn02.h.
#define KN02_PHYS_TC_4_END 0x1f3fffff /* 4 Meg, reserved*/ |
Definition at line 132 of file dec_kn02.h.
#define KN02_PHYS_TC_4_START 0x1f000000 /* TURBOchannel, slot 4 */ |
Definition at line 131 of file dec_kn02.h.
#define KN02_PHYS_TC_5_END 0x1f7fffff /* 4 Meg, SCSI */ |
Definition at line 135 of file dec_kn02.h.
Referenced by MACHINE_SETUP().
#define KN02_PHYS_TC_5_START 0x1f400000 /* TURBOchannel, slot 5 */ |
Definition at line 134 of file dec_kn02.h.
Referenced by MACHINE_SETUP().
#define KN02_PHYS_TC_6_END 0x1fbfffff /* 4 Meg, ether */ |
Definition at line 138 of file dec_kn02.h.
Referenced by MACHINE_SETUP().
#define KN02_PHYS_TC_6_START 0x1f800000 /* TURBOchannel, slot 6 */ |
Definition at line 137 of file dec_kn02.h.
Referenced by MACHINE_SETUP().
#define KN02_PHYS_TC_7_END 0x1fffffff /* 4 Meg, system devices */ |
Definition at line 141 of file dec_kn02.h.
#define KN02_PHYS_TC_7_START 0x1fc00000 /* TURBOchannel, slot 7 */ |
Definition at line 140 of file dec_kn02.h.
#define KN02_PHYS_TC_END KN02_PHYS_TC_7_END /* 32 Meg */ |
Definition at line 144 of file dec_kn02.h.
#define KN02_PHYS_TC_START KN02_PHYS_TC_0_START |
Definition at line 143 of file dec_kn02.h.
#define KN02_SYS_CHKSYN KN02_PHYS_TC_7_START+0x100000 |
Definition at line 156 of file dec_kn02.h.
#define KN02_SYS_CLOCK KN02_PHYS_TC_7_START+0x280000 |
Definition at line 159 of file dec_kn02.h.
Referenced by MACHINE_SETUP().
#define KN02_SYS_CSR KN02_PHYS_TC_7_START+0x300000 |
Definition at line 160 of file dec_kn02.h.
Referenced by MACHINE_SETUP().
#define KN02_SYS_DZ KN02_PHYS_TC_7_START+0x200000 |
Definition at line 158 of file dec_kn02.h.
Referenced by MACHINE_SETUP().
#define KN02_SYS_ERRADR KN02_PHYS_TC_7_START+0x180000 |
Definition at line 157 of file dec_kn02.h.
#define KN02_SYS_RESERVED KN02_PHYS_TC_7_START+0x080000 |
Definition at line 155 of file dec_kn02.h.
#define KN02_SYS_ROM1_END KN02_PHYS_TC_7_START+0x3fffff |
Definition at line 162 of file dec_kn02.h.
#define KN02_SYS_ROM1_START KN02_PHYS_TC_7_START+0x380000 |
Definition at line 161 of file dec_kn02.h.
#define KN02_SYS_ROM_END KN02_PHYS_TC_7_START+0x07ffff |
Definition at line 154 of file dec_kn02.h.
#define KN02_SYS_ROM_START KN02_PHYS_TC_7_START+0x000000 |
Definition at line 153 of file dec_kn02.h.
#define KN02_TC_MAX 6 /* don't look at system slot */ |
Definition at line 148 of file dec_kn02.h.
#define KN02_TC_MIN 0 |
Definition at line 147 of file dec_kn02.h.
#define KN02_TC_NSLOTS 8 |
Definition at line 146 of file dec_kn02.h.