luna88k_board.h Source File
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Go to the documentation of this file. 31 #ifndef _MACHINE_BOARD_H_ 32 #define _MACHINE_BOARD_H_ 44 #elif defined(__STDC__) 45 #define U(num) num ## U 54 #define MAXPHYSMEM U(0x10000000) 56 #define PROM_ADDR U(0x41000000) 57 #define PROM_SPACE U(0x00040000) 58 #define NVRAM_ADDR U(0x45000000) 59 #define NVRAM_SPACE U(0x00001FDC) 60 #define FUSE_ROM_ADDR U(0x43000000) 61 #define FUSE_ROM_SPACE 1024 62 #define OBIO_CAL_CTL U(0x45001FE0) 63 #define OBIO_CAL_SEC U(0x45001FE4) 64 #define OBIO_CAL_MIN U(0x45001FE8) 65 #define OBIO_CAL_HOUR U(0x45001FEC) 66 #define OBIO_CAL_DOW U(0x45001FF0) 67 #define OBIO_CAL_DAY U(0x45001FF4) 68 #define OBIO_CAL_MON U(0x45001FF8) 69 #define OBIO_CAL_YEAR U(0x45001FFC) 70 #define NVRAM_ADDR_88K2 U(0x47000000) 71 #define OBIO_PIO0_BASE U(0x49000000) 72 #define OBIO_PIO0_SPACE U(0x0000000C) 73 #define OBIO_PIO0A U(0x49000000) 74 #define OBIO_PIO0B U(0x49000004) 75 #define OBIO_PIO0C U(0x49000008) 76 #define OBIO_PIO0 U(0x4900000C) 77 #define OBIO_PIO1_BASE U(0x4D000000) 78 #define OBIO_PIO1_SPACE U(0x0000000C) 79 #define OBIO_PIO1A U(0x4D000000) 80 #define OBIO_PIO1B U(0x4D000004) 81 #define OBIO_PIO1C U(0x4D000008) 82 #define OBIO_PIO1 U(0x4D00000C) 83 #define OBIO_SIO U(0x51000000) 84 #define OBIO_TAS U(0x61000000) 85 #define OBIO_CLOCK0 U(0x63000000) 86 #define OBIO_CLOCK1 U(0x63000004) 87 #define OBIO_CLOCK2 U(0x63000008) 88 #define OBIO_CLOCK3 U(0x6300000C) 89 #define OBIO_CLK_INTR 31 90 #define INT_ST_MASK0 U(0x65000000) 91 #define INT_ST_MASK1 U(0x65000004) 92 #define INT_ST_MASK2 U(0x65000008) 93 #define INT_ST_MASK3 U(0x6500000C) 95 #define INT_SET_LV7 U(0x00000000) 96 #define INT_SET_LV6 U(0x00000000) 97 #define INT_SET_LV5 U(0x84000000) 98 #define INT_SET_LV4 U(0xC4000000) 99 #define INT_SET_LV3 U(0xE4000000) 100 #define INT_SET_LV2 U(0xF4000000) 101 #define INT_SET_LV1 U(0xFC000000) 102 #define INT_SET_LV0 U(0xFC000000) 103 #define INT_SLAVE_MASK U(0x84000000) 105 #define SOFT_INT0 U(0x69000000) 106 #define SOFT_INT1 U(0x69000004) 107 #define SOFT_INT2 U(0x69000008) 108 #define SOFT_INT3 U(0x6900000C) 109 #define SOFT_INT_FLAG0 U(0x6B000000) 110 #define SOFT_INT_FLAG1 U(0x6B000000) 111 #define SOFT_INT_FLAG2 U(0x6B000000) 112 #define SOFT_INT_FLAG3 U(0x6B000000) 113 #define RESET_CPU0 U(0x6D000000) 114 #define RESET_CPU1 U(0x6D000004) 115 #define RESET_CPU2 U(0x6D000008) 116 #define RESET_CPU3 U(0x6D00000C) 117 #define RESET_CPU_ALL U(0x6D000010) 118 #define TRI_PORT_RAM U(0x71000000) 119 #define TRI_PORT_RAM_SPACE 0x20000 120 #define EXT_A_ADDR U(0x81000000) 121 #define EXT_A_SPACE U(0x02000000) 122 #define EXT_B_ADDR U(0x83000000) 123 #define EXT_B_SPACE U(0x01000000) 124 #define PC_BASE U(0x90000000) 125 #define PC_SPACE U(0x02000000) 127 #define MROM_ADDR U(0xA1000000) 128 #define MROM_SPACE 0x400000 129 #define BMAP_START U(0xB1000000) 130 #define BMAP_SPACE (BMAP_END - BMAP_START) 131 #define BMAP_RFCNT U(0xB1000000) 132 #define BMAP_BMSEL U(0xB1040000) 133 #define BMAP_BMP U(0xB1080000) 134 #define BMAP_BMAP0 U(0xB10C0000) 135 #define BMAP_BMAP1 U(0xB1100000) 136 #define BMAP_BMAP2 U(0xB1140000) 137 #define BMAP_BMAP3 U(0xB1180000) 138 #define BMAP_BMAP4 U(0xB11C0000) 139 #define BMAP_BMAP5 U(0xB1200000) 140 #define BMAP_BMAP6 U(0xB1240000) 141 #define BMAP_BMAP7 U(0xB1280000) 142 #define BMAP_FN U(0xB12C0000) 143 #define BMAP_FN0 U(0xB1300000) 144 #define BMAP_FN1 U(0xB1340000) 145 #define BMAP_FN2 U(0xB1380000) 146 #define BMAP_FN3 U(0xB13C0000) 147 #define BMAP_FN4 U(0xB1400000) 148 #define BMAP_FN5 U(0xB1440000) 149 #define BMAP_FN6 U(0xB1480000) 150 #define BMAP_FN7 U(0xB14C0000) 151 #define BMAP_END U(0xB1500000) 152 #define BMAP_END24P U(0xB1800000) 153 #define BMAP_PALLET0 U(0xC0000000) 154 #define BMAP_PALLET1 U(0xC1000000) 155 #define BMAP_PALLET2 U(0xC1100000) 156 #define BOARD_CHECK_REG U(0xD0000000) 157 #define BMAP_CRTC U(0xD1000000) 158 #define BMAP_IDENTROM U(0xD1800000) 159 #define SCSI_ADDR U(0xE1000000) 160 #define LANCE_ADDR U(0xF1000000) 162 #define CMMU_I0 U(0xFFF07000) 163 #define CMMU_D0 U(0xFFF06000) 164 #define CMMU_I1 U(0xFFF05000) 165 #define CMMU_D1 U(0xFFF04000) 166 #define CMMU_I2 U(0xFFF03000) 167 #define CMMU_D2 U(0xFFF02000) 168 #define CMMU_I3 U(0xFFF01000) 169 #define CMMU_D3 U(0xFFF00000)
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