dev_algor.cc Source File

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dev_algor.cc
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1 /*
2  * Copyright (C) 2005-2009 Anders Gavare. All rights reserved.
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions are met:
6  *
7  * 1. Redistributions of source code must retain the above copyright
8  * notice, this list of conditions and the following disclaimer.
9  * 2. Redistributions in binary form must reproduce the above copyright
10  * notice, this list of conditions and the following disclaimer in the
11  * documentation and/or other materials provided with the distribution.
12  * 3. The name of the author may not be used to endorse or promote products
13  * derived from this software without specific prior written permission.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25  * SUCH DAMAGE.
26  *
27  *
28  * COMMENT: Algor P5064 misc. stuff
29  *
30  * TODO: This is hardcoded for P5064 right now. Generalize it to P40xx etc.
31  *
32  * CPU irq 2 = ISA, 3 = PCI, 4 = Local.
33  */
34 
35 #include <stdio.h>
36 #include <stdlib.h>
37 #include <string.h>
38 
39 #include "cpu.h"
40 #include "device.h"
41 #include "devices.h"
42 #include "interrupt.h"
43 #include "machine.h"
44 #include "memory.h"
45 #include "misc.h"
46 
48 
49 
50 struct algor_data {
51  uint64_t base_addr;
55 };
56 
57 
59 {
60  struct algor_data *d = (struct algor_data *) extra;
61  uint64_t idata = 0, odata = 0;
62  const char *n = NULL;
63 
64  if (writeflag == MEM_WRITE)
65  idata = memory_readmax64(cpu, data, len);
66 
67  relative_addr += d->base_addr;
68 
69  switch (relative_addr) {
70 
71  case P5064_LED1 + 0x0:
72  case P5064_LED1 + 0x4:
73  case P5064_LED1 + 0x8:
74  case P5064_LED1 + 0xc:
75  break;
76 
77  case P5064_LOCINT:
78  /*
79  * TODO: See how ISAINT is implemented.
80  *
81  * Implemented so far: COM1 only.
82  */
83  n = "P5064_LOCINT";
84  if (writeflag == MEM_READ) {
85  /* Ugly hack for NetBSD startup. TODO: fix */
86  static int x = 0;
87  if (((++ x) & 0xffff) == 0)
88  odata |= LOCINT_RTC;
89 
91  ~cpu->machine->isa_pic_data.pic1->ier & 0x10)
92  odata |= LOCINT_COM1;
94  ~cpu->machine->isa_pic_data.pic1->ier & 0x08)
95  odata |= LOCINT_COM2;
96 
97  /* Read => ack: */
98  cpu->machine->isa_pic_data.pic1->irr &= ~0x18;
100  } else {
101  if (idata & LOCINT_COM1)
102  cpu->machine->isa_pic_data.pic1->ier &= ~0x10;
103  else
104  cpu->machine->isa_pic_data.pic1->ier |= 0x10;
105  if (idata & LOCINT_COM2)
106  cpu->machine->isa_pic_data.pic1->ier &= ~0x08;
107  else
108  cpu->machine->isa_pic_data.pic1->ier |= 0x08;
109  }
110  break;
111 
112  case P5064_PANIC:
113  n = "P5064_PANIC";
114  if (writeflag == MEM_READ)
115  odata = 0;
116  break;
117 
118  case P5064_PCIINT:
119  /*
120  * TODO: See how ISAINT is implemented.
121  */
122  n = "P5064_PCIINT";
123  if (writeflag == MEM_READ) {
124  odata = 0;
126  }
127  break;
128 
129  case P5064_ISAINT:
130  /*
131  * ISA interrupts:
132  *
133  * Bit: IRQ Source:
134  * 0 ISAINT_ISABR
135  * 1 ISAINT_IDE0
136  * 2 ISAINT_IDE1
137  *
138  * NOTE/TODO: Ugly redirection to the ISA controller.
139  */
140  n = "P5064_ISAINT";
141  if (writeflag == MEM_WRITE) {
142  if (idata & ISAINT_IDE0)
143  cpu->machine->isa_pic_data.pic2->ier &= ~0x40;
144  else
145  cpu->machine->isa_pic_data.pic2->ier |= 0x40;
146  if (idata & ISAINT_IDE1)
147  cpu->machine->isa_pic_data.pic2->ier &= ~0x80;
148  else
149  cpu->machine->isa_pic_data.pic2->ier |= 0x80;
150  cpu->machine->isa_pic_data.pic1->ier &= ~0x04;
151  } else {
152  if (cpu->machine->isa_pic_data.pic2->irr &
153  ~cpu->machine->isa_pic_data.pic2->ier & 0x40)
154  odata |= ISAINT_IDE0;
155  if (cpu->machine->isa_pic_data.pic2->irr &
156  ~cpu->machine->isa_pic_data.pic2->ier & 0x80)
157  odata |= ISAINT_IDE1;
158 
159  /* Read => ack: */
160  cpu->machine->isa_pic_data.pic2->irr &= ~0xc0;
162  }
163  break;
164 
165  case P5064_KBDINT:
166  /*
167  * TODO: See how ISAINT is implemented.
168  */
169  n = "P5064_KBDINT";
170  if (writeflag == MEM_READ)
171  odata = 0;
172  break;
173 
174  default:if (writeflag == MEM_READ) {
175  fatal("[ algor: read from 0x%x ]\n",
176  (int)relative_addr);
177  } else {
178  fatal("[ algor: write to 0x%x: 0x%" PRIx64" ]\n",
179  (int) relative_addr, (uint64_t) idata);
180  }
181  }
182 
183  if (n != NULL) {
184  if (writeflag == MEM_READ) {
185  debug("[ algor: read from %s: 0x%" PRIx64" ]\n",
186  n, (uint64_t) odata);
187  } else {
188  debug("[ algor: write to %s: 0x%" PRIx64" ]\n",
189  n, (uint64_t) idata);
190  }
191  }
192 
193  if (writeflag == MEM_READ)
194  memory_writemax64(cpu, data, len, odata);
195 
196  return 1;
197 }
198 
199 
200 DEVINIT(algor)
201 {
202  char tmpstr[200];
203  struct algor_data *d;
204 
205  CHECK_ALLOCATION(d = (struct algor_data *) malloc(sizeof(struct algor_data)));
206  memset(d, 0, sizeof(struct algor_data));
207 
208  d->base_addr = devinit->addr;
209  if (devinit->addr != 0x1ff00000) {
210  fatal("The Algor base address should be 0x1ff00000.\n");
211  exit(1);
212  }
213 
214  /* Connect to MIPS irq 2, 3, and 4: */
215  snprintf(tmpstr, sizeof(tmpstr), "%s.2", devinit->interrupt_path);
216  INTERRUPT_CONNECT(tmpstr, d->mips_irq_2);
217  snprintf(tmpstr, sizeof(tmpstr), "%s.3", devinit->interrupt_path);
218  INTERRUPT_CONNECT(tmpstr, d->mips_irq_3);
219  snprintf(tmpstr, sizeof(tmpstr), "%s.4", devinit->interrupt_path);
220  INTERRUPT_CONNECT(tmpstr, d->mips_irq_4);
221 
223  devinit->addr, 0x100000, dev_algor_access, d, DM_DEFAULT, NULL);
224 
225  devinit->return_ptr = d;
226 
227  return 1;
228 }
229 
uint64_t memory_readmax64(struct cpu *cpu, unsigned char *buf, int len)
Definition: memory.cc:55
void fatal(const char *fmt,...)
Definition: main.cc:152
struct interrupt mips_irq_4
Definition: dev_algor.cc:54
#define DM_DEFAULT
Definition: memory.h:130
struct interrupt mips_irq_2
Definition: dev_algor.cc:52
DEVINIT(algor)
Definition: dev_algor.cc:200
char * name
Definition: device.h:43
#define LOCINT_RTC
#define LOCINT_COM2
struct machine * machine
Definition: cpu.h:328
#define MEM_READ
Definition: memory.h:116
struct memory * memory
Definition: machine.h:126
#define ISAINT_IDE0
void * return_ptr
Definition: device.h:56
#define P5064_LOCINT
#define LOCINT_COM1
#define P5064_LED1
struct isa_pic_data isa_pic_data
Definition: machine.h:190
#define CHECK_ALLOCATION(ptr)
Definition: misc.h:239
uint8_t irr
Definition: devices.h:72
u_short data
Definition: siireg.h:79
struct pic8259_data * pic1
Definition: machine.h:48
#define MEM_WRITE
Definition: memory.h:117
#define P5064_KBDINT
#define P5064_PCIINT
Definition: device.h:40
#define ISAINT_IDE1
uint64_t base_addr
Definition: dev_algor.cc:51
#define debug
Definition: dev_adb.cc:57
#define INTERRUPT_CONNECT(name, istruct)
Definition: interrupt.h:77
Definition: cpu.h:326
struct machine * machine
Definition: device.h:41
void memory_writemax64(struct cpu *cpu, unsigned char *buf, int len, uint64_t data)
Definition: memory.cc:89
#define P5064_ISAINT
void memory_device_register(struct memory *mem, const char *, uint64_t baseaddr, uint64_t len, int(*f)(struct cpu *, struct memory *, uint64_t, unsigned char *, size_t, int, void *), void *extra, int flags, unsigned char *dyntrans_data)
Definition: memory.cc:339
struct interrupt mips_irq_3
Definition: dev_algor.cc:53
uint8_t ier
Definition: devices.h:74
struct pic8259_data * pic2
Definition: machine.h:49
#define P5064_PANIC
uint64_t addr
Definition: device.h:46
DEVICE_ACCESS(algor)
Definition: dev_algor.cc:58
char * interrupt_path
Definition: device.h:50
#define INTERRUPT_DEASSERT(istruct)
Definition: interrupt.h:75

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