dev_footbridge.cc Source File

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dev_footbridge.cc
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1 /*
2  * Copyright (C) 2005-2009 Anders Gavare. All rights reserved.
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions are met:
6  *
7  * 1. Redistributions of source code must retain the above copyright
8  * notice, this list of conditions and the following disclaimer.
9  * 2. Redistributions in binary form must reproduce the above copyright
10  * notice, this list of conditions and the following disclaimer in the
11  * documentation and/or other materials provided with the distribution.
12  * 3. The name of the author may not be used to endorse or promote products
13  * derived from this software without specific prior written permission.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25  * SUCH DAMAGE.
26  *
27  *
28  * COMMENT: DC21285 "Footbridge" controller; used in Netwinder and Cats
29  *
30  * TODO:
31  * o) Add actual support for the fcom serial port.
32  * o) FIQs.
33  * o) Pretty much everything else as well :) (This entire thing
34  * is a quick hack to work primarily with NetBSD and OpenBSD
35  * as guest OSes.)
36  */
37 
38 #include <stdio.h>
39 #include <stdlib.h>
40 #include <string.h>
41 
42 #include "bus_pci.h"
43 #include "console.h"
44 #include "cpu.h"
45 #include "device.h"
46 #include "devices.h"
47 #include "machine.h"
48 #include "memory.h"
49 #include "misc.h"
50 #include "timer.h"
51 
52 #include "thirdparty/dc21285reg.h"
53 
54 
55 #define DEV_FOOTBRIDGE_TICK_SHIFT 14
56 #define DEV_FOOTBRIDGE_LENGTH 0x400
57 
58 #define N_FOOTBRIDGE_TIMERS 4
59 
61  struct interrupt irq;
62 
63  struct pci_data *pcibus;
64 
66 
70 
74 
76 
77  uint32_t irq_status;
78  uint32_t irq_enable;
79 
80  uint32_t fiq_status;
81  uint32_t fiq_enable;
82 };
83 
84 
85 static void timer_tick0(struct timer *t, void *extra)
86 { ((struct footbridge_data *)extra)->pending_timer_interrupts[0] ++; }
87 static void timer_tick1(struct timer *t, void *extra)
88 { ((struct footbridge_data *)extra)->pending_timer_interrupts[1] ++; }
89 static void timer_tick2(struct timer *t, void *extra)
90 { ((struct footbridge_data *)extra)->pending_timer_interrupts[2] ++; }
91 static void timer_tick3(struct timer *t, void *extra)
92 { ((struct footbridge_data *)extra)->pending_timer_interrupts[3] ++; }
93 
94 
95 static void reload_timer_value(struct cpu *cpu, struct footbridge_data *d,
96  int timer_nr)
97 {
98  double freq = (double)cpu->machine->emulated_hz;
99  int cycles = d->timer_load[timer_nr];
100 
101  if (d->timer_control[timer_nr] & TIMER_FCLK_16)
102  cycles <<= 4;
103  else if (d->timer_control[timer_nr] & TIMER_FCLK_256)
104  cycles <<= 8;
105  freq /= (double)cycles;
106 
107  d->timer_value[timer_nr] = d->timer_load[timer_nr];
108 
109  /* printf("%i: %i -> %f Hz\n", timer_nr,
110  d->timer_load[timer_nr], freq); */
111 
112  if (d->timer[timer_nr] == NULL) {
113  switch (timer_nr) {
114  case 0: d->timer[0] = timer_add(freq, timer_tick0, d); break;
115  case 1: d->timer[1] = timer_add(freq, timer_tick1, d); break;
116  case 2: d->timer[2] = timer_add(freq, timer_tick2, d); break;
117  case 3: d->timer[3] = timer_add(freq, timer_tick3, d); break;
118  }
119  } else {
120  timer_update_frequency(d->timer[timer_nr], freq);
121  }
122 }
123 
124 
125 /*
126  * The 4 footbridge timers should decrease and cause interrupts. Periodic
127  * interrupts restart as soon as they are acknowledged, non-periodic
128  * interrupts need to be "reloaded" to restart.
129  *
130  * TODO: Hm. I thought I had solved this, but it didn't quite work.
131  * This needs to be re-checked against documentation, sometime.
132  */
133 DEVICE_TICK(footbridge)
134 {
135  struct footbridge_data *d = (struct footbridge_data *) extra;
136  int i;
137 
138  for (i=0; i<N_FOOTBRIDGE_TIMERS; i++) {
139  if (d->timer_control[i] & TIMER_ENABLE) {
140  if (d->pending_timer_interrupts[i] > 0) {
141  d->timer_value[i] = random() % d->timer_load[i];
143  }
144  }
145  }
146 }
147 
148 
149 /*
150  * footbridge_interrupt_assert():
151  */
153 {
154  struct footbridge_data *d = (struct footbridge_data *) interrupt->extra;
155  d->irq_status |= interrupt->line;
156 
157  if ((d->irq_status & d->irq_enable) && !d->irq_asserted) {
158  d->irq_asserted = 1;
159  INTERRUPT_ASSERT(d->irq);
160  }
161 }
162 
163 
164 /*
165  * footbridge_interrupt_deassert():
166  */
168 {
169  struct footbridge_data *d = (struct footbridge_data *) interrupt->extra;
170  d->irq_status &= ~interrupt->line;
171 
172  if (!(d->irq_status & d->irq_enable) && d->irq_asserted) {
173  d->irq_asserted = 0;
175  }
176 }
177 
178 
179 /*
180  * Reading the byte at 0x79000000 is a quicker way to figure out which ISA
181  * interrupt has occurred (and acknowledging it at the same time), than
182  * dealing with the legacy 0x20/0xa0 ISA ports.
183  */
184 DEVICE_ACCESS(footbridge_isa)
185 {
186  /* struct footbridge_data *d = extra; */
187  uint64_t idata = 0, odata = 0;
188  int x;
189 
190  if (writeflag == MEM_WRITE) {
191  idata = memory_readmax64(cpu, data, len);
192  fatal("[ footbridge_isa: WARNING/TODO: write! ]\n");
193  }
194 
195  x = cpu->machine->isa_pic_data.last_int;
196  if (x < 8)
197  odata = cpu->machine->isa_pic_data.pic1->irq_base + x;
198  else
199  odata = cpu->machine->isa_pic_data.pic2->irq_base + x - 8;
200 
201  if (writeflag == MEM_READ)
202  memory_writemax64(cpu, data, len, odata);
203 
204  return 1;
205 }
206 
207 
208 /*
209  * Reset pin at ISA port 0x338, at least in the NetWinder:
210  *
211  * TODO: NOT WORKING YET!
212  */
213 DEVICE_ACCESS(footbridge_reset)
214 {
215  uint64_t idata = 0;
216 
217  if (writeflag == MEM_WRITE) {
218  idata = memory_readmax64(cpu, data, len);
219  if (idata & 0x40) {
220  debug("[ footbridge_reset: GP16: Halting. ]\n");
221  cpu->running = 0;
222 exit(1);
223  }
224  }
225 
226  return 1;
227 }
228 
229 
230 /*
231  * The Footbridge PCI configuration space is implemented as a direct memory
232  * space (i.e. not one port for addr and one port for data). This function
233  * translates that into bus_pci calls.
234  */
235 DEVICE_ACCESS(footbridge_pci)
236 {
237  struct footbridge_data *d = (struct footbridge_data *) extra;
238  uint64_t idata = 0, odata = 0;
239  int bus, dev, func, reg;
240 
241  if (writeflag == MEM_WRITE)
242  idata = memory_readmax64(cpu, data, len|MEM_PCI_LITTLE_ENDIAN);
243 
244  /* Decompose the (direct) address into its components: */
245  bus_pci_decompose_1(relative_addr, &bus, &dev, &func, &reg);
246  bus_pci_setaddr(cpu, d->pcibus, bus, dev, func, reg);
247 
248  if (bus == 255) {
249  fatal("[ footbridge DEBUG ERROR: bus 255 unlikely,"
250  " pc (might not be updated) = 0x%08x ]\n", (int)cpu->pc);
251  exit(1);
252  }
253 
254  debug("[ footbridge pci: %s bus %i, device %i, function %i, register "
255  "%i ]\n", writeflag == MEM_READ? "read from" : "write to", bus,
256  dev, func, reg);
257 
258  bus_pci_data_access(cpu, d->pcibus, writeflag == MEM_READ?
259  &odata : &idata, len, writeflag);
260 
261  if (writeflag == MEM_READ)
262  memory_writemax64(cpu, data, len|MEM_PCI_LITTLE_ENDIAN, odata);
263 
264  return 1;
265 }
266 
267 
268 DEVICE_ACCESS(footbridge)
269 {
270  struct footbridge_data *d = (struct footbridge_data *) extra;
271  uint64_t idata = 0, odata = 0;
272  int timer_nr = 0;
273 
274  if (writeflag == MEM_WRITE)
275  idata = memory_readmax64(cpu, data, len);
276 
277  if (relative_addr >= TIMER_1_LOAD && relative_addr <= TIMER_4_CLEAR) {
278  timer_nr = (relative_addr >> 5) & (N_FOOTBRIDGE_TIMERS - 1);
279  relative_addr &= ~0x060;
280  }
281 
282  switch (relative_addr) {
283 
284  case VENDOR_ID:
285  odata = 0x1011; /* DC21285_VENDOR_ID */
286  break;
287 
288  case DEVICE_ID:
289  odata = 0x1065; /* DC21285_DEVICE_ID */
290  break;
291 
292  case 0x04:
293  case 0x0c:
294  case 0x10:
295  case 0x14:
296  case 0x18:
297  /* TODO. Written to by Linux. */
298  break;
299 
300  case REVISION:
301  odata = 3; /* footbridge revision number */
302  break;
303 
305  /* TODO: Written to by Linux. */
306  if (writeflag == MEM_WRITE && idata != 0)
307  fatal("[ footbridge: TODO: write to PCI_ADDRESS_"
308  "EXTENSION: 0x%llx ]\n", (long long)idata);
309  break;
310 
311  case SA_CONTROL:
312  /* Read by Linux: */
313  odata = PCI_CENTRAL_FUNCTION;
314  break;
315 
316  case UART_DATA:
317  if (writeflag == MEM_WRITE)
318  console_putchar(d->console_handle, idata);
319  break;
320 
321  case UART_RX_STAT:
322  /* TODO */
323  odata = 0;
324  break;
325 
326  case UART_FLAGS:
327  odata = UART_TX_EMPTY;
328  break;
329 
330  case IRQ_STATUS:
331  if (writeflag == MEM_READ)
332  odata = d->irq_status & d->irq_enable;
333  else {
334  fatal("[ WARNING: footbridge write to irq status? ]\n");
335  exit(1);
336  }
337  break;
338 
339  case IRQ_RAW_STATUS:
340  if (writeflag == MEM_READ)
341  odata = d->irq_status;
342  else {
343  fatal("[ footbridge write to irq_raw_status ]\n");
344  exit(1);
345  }
346  break;
347 
348  case IRQ_ENABLE_SET:
349  if (writeflag == MEM_WRITE) {
350  d->irq_enable |= idata;
351  if (d->irq_status & d->irq_enable)
352  INTERRUPT_ASSERT(d->irq);
353  else
355  } else {
356  odata = d->irq_enable;
357  fatal("[ WARNING: footbridge read from "
358  "ENABLE SET? ]\n");
359  exit(1);
360  }
361  break;
362 
363  case IRQ_ENABLE_CLEAR:
364  if (writeflag == MEM_WRITE) {
365  d->irq_enable &= ~idata;
366  if (d->irq_status & d->irq_enable)
367  INTERRUPT_ASSERT(d->irq);
368  else
370  } else {
371  odata = d->irq_enable;
372  fatal("[ WARNING: footbridge read from "
373  "ENABLE CLEAR? ]\n");
374  exit(1);
375  }
376  break;
377 
378  case FIQ_STATUS:
379  if (writeflag == MEM_READ)
380  odata = d->fiq_status & d->fiq_enable;
381  else {
382  fatal("[ WARNING: footbridge write to fiq status? ]\n");
383  exit(1);
384  }
385  break;
386 
387  case FIQ_RAW_STATUS:
388  if (writeflag == MEM_READ)
389  odata = d->fiq_status;
390  else {
391  fatal("[ footbridge write to fiq_raw_status ]\n");
392  exit(1);
393  }
394  break;
395 
396  case FIQ_ENABLE_SET:
397  if (writeflag == MEM_WRITE)
398  d->fiq_enable |= idata;
399  break;
400 
401  case FIQ_ENABLE_CLEAR:
402  if (writeflag == MEM_WRITE)
403  d->fiq_enable &= ~idata;
404  break;
405 
406  case TIMER_1_LOAD:
407  if (writeflag == MEM_READ)
408  odata = d->timer_load[timer_nr];
409  else {
410  d->timer_load[timer_nr] = idata & TIMER_MAX_VAL;
411  reload_timer_value(cpu, d, timer_nr);
412  /* debug("[ footbridge: timer %i (1-based), "
413  "value %i ]\n", timer_nr + 1,
414  (int)d->timer_value[timer_nr]); */
415  INTERRUPT_DEASSERT(d->timer_irq[timer_nr]);
416  }
417  break;
418 
419  case TIMER_1_VALUE:
420  if (writeflag == MEM_READ)
421  odata = d->timer_value[timer_nr];
422  else
423  d->timer_value[timer_nr] = idata & TIMER_MAX_VAL;
424  break;
425 
426  case TIMER_1_CONTROL:
427  if (writeflag == MEM_READ)
428  odata = d->timer_control[timer_nr];
429  else {
430  d->timer_control[timer_nr] = idata;
431  if (idata & TIMER_FCLK_16 &&
432  idata & TIMER_FCLK_256) {
433  fatal("TODO: footbridge timer: "
434  "both 16 and 256?\n");
435  exit(1);
436  }
437  if (idata & TIMER_ENABLE) {
438  reload_timer_value(cpu, d, timer_nr);
439  } else {
440  d->pending_timer_interrupts[timer_nr] = 0;
441  }
442  INTERRUPT_DEASSERT(d->timer_irq[timer_nr]);
443  }
444  break;
445 
446  case TIMER_1_CLEAR:
447  if (d->timer_control[timer_nr] & TIMER_MODE_PERIODIC) {
448  reload_timer_value(cpu, d, timer_nr);
449  }
450 
451  if (d->pending_timer_interrupts[timer_nr] > 0) {
452  d->pending_timer_interrupts[timer_nr] --;
453  }
454 
455  INTERRUPT_DEASSERT(d->timer_irq[timer_nr]);
456  break;
457 
458  default:if (writeflag == MEM_READ) {
459  fatal("[ footbridge: read from 0x%x ]\n",
460  (int)relative_addr);
461  } else {
462  fatal("[ footbridge: write to 0x%x: 0x%llx ]\n",
463  (int)relative_addr, (long long)idata);
464  }
465  }
466 
467  if (writeflag == MEM_READ)
468  memory_writemax64(cpu, data, len, odata);
469 
470  return 1;
471 }
472 
473 
474 DEVINIT(footbridge)
475 {
476  struct footbridge_data *d;
477  char irq_path[300], irq_path_isa[300];
478  uint64_t pci_addr = 0x7b000000;
479  int i;
480 
481  CHECK_ALLOCATION(d = (struct footbridge_data *) malloc(sizeof(struct footbridge_data)));
482  memset(d, 0, sizeof(struct footbridge_data));
483 
484  /* Connect to the CPU which this footbridge will interrupt: */
486 
487  /* DC21285 register access: */
490  dev_footbridge_access, d, DM_DEFAULT, NULL);
491 
492  /* ISA interrupt status/acknowledgement: */
493  memory_device_register(devinit->machine->memory, "footbridge_isa",
494  0x79000000, 8, dev_footbridge_isa_access, d, DM_DEFAULT, NULL);
495 
496  /* The "fcom" console: */
498 
499  /* Register 32 footbridge interrupts: */
500  snprintf(irq_path, sizeof(irq_path), "%s.footbridge",
502  for (i=0; i<32; i++) {
503  struct interrupt interrupt_template;
504  char tmpstr[200];
505 
506  memset(&interrupt_template, 0, sizeof(interrupt_template));
507  interrupt_template.line = 1 << i;
508  snprintf(tmpstr, sizeof(tmpstr), "%s.%i", irq_path, i);
509  interrupt_template.name = tmpstr;
510 
511  interrupt_template.extra = d;
512  interrupt_template.interrupt_assert =
514  interrupt_template.interrupt_deassert =
516  interrupt_handler_register(&interrupt_template);
517 
518  /* Connect locally to some interrupts: */
519  if (i>=IRQ_TIMER_1 && i<=IRQ_TIMER_4)
520  INTERRUPT_CONNECT(tmpstr, d->timer_irq[i-IRQ_TIMER_1]);
521  }
522 
523  switch (devinit->machine->machine_type) {
524  case MACHINE_CATS:
525  snprintf(irq_path_isa, sizeof(irq_path_isa), "%s.10", irq_path);
526  break;
527  case MACHINE_NETWINDER:
528  snprintf(irq_path_isa, sizeof(irq_path_isa), "%s.11", irq_path);
529  break;
530  default:fatal("footbridge unimpl machine type\n");
531  exit(1);
532  }
533 
534  /* A PCI bus: */
535  d->pcibus = bus_pci_init(
536  devinit->machine,
537  irq_path,
538  0x7c000000, /* PCI device io offset */
539  0x80000000, /* PCI device mem offset */
540  0x00000000, /* PCI port base */
541  0x00000000, /* PCI mem base */
542  irq_path, /* PCI irq base */
543  0x7c000000, /* ISA port base */
544  0x80000000, /* ISA mem base */
545  irq_path_isa); /* ISA port base */
546 
547  /* ... with some default devices for known machine types: */
548  switch (devinit->machine->machine_type) {
549  case MACHINE_CATS:
551  devinit->machine->memory, 0xc0, 7, 0, "ali_m1543");
553  devinit->machine->memory, 0xc0, 10, 0, "dec21143");
555  devinit->machine->memory, 0xc0, 16, 0, "ali_m5229");
556  break;
557  case MACHINE_NETWINDER:
559  devinit->machine->memory, 0xc0, 11, 0, "symphony_83c553");
561  devinit->machine->memory, 0xc0, 11, 1, "symphony_82c105");
563  "footbridge_reset", 0x7c000338, 1,
564  dev_footbridge_reset_access, d, DM_DEFAULT, NULL);
565  break;
566  default:fatal("footbridge: unimplemented machine type.\n");
567  exit(1);
568  }
569 
570  /* PCI configuration space: */
572  "footbridge_pci", pci_addr, 0x1000000,
573  dev_footbridge_pci_access, d, DM_DEFAULT, NULL);
574 
575  /* Timer ticks: */
576  for (i=0; i<N_FOOTBRIDGE_TIMERS; i++) {
578  d->timer_load[i] = TIMER_MAX_VAL;
579  }
580 
582  dev_footbridge_tick, d, DEV_FOOTBRIDGE_TICK_SHIFT);
583 
584  devinit->return_ptr = d->pcibus;
585  return 1;
586 }
587 
uint64_t memory_readmax64(struct cpu *cpu, unsigned char *buf, int len)
Definition: memory.cc:55
#define FIQ_ENABLE_SET
Definition: dc21285reg.h:342
void fatal(const char *fmt,...)
Definition: main.cc:152
int emulated_hz
Definition: machine.h:165
void(* interrupt_assert)(struct interrupt *)
Definition: interrupt.h:38
#define DM_DEFAULT
Definition: memory.h:130
#define DEV_FOOTBRIDGE_TICK_SHIFT
#define TIMER_1_VALUE
Definition: dc21285reg.h:376
#define TIMER_FCLK_256
Definition: dc21285reg.h:363
DEVICE_TICK(footbridge)
#define UART_FLAGS
Definition: dc21285reg.h:290
#define TIMER_1_CLEAR
Definition: dc21285reg.h:378
char * name
Definition: device.h:43
int machine_type
Definition: machine.h:111
void * extra
Definition: timer.cc:50
uint32_t timer_value[N_FOOTBRIDGE_TIMERS]
struct machine * machine
Definition: cpu.h:328
void interrupt_handler_register(struct interrupt *templ)
Definition: interrupt.cc:81
struct pci_data * pcibus
#define MEM_READ
Definition: memory.h:116
void(* interrupt_deassert)(struct interrupt *)
Definition: interrupt.h:39
struct memory * memory
Definition: machine.h:126
void bus_pci_add(struct machine *machine, struct pci_data *pci_data, struct memory *mem, int bus, int device, int function, const char *name)
Definition: bus_pci.cc:217
DEVINIT(footbridge)
#define MACHINE_NETWINDER
Definition: machine.h:242
void console_putchar(int handle, int ch)
Definition: console.cc:405
#define reg(x)
int pending_timer_interrupts[N_FOOTBRIDGE_TIMERS]
void * return_ptr
Definition: device.h:56
DEVICE_ACCESS(footbridge_isa)
#define FIQ_ENABLE_CLEAR
Definition: dc21285reg.h:343
Definition: timer.cc:45
void footbridge_interrupt_assert(struct interrupt *interrupt)
#define VENDOR_ID
Definition: dc21285reg.h:47
#define MACHINE_CATS
Definition: machine.h:240
struct isa_pic_data isa_pic_data
Definition: machine.h:190
uint64_t pc
Definition: cpu.h:383
#define CHECK_ALLOCATION(ptr)
Definition: misc.h:239
void timer_update_frequency(struct timer *t, double new_freq)
Definition: timer.cc:132
#define UART_DATA
Definition: dc21285reg.h:263
#define TIMER_4_CLEAR
Definition: dc21285reg.h:390
#define PCI_ADDRESS_EXTENSION
Definition: dc21285reg.h:224
void bus_pci_setaddr(struct cpu *cpu, struct pci_data *pci_data, int bus, int device, int function, int reg)
Definition: bus_pci.cc:197
int irq_base
Definition: devices.h:66
u_short data
Definition: siireg.h:79
struct pic8259_data * pic1
Definition: machine.h:48
#define IRQ_TIMER_1
Definition: dc21285reg.h:301
struct timer * timer_add(double freq, void(*timer_tick)(struct timer *timer, void *extra), void *extra)
Definition: timer.cc:75
#define INTERRUPT_ASSERT(istruct)
Definition: interrupt.h:74
#define IRQ_TIMER_4
Definition: dc21285reg.h:304
#define N_FOOTBRIDGE_TIMERS
#define FIQ_RAW_STATUS
Definition: dc21285reg.h:340
uint32_t timer_load[N_FOOTBRIDGE_TIMERS]
uint8_t running
Definition: cpu.h:353
#define UART_TX_EMPTY
Definition: dc21285reg.h:293
#define MEM_WRITE
Definition: memory.h:117
Definition: device.h:40
#define DEVICE_ID
Definition: dc21285reg.h:49
#define debug
Definition: dev_adb.cc:57
uint32_t line
Definition: interrupt.h:51
#define INTERRUPT_CONNECT(name, istruct)
Definition: interrupt.h:77
Definition: cpu.h:326
void footbridge_interrupt_deassert(struct interrupt *interrupt)
struct machine * machine
Definition: device.h:41
int last_int
Definition: machine.h:52
char * name
Definition: interrupt.h:66
void memory_writemax64(struct cpu *cpu, unsigned char *buf, int len, uint64_t data)
Definition: memory.cc:89
#define FIQ_STATUS
Definition: dc21285reg.h:339
int console_start_slave(struct machine *machine, const char *consolename, int use_for_input)
Definition: console.cc:668
#define SA_CONTROL
Definition: dc21285reg.h:197
void memory_device_register(struct memory *mem, const char *, uint64_t baseaddr, uint64_t len, int(*f)(struct cpu *, struct memory *, uint64_t, unsigned char *, size_t, int, void *), void *extra, int flags, unsigned char *dyntrans_data)
Definition: memory.cc:339
#define REVISION
Definition: dc21285reg.h:51
void bus_pci_decompose_1(uint32_t t, int *bus, int *dev, int *func, int *reg)
Definition: bus_pci.cc:77
struct pic8259_data * pic2
Definition: machine.h:49
#define TIMER_ENABLE
Definition: dc21285reg.h:367
#define IRQ_STATUS
Definition: dc21285reg.h:332
struct pci_data * bus_pci_init(struct machine *machine, const char *irq_path, uint64_t pci_actual_io_offset, uint64_t pci_actual_mem_offset, uint64_t pci_portbase, uint64_t pci_membase, const char *pci_irqbase, uint64_t isa_portbase, uint64_t isa_membase, const char *isa_irqbase)
Definition: bus_pci.cc:356
struct interrupt irq
#define IRQ_ENABLE_SET
Definition: dc21285reg.h:335
addr & if(addr >=0x24 &&page !=NULL)
struct timer * timer[N_FOOTBRIDGE_TIMERS]
#define UART_RX_STAT
Definition: dc21285reg.h:264
uint64_t addr
Definition: device.h:46
struct interrupt timer_irq[N_FOOTBRIDGE_TIMERS]
void machine_add_tickfunction(struct machine *machine, void(*func)(struct cpu *, void *), void *extra, int clockshift)
Definition: machine.cc:280
#define IRQ_RAW_STATUS
Definition: dc21285reg.h:333
#define IRQ_ENABLE_CLEAR
Definition: dc21285reg.h:336
void * extra
Definition: interrupt.h:59
void bus_pci_data_access(struct cpu *cpu, struct pci_data *pci_data, uint64_t *data, int len, int writeflag)
Definition: bus_pci.cc:96
#define MEM_PCI_LITTLE_ENDIAN
Definition: memory.h:97
#define TIMER_MODE_PERIODIC
Definition: dc21285reg.h:366
#define TIMER_1_CONTROL
Definition: dc21285reg.h:377
#define DEV_FOOTBRIDGE_LENGTH
uint32_t timer_control[N_FOOTBRIDGE_TIMERS]
#define PCI_CENTRAL_FUNCTION
Definition: dc21285reg.h:222
#define TIMER_1_LOAD
Definition: dc21285reg.h:375
char * interrupt_path
Definition: device.h:50
#define TIMER_MAX_VAL
Definition: dc21285reg.h:371
#define TIMER_FCLK_16
Definition: dc21285reg.h:362
#define INTERRUPT_DEASSERT(istruct)
Definition: interrupt.h:75

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