armreg.h File Reference

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Macros
armreg.h File Reference

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Macros

#define PSR_FLAGS   0xf0000000 /* flags */
 
#define PSR_N_bit   (1 << 31) /* negative */
 
#define PSR_Z_bit   (1 << 30) /* zero */
 
#define PSR_C_bit   (1 << 29) /* carry */
 
#define PSR_V_bit   (1 << 28) /* overflow */
 
#define PSR_Q_bit   (1 << 27) /* saturation */
 
#define I32_bit   (1 << 7) /* IRQ disable */
 
#define F32_bit   (1 << 6) /* FIQ disable */
 
#define PSR_T_bit   (1 << 5) /* Thumb state */
 
#define PSR_J_bit   (1 << 24) /* Java mode */
 
#define PSR_MODE   0x0000001f /* mode mask */
 
#define PSR_USR26_MODE   0x00000000
 
#define PSR_FIQ26_MODE   0x00000001
 
#define PSR_IRQ26_MODE   0x00000002
 
#define PSR_SVC26_MODE   0x00000003
 
#define PSR_USR32_MODE   0x00000010
 
#define PSR_FIQ32_MODE   0x00000011
 
#define PSR_IRQ32_MODE   0x00000012
 
#define PSR_SVC32_MODE   0x00000013
 
#define PSR_ABT32_MODE   0x00000017
 
#define PSR_UND32_MODE   0x0000001b
 
#define PSR_SYS32_MODE   0x0000001f
 
#define PSR_32_MODE   0x00000010
 
#define PSR_IN_USR_MODE(psr)   (!((psr) & 3)) /* XXX */
 
#define PSR_IN_32_MODE(psr)   ((psr) & PSR_32_MODE)
 
#define R15_MODE   0x00000003
 
#define R15_MODE_USR   0x00000000
 
#define R15_MODE_FIQ   0x00000001
 
#define R15_MODE_IRQ   0x00000002
 
#define R15_MODE_SVC   0x00000003
 
#define R15_PC   0x03fffffc
 
#define R15_FIQ_DISABLE   0x04000000
 
#define R15_IRQ_DISABLE   0x08000000
 
#define R15_FLAGS   0xf0000000
 
#define R15_FLAG_N   0x80000000
 
#define R15_FLAG_Z   0x40000000
 
#define R15_FLAG_C   0x20000000
 
#define R15_FLAG_V   0x10000000
 
#define ARM_CP15_CPU_ID   0
 
#define CPU_ID_IMPLEMENTOR_MASK   0xff000000
 
#define CPU_ID_ARM_LTD   0x41000000 /* 'A' */
 
#define CPU_ID_DEC   0x44000000 /* 'D' */
 
#define CPU_ID_INTEL   0x69000000 /* 'i' */
 
#define CPU_ID_TI   0x54000000 /* 'T' */
 
#define CPU_ID_ISOLD(x)   (((x) & 0x0000f000) == 0x00000000)
 
#define CPU_ID_IS7(x)   (((x) & 0x0000f000) == 0x00007000)
 
#define CPU_ID_ISNEW(x)   (!CPU_ID_ISOLD(x) && !CPU_ID_IS7(x))
 
#define CPU_ID_FOUNDRY_MASK   0x00ff0000
 
#define CPU_ID_FOUNDRY_VLSI   0x00560000
 
#define CPU_ID_7ARCH_MASK   0x00800000
 
#define CPU_ID_7ARCH_V3   0x00000000
 
#define CPU_ID_7ARCH_V4T   0x00800000
 
#define CPU_ID_7VARIANT_MASK   0x007f0000
 
#define CPU_ID_ARCH_MASK   0x000f0000
 
#define CPU_ID_ARCH_V3   0x00000000
 
#define CPU_ID_ARCH_V4   0x00010000
 
#define CPU_ID_ARCH_V4T   0x00020000
 
#define CPU_ID_ARCH_V5   0x00030000
 
#define CPU_ID_ARCH_V5T   0x00040000
 
#define CPU_ID_ARCH_V5TE   0x00050000
 
#define CPU_ID_ARCH_V5TEJ   0x00060000
 
#define CPU_ID_ARCH_V6   0x00070000
 
#define CPU_ID_VARIANT_MASK   0x00f00000
 
#define CPU_ID_PARTNO_MASK   0x0000fff0
 
#define CPU_ID_XSCALE_COREGEN_MASK   0x0000e000 /* core generation */
 
#define CPU_ID_XSCALE_COREREV_MASK   0x00001c00 /* core revision */
 
#define CPU_ID_XSCALE_PRODUCT_MASK   0x000003f0 /* product number */
 
#define CPU_ID_REVISION_MASK   0x0000000f
 
#define CPU_ID_CPU_MASK   0xfffffff0
 
#define CPU_ID_ARM2   0x41560200
 
#define CPU_ID_ARM250   0x41560250
 
#define CPU_ID_ARM3   0x41560300
 
#define CPU_ID_ARM600   0x41560600
 
#define CPU_ID_ARM610   0x41560610
 
#define CPU_ID_ARM620   0x41560620
 
#define CPU_ID_ARM700   0x41007000 /* XXX This is a guess. */
 
#define CPU_ID_ARM710   0x41007100
 
#define CPU_ID_ARM7500   0x41027100 /* XXX This is a guess. */
 
#define CPU_ID_ARM710A   0x41047100 /* inc ARM7100 */
 
#define CPU_ID_ARM7500FE   0x41077100
 
#define CPU_ID_ARM710T   0x41807100
 
#define CPU_ID_ARM720T   0x41807200
 
#define CPU_ID_ARM740T8K   0x41807400 /* XXX no MMU, 8KB cache */
 
#define CPU_ID_ARM740T4K   0x41817400 /* XXX no MMU, 4KB cache */
 
#define CPU_ID_ARM810   0x41018100
 
#define CPU_ID_ARM920T   0x41129200
 
#define CPU_ID_ARM922T   0x41029220
 
#define CPU_ID_ARM940T   0x41029400 /* XXX no MMU */
 
#define CPU_ID_ARM946ES   0x41049460 /* XXX no MMU */
 
#define CPU_ID_ARM966ES   0x41049660 /* XXX no MMU */
 
#define CPU_ID_ARM966ESR1   0x41059660 /* XXX no MMU */
 
#define CPU_ID_ARM1020E   0x4115a200 /* (AKA arm10 rev 1) */
 
#define CPU_ID_ARM1022ES   0x4105a220
 
#define CPU_ID_ARM1026EJS   0x4106a260
 
#define CPU_ID_ARM1136JS   0x4107b360
 
#define CPU_ID_ARM1136JSR1   0x4117b360
 
#define CPU_ID_SA110   0x4401a100
 
#define CPU_ID_SA1100   0x4401a110
 
#define CPU_ID_TI925T   0x54029250
 
#define CPU_ID_SA1110   0x6901b110
 
#define CPU_ID_IXP1200   0x6901c120
 
#define CPU_ID_80200   0x69052000
 
#define CPU_ID_PXA250   0x69052100 /* sans core revision */
 
#define CPU_ID_PXA210   0x69052120
 
#define CPU_ID_PXA250A   0x69052100 /* 1st version Core */
 
#define CPU_ID_PXA210A   0x69052120 /* 1st version Core */
 
#define CPU_ID_PXA250B   0x69052900 /* 3rd version Core */
 
#define CPU_ID_PXA210B   0x69052920 /* 3rd version Core */
 
#define CPU_ID_PXA250C   0x69052d00 /* 4th version Core */
 
#define CPU_ID_PXA210C   0x69052d20 /* 4th version Core */
 
#define CPU_ID_PXA27X   0x69054110
 
#define CPU_ID_80321_400   0x69052420
 
#define CPU_ID_80321_600   0x69052430
 
#define CPU_ID_80321_400_B0   0x69052c20
 
#define CPU_ID_80321_600_B0   0x69052c30
 
#define CPU_ID_80321_600_2   0x69052c32
 
#define CPU_ID_80219_400   0x69052e20
 
#define CPU_ID_80219_600   0x69052e30
 
#define CPU_ID_IXP425_533   0x690541c0
 
#define CPU_ID_IXP425_400   0x690541d0
 
#define CPU_ID_IXP425_266   0x690541f0
 
#define ARM3_CP15_FLUSH   1
 
#define ARM3_CP15_CONTROL   2
 
#define ARM3_CP15_CACHEABLE   3
 
#define ARM3_CP15_UPDATEABLE   4
 
#define ARM3_CP15_DISRUPTIVE   5
 
#define ARM3_CTL_CACHE_ON   0x00000001
 
#define ARM3_CTL_SHARED   0x00000002
 
#define ARM3_CTL_MONITOR   0x00000004
 
#define CPU_CONTROL_MMU_ENABLE   0x00000001 /* M: MMU/Protection unit enable */
 
#define CPU_CONTROL_AFLT_ENABLE   0x00000002 /* A: Alignment fault enable */
 
#define CPU_CONTROL_DC_ENABLE   0x00000004 /* C: IDC/DC enable */
 
#define CPU_CONTROL_WBUF_ENABLE   0x00000008 /* W: Write buffer enable */
 
#define CPU_CONTROL_32BP_ENABLE   0x00000010 /* P: 32-bit exception handlers */
 
#define CPU_CONTROL_32BD_ENABLE   0x00000020 /* D: 32-bit addressing */
 
#define CPU_CONTROL_LABT_ENABLE   0x00000040 /* L: Late abort enable */
 
#define CPU_CONTROL_BEND_ENABLE   0x00000080 /* B: Big-endian mode */
 
#define CPU_CONTROL_SYST_ENABLE   0x00000100 /* S: System protection bit */
 
#define CPU_CONTROL_ROM_ENABLE   0x00000200 /* R: ROM protection bit */
 
#define CPU_CONTROL_CPCLK   0x00000400 /* F: Implementation defined */
 
#define CPU_CONTROL_BPRD_ENABLE   0x00000800 /* Z: Branch prediction enable */
 
#define CPU_CONTROL_IC_ENABLE   0x00001000 /* I: IC enable */
 
#define CPU_CONTROL_VECRELOC   0x00002000 /* V: Vector relocation */
 
#define CPU_CONTROL_ROUNDROBIN   0x00004000 /* RR: Predictable replacement */
 
#define CPU_CONTROL_V4COMPAT   0x00008000 /* L4: ARMv4 compat LDR R15 etc */
 
#define CPU_CONTROL_IDC_ENABLE   CPU_CONTROL_DC_ENABLE
 
#define XSCALE_AUXCTL_K   0x00000001 /* dis. write buffer coalescing */
 
#define XSCALE_AUXCTL_P   0x00000002 /* ECC protect page table access */
 
#define XSCALE_AUXCTL_MD_WB_RA   0x00000000 /* mini-D$ wb, read-allocate */
 
#define XSCALE_AUXCTL_MD_WB_RWA   0x00000010 /* mini-D$ wb, read/write-allocate */
 
#define XSCALE_AUXCTL_MD_WT   0x00000020 /* mini-D$ wt, read-allocate */
 
#define XSCALE_AUXCTL_MD_MASK   0x00000030
 
#define CPU_CT_ISIZE(x)   ((x) & 0xfff) /* I$ info */
 
#define CPU_CT_DSIZE(x)   (((x) >> 12) & 0xfff) /* D$ info */
 
#define CPU_CT_S   (1U << 24) /* split cache */
 
#define CPU_CT_CTYPE(x)   (((x) >> 25) & 0xf) /* cache type */
 
#define CPU_CT_CTYPE_WT   0 /* write-through */
 
#define CPU_CT_CTYPE_WB1   1 /* write-back, clean w/ read */
 
#define CPU_CT_CTYPE_WB2   2 /* w/b, clean w/ cp15,7 */
 
#define CPU_CT_CTYPE_WB6   6 /* w/b, cp15,7, lockdown fmt A */
 
#define CPU_CT_CTYPE_WB7   7 /* w/b, cp15,7, lockdown fmt B */
 
#define CPU_CT_xSIZE_LEN(x)   ((x) & 0x3) /* line size */
 
#define CPU_CT_xSIZE_M   (1U << 2) /* multiplier */
 
#define CPU_CT_xSIZE_ASSOC(x)   (((x) >> 3) & 0x7) /* associativity */
 
#define CPU_CT_xSIZE_SIZE(x)   (((x) >> 6) & 0x7) /* size */
 
#define FAULT_TYPE_MASK   0x0f
 
#define FAULT_USER   0x10
 
#define FAULT_WRTBUF_0   0x00 /* Vector Exception */
 
#define FAULT_WRTBUF_1   0x02 /* Terminal Exception */
 
#define FAULT_BUSERR_0   0x04 /* External Abort on Linefetch -- Section */
 
#define FAULT_BUSERR_1   0x06 /* External Abort on Linefetch -- Page */
 
#define FAULT_BUSERR_2   0x08 /* External Abort on Non-linefetch -- Section */
 
#define FAULT_BUSERR_3   0x0a /* External Abort on Non-linefetch -- Page */
 
#define FAULT_BUSTRNL1   0x0c /* External abort on Translation -- Level 1 */
 
#define FAULT_BUSTRNL2   0x0e /* External abort on Translation -- Level 2 */
 
#define FAULT_ALIGN_0   0x01 /* Alignment */
 
#define FAULT_ALIGN_1   0x03 /* Alignment */
 
#define FAULT_TRANS_S   0x05 /* Translation -- Section */
 
#define FAULT_TRANS_P   0x07 /* Translation -- Page */
 
#define FAULT_DOMAIN_S   0x09 /* Domain -- Section */
 
#define FAULT_DOMAIN_P   0x0b /* Domain -- Page */
 
#define FAULT_PERM_S   0x0d /* Permission -- Section */
 
#define FAULT_PERM_P   0x0f /* Permission -- Page */
 
#define FAULT_IMPRECISE   0x400 /* Imprecise exception (XSCALE) */
 
#define ARM_VECTORS_LOW   0x00000000U
 
#define ARM_VECTORS_HIGH   0xffff0000U
 
#define INSN_SIZE   4 /* Always 4 bytes */
 
#define INSN_COND_MASK   0xf0000000 /* Condition mask */
 
#define INSN_COND_AL   0xe0000000 /* Always condition */
 
#define THUMB_INSN_SIZE   2 /* Some are 4 bytes. */
 

Macro Definition Documentation

◆ ARM3_CP15_CACHEABLE

#define ARM3_CP15_CACHEABLE   3

Definition at line 227 of file armreg.h.

◆ ARM3_CP15_CONTROL

#define ARM3_CP15_CONTROL   2

Definition at line 226 of file armreg.h.

◆ ARM3_CP15_DISRUPTIVE

#define ARM3_CP15_DISRUPTIVE   5

Definition at line 229 of file armreg.h.

◆ ARM3_CP15_FLUSH

#define ARM3_CP15_FLUSH   1

Definition at line 225 of file armreg.h.

◆ ARM3_CP15_UPDATEABLE

#define ARM3_CP15_UPDATEABLE   4

Definition at line 228 of file armreg.h.

◆ ARM3_CTL_CACHE_ON

#define ARM3_CTL_CACHE_ON   0x00000001

Definition at line 232 of file armreg.h.

◆ ARM3_CTL_MONITOR

#define ARM3_CTL_MONITOR   0x00000004

Definition at line 234 of file armreg.h.

◆ ARM3_CTL_SHARED

#define ARM3_CTL_SHARED   0x00000002

Definition at line 233 of file armreg.h.

◆ ARM_CP15_CPU_ID

#define ARM_CP15_CPU_ID   0

Definition at line 109 of file armreg.h.

◆ ARM_VECTORS_HIGH

#define ARM_VECTORS_HIGH   0xffff0000U

Definition at line 345 of file armreg.h.

◆ ARM_VECTORS_LOW

#define ARM_VECTORS_LOW   0x00000000U

Definition at line 344 of file armreg.h.

◆ CPU_CONTROL_32BD_ENABLE

#define CPU_CONTROL_32BD_ENABLE   0x00000020 /* D: 32-bit addressing */

Definition at line 278 of file armreg.h.

◆ CPU_CONTROL_32BP_ENABLE

#define CPU_CONTROL_32BP_ENABLE   0x00000010 /* P: 32-bit exception handlers */

Definition at line 277 of file armreg.h.

◆ CPU_CONTROL_AFLT_ENABLE

#define CPU_CONTROL_AFLT_ENABLE   0x00000002 /* A: Alignment fault enable */

Definition at line 274 of file armreg.h.

◆ CPU_CONTROL_BEND_ENABLE

#define CPU_CONTROL_BEND_ENABLE   0x00000080 /* B: Big-endian mode */

Definition at line 280 of file armreg.h.

◆ CPU_CONTROL_BPRD_ENABLE

#define CPU_CONTROL_BPRD_ENABLE   0x00000800 /* Z: Branch prediction enable */

Definition at line 284 of file armreg.h.

◆ CPU_CONTROL_CPCLK

#define CPU_CONTROL_CPCLK   0x00000400 /* F: Implementation defined */

Definition at line 283 of file armreg.h.

◆ CPU_CONTROL_DC_ENABLE

#define CPU_CONTROL_DC_ENABLE   0x00000004 /* C: IDC/DC enable */

Definition at line 275 of file armreg.h.

◆ CPU_CONTROL_IC_ENABLE

#define CPU_CONTROL_IC_ENABLE   0x00001000 /* I: IC enable */

Definition at line 285 of file armreg.h.

◆ CPU_CONTROL_IDC_ENABLE

#define CPU_CONTROL_IDC_ENABLE   CPU_CONTROL_DC_ENABLE

Definition at line 290 of file armreg.h.

◆ CPU_CONTROL_LABT_ENABLE

#define CPU_CONTROL_LABT_ENABLE   0x00000040 /* L: Late abort enable */

Definition at line 279 of file armreg.h.

◆ CPU_CONTROL_MMU_ENABLE

#define CPU_CONTROL_MMU_ENABLE   0x00000001 /* M: MMU/Protection unit enable */

Definition at line 273 of file armreg.h.

◆ CPU_CONTROL_ROM_ENABLE

#define CPU_CONTROL_ROM_ENABLE   0x00000200 /* R: ROM protection bit */

Definition at line 282 of file armreg.h.

◆ CPU_CONTROL_ROUNDROBIN

#define CPU_CONTROL_ROUNDROBIN   0x00004000 /* RR: Predictable replacement */

Definition at line 287 of file armreg.h.

◆ CPU_CONTROL_SYST_ENABLE

#define CPU_CONTROL_SYST_ENABLE   0x00000100 /* S: System protection bit */

Definition at line 281 of file armreg.h.

◆ CPU_CONTROL_V4COMPAT

#define CPU_CONTROL_V4COMPAT   0x00008000 /* L4: ARMv4 compat LDR R15 etc */

Definition at line 288 of file armreg.h.

◆ CPU_CONTROL_VECRELOC

#define CPU_CONTROL_VECRELOC   0x00002000 /* V: Vector relocation */

Definition at line 286 of file armreg.h.

◆ CPU_CONTROL_WBUF_ENABLE

#define CPU_CONTROL_WBUF_ENABLE   0x00000008 /* W: Write buffer enable */

Definition at line 276 of file armreg.h.

◆ CPU_CT_CTYPE

#define CPU_CT_CTYPE (   x)    (((x) >> 25) & 0xf) /* cache type */

Definition at line 304 of file armreg.h.

◆ CPU_CT_CTYPE_WB1

#define CPU_CT_CTYPE_WB1   1 /* write-back, clean w/ read */

Definition at line 307 of file armreg.h.

◆ CPU_CT_CTYPE_WB2

#define CPU_CT_CTYPE_WB2   2 /* w/b, clean w/ cp15,7 */

Definition at line 308 of file armreg.h.

◆ CPU_CT_CTYPE_WB6

#define CPU_CT_CTYPE_WB6   6 /* w/b, cp15,7, lockdown fmt A */

Definition at line 309 of file armreg.h.

◆ CPU_CT_CTYPE_WB7

#define CPU_CT_CTYPE_WB7   7 /* w/b, cp15,7, lockdown fmt B */

Definition at line 310 of file armreg.h.

◆ CPU_CT_CTYPE_WT

#define CPU_CT_CTYPE_WT   0 /* write-through */

Definition at line 306 of file armreg.h.

◆ CPU_CT_DSIZE

#define CPU_CT_DSIZE (   x)    (((x) >> 12) & 0xfff) /* D$ info */

Definition at line 302 of file armreg.h.

◆ CPU_CT_ISIZE

#define CPU_CT_ISIZE (   x)    ((x) & 0xfff) /* I$ info */

Definition at line 301 of file armreg.h.

◆ CPU_CT_S

#define CPU_CT_S   (1U << 24) /* split cache */

Definition at line 303 of file armreg.h.

◆ CPU_CT_xSIZE_ASSOC

#define CPU_CT_xSIZE_ASSOC (   x)    (((x) >> 3) & 0x7) /* associativity */

Definition at line 314 of file armreg.h.

◆ CPU_CT_xSIZE_LEN

#define CPU_CT_xSIZE_LEN (   x)    ((x) & 0x3) /* line size */

Definition at line 312 of file armreg.h.

◆ CPU_CT_xSIZE_M

#define CPU_CT_xSIZE_M   (1U << 2) /* multiplier */

Definition at line 313 of file armreg.h.

◆ CPU_CT_xSIZE_SIZE

#define CPU_CT_xSIZE_SIZE (   x)    (((x) >> 6) & 0x7) /* size */

Definition at line 315 of file armreg.h.

◆ CPU_ID_7ARCH_MASK

#define CPU_ID_7ARCH_MASK   0x00800000

Definition at line 133 of file armreg.h.

◆ CPU_ID_7ARCH_V3

#define CPU_ID_7ARCH_V3   0x00000000

Definition at line 134 of file armreg.h.

◆ CPU_ID_7ARCH_V4T

#define CPU_ID_7ARCH_V4T   0x00800000

Definition at line 135 of file armreg.h.

◆ CPU_ID_7VARIANT_MASK

#define CPU_ID_7VARIANT_MASK   0x007f0000

Definition at line 136 of file armreg.h.

◆ CPU_ID_80200

#define CPU_ID_80200   0x69052000

Definition at line 203 of file armreg.h.

◆ CPU_ID_80219_400

#define CPU_ID_80219_400   0x69052e20

Definition at line 218 of file armreg.h.

◆ CPU_ID_80219_600

#define CPU_ID_80219_600   0x69052e30

Definition at line 219 of file armreg.h.

◆ CPU_ID_80321_400

#define CPU_ID_80321_400   0x69052420

Definition at line 213 of file armreg.h.

◆ CPU_ID_80321_400_B0

#define CPU_ID_80321_400_B0   0x69052c20

Definition at line 215 of file armreg.h.

◆ CPU_ID_80321_600

#define CPU_ID_80321_600   0x69052430

Definition at line 214 of file armreg.h.

◆ CPU_ID_80321_600_2

#define CPU_ID_80321_600_2   0x69052c32

Definition at line 217 of file armreg.h.

◆ CPU_ID_80321_600_B0

#define CPU_ID_80321_600_B0   0x69052c30

Definition at line 216 of file armreg.h.

◆ CPU_ID_ARCH_MASK

#define CPU_ID_ARCH_MASK   0x000f0000

Definition at line 139 of file armreg.h.

◆ CPU_ID_ARCH_V3

#define CPU_ID_ARCH_V3   0x00000000

Definition at line 140 of file armreg.h.

◆ CPU_ID_ARCH_V4

#define CPU_ID_ARCH_V4   0x00010000

Definition at line 141 of file armreg.h.

◆ CPU_ID_ARCH_V4T

#define CPU_ID_ARCH_V4T   0x00020000

Definition at line 142 of file armreg.h.

◆ CPU_ID_ARCH_V5

#define CPU_ID_ARCH_V5   0x00030000

Definition at line 143 of file armreg.h.

◆ CPU_ID_ARCH_V5T

#define CPU_ID_ARCH_V5T   0x00040000

Definition at line 144 of file armreg.h.

◆ CPU_ID_ARCH_V5TE

#define CPU_ID_ARCH_V5TE   0x00050000

Definition at line 145 of file armreg.h.

◆ CPU_ID_ARCH_V5TEJ

#define CPU_ID_ARCH_V5TEJ   0x00060000

Definition at line 146 of file armreg.h.

◆ CPU_ID_ARCH_V6

#define CPU_ID_ARCH_V6   0x00070000

Definition at line 147 of file armreg.h.

◆ CPU_ID_ARM1020E

#define CPU_ID_ARM1020E   0x4115a200 /* (AKA arm10 rev 1) */

Definition at line 193 of file armreg.h.

◆ CPU_ID_ARM1022ES

#define CPU_ID_ARM1022ES   0x4105a220

Definition at line 194 of file armreg.h.

◆ CPU_ID_ARM1026EJS

#define CPU_ID_ARM1026EJS   0x4106a260

Definition at line 195 of file armreg.h.

◆ CPU_ID_ARM1136JS

#define CPU_ID_ARM1136JS   0x4107b360

Definition at line 196 of file armreg.h.

◆ CPU_ID_ARM1136JSR1

#define CPU_ID_ARM1136JSR1   0x4117b360

Definition at line 197 of file armreg.h.

◆ CPU_ID_ARM2

#define CPU_ID_ARM2   0x41560200

Definition at line 165 of file armreg.h.

◆ CPU_ID_ARM250

#define CPU_ID_ARM250   0x41560250

Definition at line 166 of file armreg.h.

◆ CPU_ID_ARM3

#define CPU_ID_ARM3   0x41560300

Definition at line 169 of file armreg.h.

◆ CPU_ID_ARM600

#define CPU_ID_ARM600   0x41560600

Definition at line 170 of file armreg.h.

◆ CPU_ID_ARM610

#define CPU_ID_ARM610   0x41560610

Definition at line 171 of file armreg.h.

◆ CPU_ID_ARM620

#define CPU_ID_ARM620   0x41560620

Definition at line 172 of file armreg.h.

◆ CPU_ID_ARM700

#define CPU_ID_ARM700   0x41007000 /* XXX This is a guess. */

Definition at line 175 of file armreg.h.

◆ CPU_ID_ARM710

#define CPU_ID_ARM710   0x41007100

Definition at line 176 of file armreg.h.

◆ CPU_ID_ARM710A

#define CPU_ID_ARM710A   0x41047100 /* inc ARM7100 */

Definition at line 178 of file armreg.h.

◆ CPU_ID_ARM710T

#define CPU_ID_ARM710T   0x41807100

Definition at line 180 of file armreg.h.

◆ CPU_ID_ARM720T

#define CPU_ID_ARM720T   0x41807200

Definition at line 181 of file armreg.h.

◆ CPU_ID_ARM740T4K

#define CPU_ID_ARM740T4K   0x41817400 /* XXX no MMU, 4KB cache */

Definition at line 183 of file armreg.h.

◆ CPU_ID_ARM740T8K

#define CPU_ID_ARM740T8K   0x41807400 /* XXX no MMU, 8KB cache */

Definition at line 182 of file armreg.h.

◆ CPU_ID_ARM7500

#define CPU_ID_ARM7500   0x41027100 /* XXX This is a guess. */

Definition at line 177 of file armreg.h.

◆ CPU_ID_ARM7500FE

#define CPU_ID_ARM7500FE   0x41077100

Definition at line 179 of file armreg.h.

◆ CPU_ID_ARM810

#define CPU_ID_ARM810   0x41018100

Definition at line 186 of file armreg.h.

◆ CPU_ID_ARM920T

#define CPU_ID_ARM920T   0x41129200

Definition at line 187 of file armreg.h.

◆ CPU_ID_ARM922T

#define CPU_ID_ARM922T   0x41029220

Definition at line 188 of file armreg.h.

◆ CPU_ID_ARM940T

#define CPU_ID_ARM940T   0x41029400 /* XXX no MMU */

Definition at line 189 of file armreg.h.

◆ CPU_ID_ARM946ES

#define CPU_ID_ARM946ES   0x41049460 /* XXX no MMU */

Definition at line 190 of file armreg.h.

◆ CPU_ID_ARM966ES

#define CPU_ID_ARM966ES   0x41049660 /* XXX no MMU */

Definition at line 191 of file armreg.h.

◆ CPU_ID_ARM966ESR1

#define CPU_ID_ARM966ESR1   0x41059660 /* XXX no MMU */

Definition at line 192 of file armreg.h.

◆ CPU_ID_ARM_LTD

#define CPU_ID_ARM_LTD   0x41000000 /* 'A' */

Definition at line 118 of file armreg.h.

◆ CPU_ID_CPU_MASK

#define CPU_ID_CPU_MASK   0xfffffff0

Definition at line 162 of file armreg.h.

◆ CPU_ID_DEC

#define CPU_ID_DEC   0x44000000 /* 'D' */

Definition at line 119 of file armreg.h.

◆ CPU_ID_FOUNDRY_MASK

#define CPU_ID_FOUNDRY_MASK   0x00ff0000

Definition at line 129 of file armreg.h.

◆ CPU_ID_FOUNDRY_VLSI

#define CPU_ID_FOUNDRY_VLSI   0x00560000

Definition at line 130 of file armreg.h.

◆ CPU_ID_IMPLEMENTOR_MASK

#define CPU_ID_IMPLEMENTOR_MASK   0xff000000

Definition at line 117 of file armreg.h.

◆ CPU_ID_INTEL

#define CPU_ID_INTEL   0x69000000 /* 'i' */

Definition at line 120 of file armreg.h.

◆ CPU_ID_IS7

#define CPU_ID_IS7 (   x)    (((x) & 0x0000f000) == 0x00007000)

Definition at line 125 of file armreg.h.

◆ CPU_ID_ISNEW

#define CPU_ID_ISNEW (   x)    (!CPU_ID_ISOLD(x) && !CPU_ID_IS7(x))

Definition at line 126 of file armreg.h.

◆ CPU_ID_ISOLD

#define CPU_ID_ISOLD (   x)    (((x) & 0x0000f000) == 0x00000000)

Definition at line 124 of file armreg.h.

◆ CPU_ID_IXP1200

#define CPU_ID_IXP1200   0x6901c120

Definition at line 202 of file armreg.h.

◆ CPU_ID_IXP425_266

#define CPU_ID_IXP425_266   0x690541f0

Definition at line 222 of file armreg.h.

◆ CPU_ID_IXP425_400

#define CPU_ID_IXP425_400   0x690541d0

Definition at line 221 of file armreg.h.

◆ CPU_ID_IXP425_533

#define CPU_ID_IXP425_533   0x690541c0

Definition at line 220 of file armreg.h.

◆ CPU_ID_PARTNO_MASK

#define CPU_ID_PARTNO_MASK   0x0000fff0

Definition at line 151 of file armreg.h.

◆ CPU_ID_PXA210

#define CPU_ID_PXA210   0x69052120

Definition at line 205 of file armreg.h.

◆ CPU_ID_PXA210A

#define CPU_ID_PXA210A   0x69052120 /* 1st version Core */

Definition at line 207 of file armreg.h.

◆ CPU_ID_PXA210B

#define CPU_ID_PXA210B   0x69052920 /* 3rd version Core */

Definition at line 209 of file armreg.h.

◆ CPU_ID_PXA210C

#define CPU_ID_PXA210C   0x69052d20 /* 4th version Core */

Definition at line 211 of file armreg.h.

◆ CPU_ID_PXA250

#define CPU_ID_PXA250   0x69052100 /* sans core revision */

Definition at line 204 of file armreg.h.

◆ CPU_ID_PXA250A

#define CPU_ID_PXA250A   0x69052100 /* 1st version Core */

Definition at line 206 of file armreg.h.

◆ CPU_ID_PXA250B

#define CPU_ID_PXA250B   0x69052900 /* 3rd version Core */

Definition at line 208 of file armreg.h.

◆ CPU_ID_PXA250C

#define CPU_ID_PXA250C   0x69052d00 /* 4th version Core */

Definition at line 210 of file armreg.h.

◆ CPU_ID_PXA27X

#define CPU_ID_PXA27X   0x69054110

Definition at line 212 of file armreg.h.

◆ CPU_ID_REVISION_MASK

#define CPU_ID_REVISION_MASK   0x0000000f

Definition at line 159 of file armreg.h.

◆ CPU_ID_SA110

#define CPU_ID_SA110   0x4401a100

Definition at line 198 of file armreg.h.

◆ CPU_ID_SA1100

#define CPU_ID_SA1100   0x4401a110

Definition at line 199 of file armreg.h.

◆ CPU_ID_SA1110

#define CPU_ID_SA1110   0x6901b110

Definition at line 201 of file armreg.h.

◆ CPU_ID_TI

#define CPU_ID_TI   0x54000000 /* 'T' */

Definition at line 121 of file armreg.h.

◆ CPU_ID_TI925T

#define CPU_ID_TI925T   0x54029250

Definition at line 200 of file armreg.h.

◆ CPU_ID_VARIANT_MASK

#define CPU_ID_VARIANT_MASK   0x00f00000

Definition at line 148 of file armreg.h.

◆ CPU_ID_XSCALE_COREGEN_MASK

#define CPU_ID_XSCALE_COREGEN_MASK   0x0000e000 /* core generation */

Definition at line 154 of file armreg.h.

◆ CPU_ID_XSCALE_COREREV_MASK

#define CPU_ID_XSCALE_COREREV_MASK   0x00001c00 /* core revision */

Definition at line 155 of file armreg.h.

◆ CPU_ID_XSCALE_PRODUCT_MASK

#define CPU_ID_XSCALE_PRODUCT_MASK   0x000003f0 /* product number */

Definition at line 156 of file armreg.h.

◆ F32_bit

#define F32_bit   (1 << 6) /* FIQ disable */

Definition at line 64 of file armreg.h.

◆ FAULT_ALIGN_0

#define FAULT_ALIGN_0   0x01 /* Alignment */

Definition at line 330 of file armreg.h.

◆ FAULT_ALIGN_1

#define FAULT_ALIGN_1   0x03 /* Alignment */

Definition at line 331 of file armreg.h.

◆ FAULT_BUSERR_0

#define FAULT_BUSERR_0   0x04 /* External Abort on Linefetch -- Section */

Definition at line 324 of file armreg.h.

◆ FAULT_BUSERR_1

#define FAULT_BUSERR_1   0x06 /* External Abort on Linefetch -- Page */

Definition at line 325 of file armreg.h.

◆ FAULT_BUSERR_2

#define FAULT_BUSERR_2   0x08 /* External Abort on Non-linefetch -- Section */

Definition at line 326 of file armreg.h.

◆ FAULT_BUSERR_3

#define FAULT_BUSERR_3   0x0a /* External Abort on Non-linefetch -- Page */

Definition at line 327 of file armreg.h.

◆ FAULT_BUSTRNL1

#define FAULT_BUSTRNL1   0x0c /* External abort on Translation -- Level 1 */

Definition at line 328 of file armreg.h.

◆ FAULT_BUSTRNL2

#define FAULT_BUSTRNL2   0x0e /* External abort on Translation -- Level 2 */

Definition at line 329 of file armreg.h.

◆ FAULT_DOMAIN_P

#define FAULT_DOMAIN_P   0x0b /* Domain -- Page */

Definition at line 335 of file armreg.h.

Referenced by arm_translate_v2p_mmu().

◆ FAULT_DOMAIN_S

#define FAULT_DOMAIN_S   0x09 /* Domain -- Section */

Definition at line 334 of file armreg.h.

◆ FAULT_IMPRECISE

#define FAULT_IMPRECISE   0x400 /* Imprecise exception (XSCALE) */

Definition at line 339 of file armreg.h.

◆ FAULT_PERM_P

#define FAULT_PERM_P   0x0f /* Permission -- Page */

Definition at line 337 of file armreg.h.

◆ FAULT_PERM_S

#define FAULT_PERM_S   0x0d /* Permission -- Section */

Definition at line 336 of file armreg.h.

◆ FAULT_TRANS_P

#define FAULT_TRANS_P   0x07 /* Translation -- Page */

Definition at line 333 of file armreg.h.

Referenced by arm_translate_v2p_mmu().

◆ FAULT_TRANS_S

#define FAULT_TRANS_S   0x05 /* Translation -- Section */

Definition at line 332 of file armreg.h.

Referenced by arm_translate_v2p_mmu().

◆ FAULT_TYPE_MASK

#define FAULT_TYPE_MASK   0x0f

Definition at line 319 of file armreg.h.

◆ FAULT_USER

#define FAULT_USER   0x10

Definition at line 320 of file armreg.h.

◆ FAULT_WRTBUF_0

#define FAULT_WRTBUF_0   0x00 /* Vector Exception */

Definition at line 322 of file armreg.h.

◆ FAULT_WRTBUF_1

#define FAULT_WRTBUF_1   0x02 /* Terminal Exception */

Definition at line 323 of file armreg.h.

◆ I32_bit

#define I32_bit   (1 << 7) /* IRQ disable */

Definition at line 63 of file armreg.h.

◆ INSN_COND_AL

#define INSN_COND_AL   0xe0000000 /* Always condition */

Definition at line 360 of file armreg.h.

◆ INSN_COND_MASK

#define INSN_COND_MASK   0xf0000000 /* Condition mask */

Definition at line 359 of file armreg.h.

◆ INSN_SIZE

#define INSN_SIZE   4 /* Always 4 bytes */

Definition at line 358 of file armreg.h.

◆ PSR_32_MODE

#define PSR_32_MODE   0x00000010

Definition at line 81 of file armreg.h.

◆ PSR_ABT32_MODE

#define PSR_ABT32_MODE   0x00000017

Definition at line 78 of file armreg.h.

◆ PSR_C_bit

#define PSR_C_bit   (1 << 29) /* carry */

Definition at line 58 of file armreg.h.

◆ PSR_FIQ26_MODE

#define PSR_FIQ26_MODE   0x00000001

Definition at line 71 of file armreg.h.

◆ PSR_FIQ32_MODE

#define PSR_FIQ32_MODE   0x00000011

Definition at line 75 of file armreg.h.

◆ PSR_FLAGS

#define PSR_FLAGS   0xf0000000 /* flags */

Definition at line 55 of file armreg.h.

◆ PSR_IN_32_MODE

#define PSR_IN_32_MODE (   psr)    ((psr) & PSR_32_MODE)

Definition at line 84 of file armreg.h.

◆ PSR_IN_USR_MODE

#define PSR_IN_USR_MODE (   psr)    (!((psr) & 3)) /* XXX */

Definition at line 83 of file armreg.h.

◆ PSR_IRQ26_MODE

#define PSR_IRQ26_MODE   0x00000002

Definition at line 72 of file armreg.h.

◆ PSR_IRQ32_MODE

#define PSR_IRQ32_MODE   0x00000012

Definition at line 76 of file armreg.h.

◆ PSR_J_bit

#define PSR_J_bit   (1 << 24) /* Java mode */

Definition at line 67 of file armreg.h.

◆ PSR_MODE

#define PSR_MODE   0x0000001f /* mode mask */

Definition at line 69 of file armreg.h.

◆ PSR_N_bit

#define PSR_N_bit   (1 << 31) /* negative */

Definition at line 56 of file armreg.h.

◆ PSR_Q_bit

#define PSR_Q_bit   (1 << 27) /* saturation */

Definition at line 61 of file armreg.h.

◆ PSR_SVC26_MODE

#define PSR_SVC26_MODE   0x00000003

Definition at line 73 of file armreg.h.

◆ PSR_SVC32_MODE

#define PSR_SVC32_MODE   0x00000013

Definition at line 77 of file armreg.h.

◆ PSR_SYS32_MODE

#define PSR_SYS32_MODE   0x0000001f

Definition at line 80 of file armreg.h.

◆ PSR_T_bit

#define PSR_T_bit   (1 << 5) /* Thumb state */

Definition at line 66 of file armreg.h.

◆ PSR_UND32_MODE

#define PSR_UND32_MODE   0x0000001b

Definition at line 79 of file armreg.h.

◆ PSR_USR26_MODE

#define PSR_USR26_MODE   0x00000000

Definition at line 70 of file armreg.h.

◆ PSR_USR32_MODE

#define PSR_USR32_MODE   0x00000010

Definition at line 74 of file armreg.h.

◆ PSR_V_bit

#define PSR_V_bit   (1 << 28) /* overflow */

Definition at line 59 of file armreg.h.

◆ PSR_Z_bit

#define PSR_Z_bit   (1 << 30) /* zero */

Definition at line 57 of file armreg.h.

◆ R15_FIQ_DISABLE

#define R15_FIQ_DISABLE   0x04000000

Definition at line 96 of file armreg.h.

◆ R15_FLAG_C

#define R15_FLAG_C   0x20000000

Definition at line 102 of file armreg.h.

◆ R15_FLAG_N

#define R15_FLAG_N   0x80000000

Definition at line 100 of file armreg.h.

◆ R15_FLAG_V

#define R15_FLAG_V   0x10000000

Definition at line 103 of file armreg.h.

◆ R15_FLAG_Z

#define R15_FLAG_Z   0x40000000

Definition at line 101 of file armreg.h.

◆ R15_FLAGS

#define R15_FLAGS   0xf0000000

Definition at line 99 of file armreg.h.

◆ R15_IRQ_DISABLE

#define R15_IRQ_DISABLE   0x08000000

Definition at line 97 of file armreg.h.

◆ R15_MODE

#define R15_MODE   0x00000003

Definition at line 88 of file armreg.h.

◆ R15_MODE_FIQ

#define R15_MODE_FIQ   0x00000001

Definition at line 90 of file armreg.h.

◆ R15_MODE_IRQ

#define R15_MODE_IRQ   0x00000002

Definition at line 91 of file armreg.h.

◆ R15_MODE_SVC

#define R15_MODE_SVC   0x00000003

Definition at line 92 of file armreg.h.

◆ R15_MODE_USR

#define R15_MODE_USR   0x00000000

Definition at line 89 of file armreg.h.

◆ R15_PC

#define R15_PC   0x03fffffc

Definition at line 94 of file armreg.h.

◆ THUMB_INSN_SIZE

#define THUMB_INSN_SIZE   2 /* Some are 4 bytes. */

Definition at line 362 of file armreg.h.

◆ XSCALE_AUXCTL_K

#define XSCALE_AUXCTL_K   0x00000001 /* dis. write buffer coalescing */

Definition at line 293 of file armreg.h.

◆ XSCALE_AUXCTL_MD_MASK

#define XSCALE_AUXCTL_MD_MASK   0x00000030

Definition at line 298 of file armreg.h.

◆ XSCALE_AUXCTL_MD_WB_RA

#define XSCALE_AUXCTL_MD_WB_RA   0x00000000 /* mini-D$ wb, read-allocate */

Definition at line 295 of file armreg.h.

◆ XSCALE_AUXCTL_MD_WB_RWA

#define XSCALE_AUXCTL_MD_WB_RWA   0x00000010 /* mini-D$ wb, read/write-allocate */

Definition at line 296 of file armreg.h.

◆ XSCALE_AUXCTL_MD_WT

#define XSCALE_AUXCTL_MD_WT   0x00000020 /* mini-D$ wt, read-allocate */

Definition at line 297 of file armreg.h.

◆ XSCALE_AUXCTL_P

#define XSCALE_AUXCTL_P   0x00000002 /* ECC protect page table access */

Definition at line 294 of file armreg.h.


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