88 #define MC_REGA_RSMASK 0x0f 89 #define MC_REGA_DVMASK 0x70 90 #define MC_REGA_UIP 0x80 94 #define MC_REGB_DSE 0x01 95 #define MC_REGB_24HR 0x02 96 #define MC_REGB_BINARY 0x04 97 #define MC_REGB_SQWE 0x08 98 #define MC_REGB_UIE 0x10 99 #define MC_REGB_AIE 0x20 100 #define MC_REGB_PIE 0x40 101 #define MC_REGB_SET 0x80 106 #define MC_REGC_UF 0x10 107 #define MC_REGC_AF 0x20 108 #define MC_REGC_PF 0x40 109 #define MC_REGC_IRQF 0x80 114 #define MC_REGD_VRT 0x80 118 #define MC_NTODREGS 0xa 120 #define MC_NVRAM_START 0xe 121 #define MC_NVRAM_SIZE 50 126 #define MC_RATE_NONE 0x0 127 #define MC_RATE_1 0x1 128 #define MC_RATE_2 0x2 129 #define MC_RATE_8192_Hz 0x3 130 #define MC_RATE_4096_Hz 0x4 131 #define MC_RATE_2048_Hz 0x5 132 #define MC_RATE_1024_Hz 0x6 133 #define MC_RATE_512_Hz 0x7 134 #define MC_RATE_256_Hz 0x8 135 #define MC_RATE_128_Hz 0x9 136 #define MC_RATE_64_Hz 0xa 137 #define MC_RATE_32_Hz 0xb 138 #define MC_RATE_16_Hz 0xc 139 #define MC_RATE_8_Hz 0xd 140 #define MC_RATE_4_Hz 0xe 141 #define MC_RATE_2_Hz 0xf 146 #define MC_BASE_4_MHz 0x00 147 #define MC_BASE_1_MHz 0x10 148 #define MC_BASE_32_KHz 0x20 149 #define MC_BASE_NONE 0x60 150 #define MC_BASE_RESET 0x70 157 u_int mc146818_read
__P((
void *sc, u_int
reg));
158 void mc146818_write
__P((
void *sc, u_int
reg, u_int datum));
169 #define MC146818_GETTOD(sc, regs) \ 174 while (mc146818_read(sc, MC_REGA) & MC_REGA_UIP) \ 178 for (i = 0; i < MC_NTODREGS; i++) \ 179 (*regs)[i] = mc146818_read(sc, i); \ 186 #define MC146818_PUTTOD(sc, regs) \ 191 mc146818_write(sc, MC_REGB, \ 192 mc146818_read(sc, MC_REGB) | MC_REGB_SET); \ 195 for (i = 0; i < MC_NTODREGS; i++) \ 196 mc146818_write(sc, i, (*regs)[i]); \ 199 mc146818_write(sc, MC_REGB, \ 200 mc146818_read(sc, MC_REGB) & ~MC_REGB_SET); \
u_int mc_todregs[MC_NTODREGS]