38 int low_pc = ((size_t)ic - (size_t)cpu->cd.sh.cur_ic_page) \ 39 / sizeof(struct sh_instr_call); \ 40 cpu->pc &= ~((SH_IC_ENTRIES_PER_PAGE-1) \ 41 << SH_INSTR_ALIGNMENT_SHIFT); \ 42 cpu->pc += (low_pc << SH_INSTR_ALIGNMENT_SHIFT); \ 45 #define ABORT_EXECUTION { SYNCH_PC; \ 46 fatal("Execution aborted at: pc = 0x%08x\n", (int)cpu->pc); \ 47 cpu->cd.sh.next_ic = ¬hing_call; \ 49 debugger_n_steps_left_before_interaction = 0; } 51 #define RES_INST_IF_NOT_MD \ 52 if (!(cpu->cd.sh.sr & SH_SR_MD)) { \ 54 sh_exception(cpu, EXPEVT_RES_INST, 0, 0); \ 58 #define FLOATING_POINT_AVAILABLE_CHECK \ 59 if (cpu->cd.sh.sr & SH_SR_FD) { \ 62 if (cpu->delay_slot) \ 63 sh_exception(cpu, EXPEVT_FPU_SLOT_DISABLE, 0, 0);\ 65 sh_exception(cpu, EXPEVT_FPU_DISABLE, 0, 0); \ 159 res -= (uint64_t)
reg(
ic->arg[0]);
166 reg(
ic->arg[1]) = (uint32_t) res;
170 uint32_t r =
reg(
ic->arg[0]);
171 reg(
ic->arg[1]) = (r & 0xffff0000) | ((r >> 8)&0xff) | ((r&0xff) << 8);
175 uint32_t r =
reg(
ic->arg[0]);
176 reg(
ic->arg[1]) = (r >> 16) | (r << 16);
217 uint8_t *p = (uint8_t *)
cpu->
cd.
sh.host_store[addr >> 12];
220 p[addr & 0xfff] ^=
ic->arg[0];
240 uint8_t *p = (uint8_t *)
cpu->
cd.
sh.host_store[addr >> 12];
243 p[addr & 0xfff] |=
ic->arg[0];
263 uint8_t *p = (uint8_t *)
cpu->
cd.
sh.host_store[addr >> 12];
266 p[addr & 0xfff] &=
ic->arg[0];
310 X(mov_b_rm_predec_rn)
312 uint32_t
addr =
reg(
ic->arg[1]) -
sizeof(uint8_t);
313 int8_t *p = (int8_t *)
cpu->
cd.
sh.host_store[addr >> 12];
316 p[addr & 0xfff] =
data;
329 X(mov_w_rm_predec_rn)
331 uint32_t
addr =
reg(
ic->arg[1]) -
sizeof(uint16_t);
332 uint16_t *p = (uint16_t *)
cpu->
cd.
sh.host_store[addr >> 12];
341 p[(addr & 0xfff) >> 1] =
data;
354 X(mov_l_rm_predec_rn)
356 uint32_t
addr =
reg(
ic->arg[1]) -
sizeof(uint32_t);
357 uint32_t *p = (uint32_t *)
cpu->
cd.
sh.host_store[addr >> 12];
366 p[(addr & 0xfff) >> 2] =
data;
379 X(stc_l_rm_predec_rn_md)
381 uint32_t
addr =
reg(
ic->arg[1]) -
sizeof(uint32_t);
382 uint32_t *p = (uint32_t *)
cpu->
cd.
sh.host_store[addr >> 12];
393 p[(addr & 0xfff) >> 2] =
data;
419 uint32_t *p = (uint32_t *)
cpu->
cd.
sh.host_load[addr >> 12];
423 data = p[(addr & 0xfff) >> 2];
463 uint16_t *p = (uint16_t *)
cpu->
cd.
sh.host_load[addr >> 12];
467 data = p[(addr & 0xfff) >> 1];
514 uint8_t *p = (uint8_t *)
cpu->
cd.
sh.host_load[addr >> 12];
518 data = p[addr & 0xfff];
532 int16_t *p = (int16_t *)
cpu->
cd.
sh.host_load[addr >> 12];
536 data = p[(addr & 0xfff) >> 1];
554 uint32_t *p = (uint32_t *)
cpu->
cd.
sh.host_load[addr >> 12];
558 data = p[(addr & 0xfff) >> 2];
577 uint32_t *p = (uint32_t *)
cpu->
cd.
sh.host_load[addr >> 12];
588 size_t r1 =
ic->arg[1];
589 int ofs = (r1 - (size_t)&
cpu->
cd.
sh.
fr[0]) /
sizeof(uint32_t);
591 fatal(
"ODD fmov_rm_frn: TODO");
609 data = p[(addr & 0xfff) >> 2];
632 reg(
ic->arg[1] + 4) = data2;
638 uint32_t *p = (uint32_t *)
cpu->
cd.
sh.host_load[addr >> 12];
643 fatal(
"fmov_r0_rm_frn: sz=1 (register pair): TODO\n");
649 data = p[(addr & 0xfff) >> 2];
666 X(fmov_rm_postinc_frn)
670 uint32_t *p = (uint32_t *)
cpu->
cd.
sh.host_load[addr >> 12];
671 size_t r1 =
ic->arg[1];
675 int ofs = (r1 - (size_t)&
cpu->
cd.
sh.
fr[0]) /
sizeof(uint32_t);
683 data = p[(addr & 0xfff) >> 2];
714 reg(
ic->arg[0]) = addr +
sizeof(uint32_t);
719 int8_t *p = (int8_t *)
cpu->
cd.
sh.host_load[addr >> 12];
722 data = p[addr & 0xfff];
736 int16_t *p = (int16_t *)
cpu->
cd.
sh.host_load[addr >> 12];
739 data = p[(addr & 0xfff) >> 1];
757 uint32_t *p = (uint32_t *)
cpu->
cd.
sh.host_load[addr >> 12];
760 data = p[(addr & 0xfff) >> 2];
775 X(mov_b_arg1_postinc_to_arg0)
778 int8_t *p = (int8_t *)
cpu->
cd.
sh.host_load[addr >> 12];
781 data = p[addr & 0xfff];
791 reg(
ic->arg[1]) = addr +
sizeof(int8_t);
794 X(mov_w_arg1_postinc_to_arg0)
797 uint16_t *p = (uint16_t *)
cpu->
cd.
sh.host_load[addr >> 12];
801 data = p[(addr & 0xfff) >> 1];
818 X(mov_l_arg1_postinc_to_arg0)
821 uint32_t *p = (uint32_t *)
cpu->
cd.
sh.host_load[addr >> 12];
825 data = p[(addr & 0xfff) >> 2];
842 X(mov_l_arg1_postinc_to_arg0_md)
845 uint32_t *p = (uint32_t *)
cpu->
cd.
sh.host_load[addr >> 12];
851 data = p[(addr & 0xfff) >> 2];
873 X(mov_l_arg1_postinc_to_arg0_fp)
876 uint32_t *p = (uint32_t *)
cpu->
cd.
sh.host_load[addr >> 12];
882 data = p[(addr & 0xfff) >> 2];
907 int8_t *p = (int8_t *)
cpu->
cd.
sh.host_load[addr >> 12];
911 data = p[addr & 0xfff];
926 int16_t *p = (int16_t *)
cpu->
cd.
sh.host_load[addr >> 12];
930 data = p[(addr & 0xfff) >> 1];
949 uint32_t *p = (uint32_t *)
cpu->
cd.
sh.host_load[addr >> 12];
953 data = p[(addr & 0xfff) >> 2];
972 ((
ic->arg[0] >> 4) << 2);
973 uint32_t *p = (uint32_t *)
cpu->
cd.
sh.host_load[addr >> 12];
977 data = p[(addr & 0xfff) >> 2];
996 uint8_t *p = (uint8_t *)
cpu->
cd.
sh.host_load[addr >> 12];
1000 data = p[addr & 0xfff];
1015 uint16_t *p = (uint16_t *)
cpu->
cd.
sh.host_load[addr >> 12];
1019 data = p[(addr & 0xfff) >> 1];
1058 X(mov_b_store_rm_rn)
1061 uint8_t *p = (uint8_t *)
cpu->
cd.
sh.host_store[addr >> 12];
1065 p[addr & 0xfff] =
data;
1075 X(mov_w_store_rm_rn)
1078 uint16_t *p = (uint16_t *)
cpu->
cd.
sh.host_store[addr >> 12];
1087 p[(addr & 0xfff) >> 1] =
data;
1097 X(mov_l_store_rm_rn)
1100 uint32_t *p = (uint32_t *)
cpu->
cd.
sh.host_store[addr >> 12];
1109 p[(addr & 0xfff) >> 2] =
data;
1122 uint32_t *p = (uint32_t *)
cpu->
cd.
sh.host_store[addr >> 12];
1132 size_t r0 =
ic->arg[1];
1133 int ofs = (r0 - (size_t)&
cpu->
cd.
sh.
fr[0]) /
sizeof(uint32_t);
1135 fatal(
"ODD fmov_frm_rn: TODO");
1140 uint32_t data2 =
reg(
ic->arg[0] + 4);
1158 p[(addr & 0xfff) >> 2] =
data;
1171 uint32_t *p = (uint32_t *)
cpu->
cd.
sh.host_store[addr >> 12];
1177 fatal(
"fmov_frm_r0_rn: sz=1 (register pair): TODO\n");
1188 p[(addr & 0xfff) >> 2] =
data;
1198 X(fmov_frm_predec_rn)
1202 uint32_t *p = (uint32_t *)
cpu->
cd.
sh.host_store[addr >> 12];
1203 size_t r0 =
ic->arg[0];
1207 int ofs0 = (r0 - (size_t)&
cpu->
cd.
sh.
fr[0]) /
sizeof(uint32_t);
1222 p[(addr & 0xfff) >> 2] = data;
1250 int8_t *p = (int8_t *)
cpu->
cd.
sh.host_store[addr >> 12];
1253 p[addr & 0xfff] =
data;
1266 uint16_t *p = (uint16_t *)
cpu->
cd.
sh.host_store[addr >> 12];
1275 p[(addr & 0xfff) >> 1] =
data;
1288 uint32_t *p = (uint32_t *)
cpu->
cd.
sh.host_store[addr >> 12];
1297 p[(addr & 0xfff) >> 2] =
data;
1307 X(mov_b_r0_disp_gbr)
1310 uint8_t *p = (uint8_t *)
cpu->
cd.
sh.host_store[addr >> 12];
1313 p[addr & 0xfff] =
data;
1323 X(mov_w_r0_disp_gbr)
1326 uint16_t *p = (uint16_t *)
cpu->
cd.
sh.host_store[addr >> 12];
1335 p[(addr & 0xfff) >> 1] =
data;
1345 X(mov_l_r0_disp_gbr)
1348 uint32_t *p = (uint32_t *)
cpu->
cd.
sh.host_store[addr >> 12];
1357 p[(addr & 0xfff) >> 2] =
data;
1370 ((
ic->arg[1] >> 4) << 2);
1371 uint32_t *p = (uint32_t *)
cpu->
cd.
sh.host_store[addr >> 12];
1380 p[(addr & 0xfff) >> 2] =
data;
1393 uint8_t *p = (uint8_t *)
cpu->
cd.
sh.host_store[addr >> 12];
1397 p[addr & 0xfff] =
data;
1410 uint16_t *p = (uint16_t *)
cpu->
cd.
sh.host_store[addr >> 12];
1419 p[(addr & 0xfff) >> 1] =
data;
1449 uint64_t res =
reg(
ic->arg[1]);
1450 res += (uint64_t)
reg(
ic->arg[0]);
1453 if ((res >> 32) & 1)
1457 reg(
ic->arg[1]) = (uint32_t) res;
1465 uint64_t res =
reg(
ic->arg[1]);
1466 res -= (uint64_t)
reg(
ic->arg[0]);
1469 if ((res >> 32) & 1)
1473 reg(
ic->arg[1]) = (uint32_t) res;
1484 if (
reg(
ic->arg[0]))
1491 uint32_t rn =
reg(
ic->arg[1]), rm =
reg(
ic->arg[0]);
1492 reg(
ic->arg[1]) = (rn >> 16) | (rm << 16);
1510 int q =
reg(
ic->arg[1]) & 0x80000000;
1511 int m =
reg(
ic->arg[0]) & 0x80000000;
1526 uint32_t op1 =
reg(
ic->arg[0]), op2 =
reg(
ic->arg[1]);
1530 op2_64 = (uint32_t) ((op2 << 1) + t);
1532 op2_64 -= (uint64_t)op1;
1534 op2_64 += (uint64_t)op1;
1535 q ^= m ^ ((op2_64 >> 32) & 1);
1542 reg(
ic->arg[1]) = (uint32_t) op2_64;
1563 (int32_t)(int16_t)
reg(
ic->arg[1]);
1568 (int32_t)(uint16_t)
reg(
ic->arg[1]);
1572 uint64_t rm = (int32_t)
reg(
ic->arg[0]), rn = (int32_t)
reg(
ic->arg[1]);
1573 uint64_t res = rm * rn;
1579 uint64_t rm =
reg(
ic->arg[0]), rn =
reg(
ic->arg[1]), res;
1623 if ((int32_t)
reg(
ic->arg[1]) >= (int32_t)
reg(
ic->arg[0]))
1637 if ((int32_t)
reg(
ic->arg[1]) > (int32_t)
reg(
ic->arg[0]))
1644 if ((int32_t)
reg(
ic->arg[1]) >= 0)
1651 if ((int32_t)
reg(
ic->arg[1]) > 0)
1658 uint32_t r0 =
reg(
ic->arg[0]), r1 =
reg(
ic->arg[1]);
1660 if ((r0 & 0xff000000) == (r1 & 0xff000000))
1662 else if ((r0 & 0xff0000) == (r1 & 0xff0000))
1664 else if ((r0 & 0xff00) == (r1 & 0xff00))
1666 else if ((r0 & 0xff) == (r1 & 0xff))
1691 uint32_t rn =
reg(
ic->arg[1]);
1692 if (rn & 0x80000000)
1696 reg(
ic->arg[1]) = rn << 1;
1700 uint32_t rn =
reg(
ic->arg[1]);
1705 reg(
ic->arg[1]) = rn >> 1;
1709 uint32_t rn =
reg(
ic->arg[1]), x;
1710 if (rn & 0x80000000) {
1717 reg(
ic->arg[1]) = (rn << 1) | x;
1721 uint32_t rn =
reg(
ic->arg[1]);
1726 reg(
ic->arg[1]) = (rn >> 1) | (rn << 31);
1730 int32_t rn =
reg(
ic->arg[1]);
1735 reg(
ic->arg[1]) = rn >> 1;
1739 uint32_t rn =
reg(
ic->arg[1]), top;
1740 top = rn & 0x80000000;
1748 reg(
ic->arg[1]) = rn;
1752 uint32_t rn =
reg(
ic->arg[1]), bottom;
1761 reg(
ic->arg[1]) = rn;
1765 uint32_t rn =
reg(
ic->arg[1]) - 1;
1770 reg(
ic->arg[1]) = rn;
1789 int32_t rn =
reg(
ic->arg[1]);
1790 int32_t rm =
reg(
ic->arg[0]);
1802 reg(
ic->arg[1]) = rn;
1806 uint32_t rn =
reg(
ic->arg[1]);
1807 int32_t rm =
reg(
ic->arg[0]);
1817 reg(
ic->arg[1]) = rn;
1835 target +=
ic->arg[0];
1852 cpu->
cd.
sh.next_ic = (
struct sh_instr_call *)
ic->arg[0];
1862 target +=
ic->arg[0];
1881 target +=
ic->arg[0];
1904 cpu->
cd.
sh.next_ic = (
struct sh_instr_call *)
ic->arg[0];
1912 target +=
ic->arg[0] +
reg(
ic->arg[1]);
1930 target +=
ic->arg[0] +
reg(
ic->arg[1]);
1949 target +=
ic->arg[0] +
reg(
ic->arg[1]);
1994 cpu->
cd.
sh.next_ic = (
struct sh_instr_call *)
ic->arg[1];
1999 cpu->
cd.
sh.next_ic = (
struct sh_instr_call *)
ic->arg[1];
2006 target +=
ic->arg[0];
2025 target +=
ic->arg[0];
2049 (
struct sh_instr_call *)
ic->arg[1];
2065 (
struct sh_instr_call *)
ic->arg[1];
2203 uint32_t old_hi, old_lo;
2235 X(copy_privileged_register)
2261 cpu->
cd.
sh.next_ic = ¬hing_call;
2325 r0 =
ic->arg[0]; r1 =
ic->arg[1];
2326 ofs0 = (r0 - (size_t)&
cpu->
cd.
sh.
fr[0]) /
sizeof(uint32_t);
2327 ofs1 = (r1 - (size_t)&
cpu->
cd.
sh.
fr[0]) /
sizeof(uint32_t);
2334 reg(r1 + 4) =
reg(r0 + 4);
2352 reg(
ic->arg[0]) = (uint32_t) (ieee >> 32);
2353 reg(
ic->arg[0] +
sizeof(uint32_t)) = (uint32_t) ieee;
2357 reg(
ic->arg[0]) = (uint32_t) ieee;
2375 int64_t r1 = ((uint64_t)
reg(
ic->arg[0]) << 32) +
2376 reg(
ic->arg[0] +
sizeof(uint32_t));
2405 reg(
ic->arg[0]) = (uint32_t) (ieee >> 32);
2406 reg(
ic->arg[0] +
sizeof(uint32_t)) = (uint32_t) ieee;
2415 r1 =
reg(
ic->arg[0] +
sizeof(uint32_t)) +
2416 ((uint64_t)
reg(
ic->arg[0]) << 32);
2436 double fpulAngle = ((double)
cpu->
cd.
sh.
fpul) * 2.0 * M_PI / 65536.0;
2441 reg(
ic->arg[0] +
sizeof(uint32_t)) =
2472 frm0.
f * frn0.
f + frm1.
f * frn1.
f +
2473 frm2.
f * frn2.
f + frm3.
f * frn3.
f;
2488 double frnp0 = 0.0, frnp1 = 0.0, frnp2 = 0.0, frnp3 = 0.0;
2498 for (i=0; i<16; i++)
2503 frnp0 += xmtrx[i*4].
f * frn[i].
f;
2506 frnp1 += xmtrx[i*4 + 1].
f * frn[i].
f;
2509 frnp2 += xmtrx[i*4 + 2].
f * frn[i].
f;
2512 frnp3 += xmtrx[i*4 + 3].
f * frn[i].
f;
2543 int ofs0 = (
ic->arg[0] - (size_t)&
cpu->
cd.
sh.
fr[0]) /
sizeof(uint32_t);
2545 fatal(
"TODO: fneg_frn odd register in double prec. mode.\n");
2551 reg(
ic->arg[0]) ^= 0x80000000;
2560 int ofs0 = (
ic->arg[0] - (size_t)&
cpu->
cd.
sh.
fr[0]) /
sizeof(uint32_t);
2562 fatal(
"TODO: fneg_frn odd register in double prec. mode.\n");
2568 reg(
ic->arg[0]) &= 0x7fffffff;
2579 r1 =
reg(
ic->arg[0] +
sizeof(uint32_t)) +
2580 ((uint64_t)
reg(
ic->arg[0]) << 32);
2583 reg(
ic->arg[0]) = (uint32_t) (ieee >> 32);
2584 reg(
ic->arg[0] +
sizeof(uint32_t)) = (uint32_t) ieee;
2587 int32_t ieee, r1 =
reg(
ic->arg[0]);
2590 reg(
ic->arg[0]) = ieee;
2604 fatal(
"Double-precision fsrra? TODO\n");
2609 int32_t ieee, r1 =
reg(
ic->arg[0]);
2613 reg(
ic->arg[0]) = ieee;
2638 int64_t r1, r2, ieee;
2641 r1 =
reg(
ic->arg[0] +
sizeof(uint32_t)) +
2642 ((uint64_t)
reg(
ic->arg[0]) << 32);
2643 r2 =
reg(
ic->arg[1] +
sizeof(uint32_t)) +
2644 ((uint64_t)
reg(
ic->arg[1]) << 32);
2648 result = op2.
f + op1.
f;
2650 reg(
ic->arg[1]) = (uint32_t) (ieee >> 32);
2651 reg(
ic->arg[1] +
sizeof(uint32_t)) = (uint32_t) ieee;
2654 uint32_t r1, r2, ieee;
2657 r1 =
reg(
ic->arg[0]);
2658 r2 =
reg(
ic->arg[1]);
2662 result = op2.
f + op1.
f;
2664 reg(
ic->arg[1]) = (uint32_t) ieee;
2675 int64_t r1, r2, ieee;
2677 r1 =
reg(
ic->arg[0] +
sizeof(uint32_t)) +
2678 ((uint64_t)
reg(
ic->arg[0]) << 32);
2679 r2 =
reg(
ic->arg[1] +
sizeof(uint32_t)) +
2680 ((uint64_t)
reg(
ic->arg[1]) << 32);
2683 result = op2.
f - op1.
f;
2685 reg(
ic->arg[1]) = (uint32_t) (ieee >> 32);
2686 reg(
ic->arg[1] +
sizeof(uint32_t)) = (uint32_t) ieee;
2689 uint32_t r1, r2, ieee;
2691 r1 =
reg(
ic->arg[0]);
2692 r2 =
reg(
ic->arg[1]);
2695 result = op2.
f - op1.
f;
2697 reg(
ic->arg[1]) = (uint32_t) ieee;
2708 int64_t r1, r2, ieee;
2711 r1 =
reg(
ic->arg[0] +
sizeof(uint32_t)) +
2712 ((uint64_t)
reg(
ic->arg[0]) << 32);
2713 r2 =
reg(
ic->arg[1] +
sizeof(uint32_t)) +
2714 ((uint64_t)
reg(
ic->arg[1]) << 32);
2718 result = op2.
f * op1.
f;
2720 reg(
ic->arg[1]) = (uint32_t) (ieee >> 32);
2721 reg(
ic->arg[1] +
sizeof(uint32_t)) = (uint32_t) ieee;
2724 uint32_t r1, r2, ieee;
2727 r1 =
reg(
ic->arg[0]);
2728 r2 =
reg(
ic->arg[1]);
2732 result = op2.
f * op1.
f;
2734 reg(
ic->arg[1]) = (uint32_t) ieee;
2745 int64_t r1, r2, ieee;
2748 r1 =
reg(
ic->arg[0] +
sizeof(uint32_t)) +
2749 ((uint64_t)
reg(
ic->arg[0]) << 32);
2750 r2 =
reg(
ic->arg[1] +
sizeof(uint32_t)) +
2751 ((uint64_t)
reg(
ic->arg[1]) << 32);
2756 result = op2.
f / op1.
f;
2762 reg(
ic->arg[1]) = (uint32_t) (ieee >> 32);
2763 reg(
ic->arg[1] +
sizeof(uint32_t)) = (uint32_t) ieee;
2766 uint32_t r1, r2, ieee;
2769 r1 =
reg(
ic->arg[0]);
2770 r2 =
reg(
ic->arg[1]);
2775 result = op2.
f / op1.
f;
2781 reg(
ic->arg[1]) = (uint32_t) ieee;
2787 int32_t r1, r2, fr0 =
cpu->
cd.
sh.
fr[0], ieee;
2796 reg(
ic->arg[1]) = ieee;
2807 r1 =
reg(
ic->arg[0] +
sizeof(uint32_t)) +
2808 ((uint64_t)
reg(
ic->arg[0]) << 32);
2809 r2 =
reg(
ic->arg[1] +
sizeof(uint32_t)) +
2810 ((uint64_t)
reg(
ic->arg[1]) << 32);
2815 uint32_t r1 =
reg(
ic->arg[0]), r2 =
reg(
ic->arg[1]);
2834 r1 =
reg(
ic->arg[0] +
sizeof(uint32_t)) +
2835 ((uint64_t)
reg(
ic->arg[0]) << 32);
2836 r2 =
reg(
ic->arg[1] +
sizeof(uint32_t)) +
2837 ((uint64_t)
reg(
ic->arg[1]) << 32);
2842 uint32_t r1 =
reg(
ic->arg[0]), r2 =
reg(
ic->arg[1]);
2880 uint32_t
addr =
reg(
ic->arg[1]), extaddr;
2883 if (addr < 0xe0000000U || addr >= 0xe4000000U)
2892 extaddr = addr & 0x03ffffe0;
2893 sq_nr = addr & 0x20? 1 : 0;
2918 fatal(
"Store Queue to external memory, when " 2919 "MMU enabled: Not yet implemented... TODO\n");
2924 for (ofs = 0; ofs < 32; ofs +=
sizeof(uint32_t)) {
2927 + sq_nr * 0x20, (
unsigned char *)
2944 uint8_t byte, newbyte;
2954 newbyte = byte | 0x80;
2986 fatal(
"SH prom_emul: unimplemented machine type.\n");
2992 cpu->
cd.
sh.next_ic = ¬hing_call;
2993 }
else if ((uint32_t)
cpu->
pc != old_pc) {
3014 X(bt_samepage_wait_for_variable)
3024 uint32_t *p = (uint32_t *)
cpu->
cd.
sh.host_load[addr >> 12];
3030 uint32_t
data = p[(addr & 0xfff) >> 2];
3074 if (
ic[-2].
f ==
instr(mov_l_disp_gbr_r0) &&
3075 ic[-1].f ==
instr(cmpeq_rm_rn) &&
3076 (
ic[-1].arg[0] == (size_t) &cpu->
cd.
sh.
r[0] ||
3077 ic[-1].arg[1] == (
size_t) &cpu->
cd.
sh.
r[0]) &&
3078 ic[0].arg[1] == (
size_t) &
ic[-2]) {
3079 ic[-2].f =
instr(bt_samepage_wait_for_variable);
3124 instr(to_be_translated)(cpu, cpu->
cd.
sh.next_ic);
3139 int low_pc = ((size_t)
ic - (
size_t)cpu->
cd.
sh.cur_ic_page)
3140 /
sizeof(
struct sh_instr_call);
3153 fatal(
"end_of_page2: fatal error, we're in a delay slot\n");
3171 uint32_t
addr, low_pc, iword;
3172 unsigned char *
page;
3173 unsigned char ib[2];
3174 int main_opcode, isize =
sizeof(ib);
3175 int in_crosspage_delayslot = 0, r8, r4, lo4, lo8;
3176 void (*samepage_function)(
struct cpu *,
struct sh_instr_call *);
3179 low_pc = ((size_t)
ic - (
size_t)cpu->
cd.
sh.cur_ic_page)
3180 /
sizeof(
struct sh_instr_call);
3186 in_crosspage_delayslot = 1;
3196 page = cpu->
cd.
sh.host_load[(uint32_t)addr >> 12];
3200 memcpy(ib, page + (addr & 0xfff), isize);
3205 fatal(
"to_be_translated(): read failed: TODO\n");
3211 uint16_t *p = (uint16_t *) ib;
3220 main_opcode = iword >> 12;
3221 r8 = (iword >> 8) & 0xf;
3222 r4 = (iword >> 4) & 0xf;
3227 #define DYNTRANS_TO_BE_TRANSLATED_HEAD 3229 #undef DYNTRANS_TO_BE_TRANSLATED_HEAD 3237 ic->arg[0] = (size_t)&cpu->
cd.
sh.
r[r4];
3238 ic->arg[1] = (
size_t)&cpu->
cd.
sh.
r[r8];
3240 switch (main_opcode) {
3245 ic->f =
instr(mov_b_rm_r0_rn);
3246 }
else if (lo4 == 0x5) {
3248 ic->f =
instr(mov_w_rm_r0_rn);
3249 }
else if (lo4 == 0x6) {
3251 ic->f =
instr(mov_l_rm_r0_rn);
3252 }
else if (lo4 == 0x7) {
3255 }
else if (iword == 0x000b) {
3260 }
else if (lo4 == 0xc) {
3262 ic->f =
instr(mov_b_r0_rm_rn);
3263 }
else if (lo4 == 0xd) {
3265 ic->f =
instr(mov_w_r0_rm_rn);
3266 }
else if (lo4 == 0xe) {
3268 ic->f =
instr(mov_l_r0_rm_rn);
3269 }
else if (iword == 0x0008) {
3272 }
else if (iword == 0x0018) {
3275 }
else if (iword == 0x0019) {
3278 }
else if (iword == 0x001b) {
3281 }
else if (iword == 0x0028) {
3284 }
else if (iword == 0x002b) {
3287 }
else if (iword == 0x0038) {
3290 }
else if (iword == 0x0048) {
3293 }
else if (iword == 0x0058) {
3296 }
else if ((lo8 & 0x8f) == 0x82) {
3298 ic->f =
instr(copy_privileged_register);
3299 ic->arg[0] = (size_t)&cpu->
cd.
sh.
r_bank[(lo8 >> 4) & 7];
3306 ic->f =
instr(copy_privileged_register);
3307 ic->arg[0] = (size_t)&cpu->
cd.
sh.
sr;
3315 ic->arg[0] = (int32_t) (addr &
3322 if (iword & 0x0f00) {
3324 fatal(
"Unimplemented NOP" 3342 ic->f =
instr(copy_privileged_register);
3347 ic->arg[0] = (int32_t) (addr &
3357 ic->arg[0] = (size_t)&cpu->
cd.
sh.
pr;
3360 ic->f =
instr(copy_privileged_register);
3364 ic->f =
instr(copy_privileged_register);
3368 ic->f =
instr(copy_fp_register);
3370 ic->arg[1] = (
size_t)&cpu->
cd.
sh.
r[r8];
3373 ic->f =
instr(copy_fp_register);
3375 ic->arg[1] = (
size_t)&cpu->
cd.
sh.
r[r8];
3401 ic->f =
instr(copy_privileged_register);
3403 ic->arg[1] = (
size_t)&cpu->
cd.
sh.
r[r8];
3406 fatal(
"Unimplemented opcode 0x%x," 3407 "0x%03x\n", main_opcode,
3415 ic->f =
instr(mov_l_rm_disp_rn);
3416 ic->arg[1] = r8 + (lo4 << 4);
3422 ic->f =
instr(mov_b_store_rm_rn);
3425 ic->f =
instr(mov_w_store_rm_rn);
3428 ic->f =
instr(mov_l_store_rm_rn);
3431 ic->f =
instr(mov_b_rm_predec_rn);
3434 ic->f =
instr(mov_w_rm_predec_rn);
3437 ic->f =
instr(mov_l_rm_predec_rn);
3469 fatal(
"Unimplemented opcode 0x%x,0x%x\n",
3514 fatal(
"Unimplemented opcode 0x%x,0x%x\n",
3523 }
else if (lo4 == 0xd) {
3525 }
else if ((lo8 & 0x8f) == 0x83) {
3527 ic->f =
instr(stc_l_rm_predec_rn_md);
3530 }
else if ((lo8 & 0x8f) == 0x87) {
3532 ic->f =
instr(mov_l_arg1_postinc_to_arg0_md);
3533 ic->arg[0] = (size_t)&cpu->
cd.
sh.
r_bank[(lo8 >> 4) & 7];
3534 }
else if ((lo8 & 0x8f) == 0x8e) {
3536 ic->f =
instr(copy_privileged_register);
3537 ic->arg[0] = (size_t)&cpu->
cd.
sh.
r[r8];
3538 ic->arg[1] = (
size_t)&cpu->
cd.
sh.
r_bank[(lo8 >> 4) & 7];
3548 ic->f =
instr(mov_l_rm_predec_rn);
3552 ic->f =
instr(stc_l_rm_predec_rn_md);
3553 ic->arg[0] = (size_t)&cpu->
cd.
sh.
sr;
3562 ic->f =
instr(mov_l_arg1_postinc_to_arg0);
3566 ic->f =
instr(mov_l_arg1_postinc_to_arg0_md);
3567 ic->arg[0] = (size_t)&cpu->
cd.
sh.
sr;
3577 ic->arg[0] = (size_t)&cpu->
cd.
sh.
r[r8];
3585 ic->arg[0] = (size_t)&cpu->
cd.
sh.
r[r8];
3586 ic->arg[1] = (addr & 0xffe) + 4;
3598 ic->f =
instr(mov_l_rm_predec_rn);
3602 ic->f =
instr(mov_l_rm_predec_rn);
3609 ic->f =
instr(mov_l_arg1_postinc_to_arg0);
3613 ic->f =
instr(mov_l_arg1_postinc_to_arg0);
3624 ic->arg[0] = (size_t)&cpu->
cd.
sh.
r[r8];
3632 ic->arg[0] = (size_t)&cpu->
cd.
sh.
r[r8];
3642 ic->f =
instr(mov_l_rm_predec_rn);
3643 ic->arg[0] = (size_t)&cpu->
cd.
sh.
pr;
3644 ic->arg[1] = (
size_t)&cpu->
cd.
sh.
r[r8];
3647 ic->f =
instr(stc_l_rm_predec_rn_md);
3657 ic->f =
instr(mov_l_arg1_postinc_to_arg0);
3658 ic->arg[0] = (size_t)&cpu->
cd.
sh.
pr;
3661 ic->f =
instr(mov_l_arg1_postinc_to_arg0_md);
3672 ic->arg[0] = (size_t)&cpu->
cd.
sh.
r[r8];
3673 ic->arg[1] = (
size_t)&cpu->
cd.
sh.
pr;
3680 ic->arg[0] = (size_t)&cpu->
cd.
sh.
r[r8];
3681 ic->arg[1] = (addr & 0xffe) + 4;
3684 ic->f =
instr(copy_privileged_register);
3685 ic->arg[0] = (size_t)&cpu->
cd.
sh.
r[r8];
3689 ic->f =
instr(stc_l_rm_predec_rn_md);
3693 ic->f =
instr(mov_l_arg1_postinc_to_arg0_md);
3697 ic->f =
instr(copy_privileged_register);
3698 ic->arg[0] = (size_t)&cpu->
cd.
sh.
r[r8];
3702 ic->f =
instr(stc_l_rm_predec_rn_md);
3706 ic->f =
instr(mov_l_arg1_postinc_to_arg0_md);
3710 ic->f =
instr(copy_privileged_register);
3711 ic->arg[0] = (size_t)&cpu->
cd.
sh.
r[r8];
3715 ic->f =
instr(mov_l_rm_predec_rn);
3717 ic->arg[1] = (
size_t)&cpu->
cd.
sh.
r[r8];
3720 ic->f =
instr(mov_l_arg1_postinc_to_arg0_fp);
3724 ic->f =
instr(copy_fp_register);
3725 ic->arg[0] = (size_t)&cpu->
cd.
sh.
r[r8];
3729 ic->f =
instr(mov_l_rm_predec_rn);
3731 ic->arg[1] = (
size_t)&cpu->
cd.
sh.
r[r8];
3736 ic->f =
instr(mov_l_arg1_postinc_to_arg0_fp);
3744 ic->f =
instr(copy_privileged_register);
3745 ic->arg[0] = (size_t)&cpu->
cd.
sh.
r[r8];
3749 fatal(
"Unimplemented opcode 0x%x," 3750 "0x%02x\n", main_opcode, lo8);
3757 ic->f =
instr(mov_l_disp_rm_rn);
3758 ic->arg[0] = r4 + (lo4 << 4);
3776 ic->f =
instr(mov_b_arg1_postinc_to_arg0);
3778 ic->arg[1] = (size_t)&cpu->
cd.
sh.
r[r4];
3779 ic->arg[0] = (
size_t)&cpu->
cd.
sh.
r[r8];
3782 ic->f =
instr(mov_w_arg1_postinc_to_arg0);
3784 ic->arg[1] = (size_t)&cpu->
cd.
sh.
r[r4];
3785 ic->arg[0] = (
size_t)&cpu->
cd.
sh.
r[r8];
3788 ic->f =
instr(mov_l_arg1_postinc_to_arg0);
3790 ic->arg[1] = (size_t)&cpu->
cd.
sh.
r[r4];
3791 ic->arg[0] = (
size_t)&cpu->
cd.
sh.
r[r8];
3825 fatal(
"Unimplemented opcode 0x%x,0x%x\n",
3833 ic->arg[0] = (int8_t)lo8;
3834 ic->arg[1] = (size_t)&cpu->
cd.
sh.
r[r8];
3847 ic->arg[0] = (int8_t)lo8 * 2 +
3850 samepage_function = NULL;
3854 ic->f =
instr(mov_b_r0_disp_rn);
3855 ic->arg[0] = (size_t)&cpu->
cd.
sh.
r[r4];
3859 ic->f =
instr(mov_w_r0_disp_rn);
3860 ic->arg[0] = (size_t)&cpu->
cd.
sh.
r[r4];
3861 ic->arg[1] = lo4 * 2;
3864 ic->f =
instr(mov_b_disp_rn_r0);
3865 ic->arg[0] = (size_t)&cpu->
cd.
sh.
r[r4];
3869 ic->f =
instr(mov_w_disp_rn_r0);
3870 ic->arg[0] = (size_t)&cpu->
cd.
sh.
r[r4];
3871 ic->arg[1] = lo4 * 2;
3875 ic->arg[0] = (int8_t)lo8;
3883 samepage_function =
instr(bf_samepage);
3887 samepage_function =
instr(bt_s_samepage);
3891 samepage_function =
instr(bf_s_samepage);
3894 fatal(
"Unimplemented opcode 0x%x,0x%x\n",
3900 if (samepage_function != NULL &&
ic->arg[0] < 0x1000 &&
3901 (addr & 0xfff) < 0xffe) {
3902 ic->arg[1] = (size_t) (cpu->
cd.
sh.cur_ic_page +
3904 ic->f = samepage_function;
3913 ic->f =
instr(mov_w_disp_pc_rn);
3919 if (
ic->arg[0] < 0x1000 && page != NULL) {
3920 uint16_t *p = (uint16_t *) page;
3921 uint16_t
data = p[
ic->arg[0] >> 1];
3927 ic->arg[0] = (int16_t) data;
3933 samepage_function = NULL;
3935 switch (main_opcode) {
3938 samepage_function =
instr(bra_samepage);
3946 samepage_function =
instr(bsr_samepage);
3953 (((int32_t)(int16_t)((iword & 0xfff) << 4)) >> 3) );
3956 if (samepage_function != NULL &&
ic->arg[0] < 0x1000 &&
3957 (addr & 0xfff) < 0xffe) {
3958 ic->arg[0] = (size_t) (cpu->
cd.
sh.cur_ic_page +
3960 ic->f = samepage_function;
3967 ic->f =
instr(mov_b_r0_disp_gbr);
3971 ic->f =
instr(mov_w_r0_disp_gbr);
3972 ic->arg[1] = lo8 << 1;
3975 ic->f =
instr(mov_l_r0_disp_gbr);
3976 ic->arg[1] = lo8 << 2;
3980 ic->arg[0] = lo8 << 2;
3983 ic->f =
instr(mov_b_disp_gbr_r0);
3987 ic->f =
instr(mov_w_disp_gbr_r0);
3988 ic->arg[1] = lo8 << 1;
3991 ic->f =
instr(mov_l_disp_gbr_r0);
3992 ic->arg[1] = lo8 << 2;
3996 ic->arg[0] = lo8 * 4 + (addr &
4017 ic->f =
instr(and_b_imm_r0_gbr);
4021 ic->f =
instr(xor_b_imm_r0_gbr);
4025 ic->f =
instr(or_b_imm_r0_gbr);
4029 fatal(
"Unimplemented opcode 0x%x,0x%x\n",
4036 ic->f =
instr(mov_l_disp_pc_rn);
4042 if (
ic->arg[0] < 0x1000 && page != NULL) {
4043 uint32_t *p = (uint32_t *) page;
4044 uint32_t
data = p[
ic->arg[0] >> 2];
4056 ic->arg[0] = (int8_t)lo8;
4057 ic->arg[1] = (size_t)&cpu->
cd.
sh.
r[r8];
4066 ic->arg[0] = (size_t)&cpu->
cd.
sh.
fr[r4];
4067 ic->arg[1] = (
size_t)&cpu->
cd.
sh.
fr[r8];
4068 }
else if (lo4 == 0x1) {
4071 ic->arg[0] = (size_t)&cpu->
cd.
sh.
fr[r4];
4072 ic->arg[1] = (
size_t)&cpu->
cd.
sh.
fr[r8];
4073 }
else if (lo4 == 0x2) {
4076 ic->arg[0] = (size_t)&cpu->
cd.
sh.
fr[r4];
4077 ic->arg[1] = (
size_t)&cpu->
cd.
sh.
fr[r8];
4078 }
else if (lo4 == 0x3) {
4081 ic->arg[0] = (size_t)&cpu->
cd.
sh.
fr[r4];
4082 ic->arg[1] = (
size_t)&cpu->
cd.
sh.
fr[r8];
4083 }
else if (lo4 == 0x4) {
4085 ic->f =
instr(fcmp_eq_frm_frn);
4086 ic->arg[0] = (size_t)&cpu->
cd.
sh.
fr[r4];
4087 ic->arg[1] = (
size_t)&cpu->
cd.
sh.
fr[r8];
4088 }
else if (lo4 == 0x5) {
4090 ic->f =
instr(fcmp_gt_frm_frn);
4091 ic->arg[0] = (size_t)&cpu->
cd.
sh.
fr[r4];
4092 ic->arg[1] = (
size_t)&cpu->
cd.
sh.
fr[r8];
4093 }
else if (lo4 == 0x6) {
4095 ic->f =
instr(fmov_r0_rm_frn);
4096 ic->arg[0] = (size_t)&cpu->
cd.
sh.
r[r4];
4097 ic->arg[1] = (
size_t)&cpu->
cd.
sh.
fr[r8];
4098 }
else if (lo4 == 0x7) {
4100 ic->f =
instr(fmov_frm_r0_rn);
4101 ic->arg[0] = (size_t)&cpu->
cd.
sh.
fr[r4];
4102 ic->arg[1] = (
size_t)&cpu->
cd.
sh.
r[r8];
4103 }
else if (lo4 == 0x8) {
4106 ic->arg[0] = (size_t)&cpu->
cd.
sh.
r[r4];
4107 ic->arg[1] = (
size_t)&cpu->
cd.
sh.
fr[r8];
4108 }
else if (lo4 == 0x9) {
4110 ic->f =
instr(fmov_rm_postinc_frn);
4111 ic->arg[0] = (size_t)&cpu->
cd.
sh.
r[r4];
4112 ic->arg[1] = (
size_t)&cpu->
cd.
sh.
fr[r8];
4113 }
else if (lo4 == 0xa) {
4116 ic->arg[0] = (size_t)&cpu->
cd.
sh.
fr[r4];
4117 ic->arg[1] = (
size_t)&cpu->
cd.
sh.
r[r8];
4118 }
else if (lo4 == 0xb) {
4120 ic->f =
instr(fmov_frm_predec_rn);
4121 ic->arg[0] = (size_t)&cpu->
cd.
sh.
fr[r4];
4122 ic->arg[1] = (
size_t)&cpu->
cd.
sh.
r[r8];
4123 }
else if (lo4 == 0xc) {
4126 ic->arg[0] = (size_t)&cpu->
cd.
sh.
fr[r4];
4127 ic->arg[1] = (
size_t)&cpu->
cd.
sh.
fr[r8];
4128 }
else if (lo8 == 0x0d) {
4130 ic->f =
instr(copy_fp_register);
4132 ic->arg[1] = (
size_t)&cpu->
cd.
sh.
fr[r8];
4133 }
else if (lo8 == 0x1d) {
4135 ic->f =
instr(copy_fp_register);
4136 ic->arg[0] = (size_t)&cpu->
cd.
sh.
fr[r8];
4138 }
else if (lo8 == 0x2d) {
4140 ic->f =
instr(float_fpul_frn);
4141 ic->arg[0] = (size_t)&cpu->
cd.
sh.
fr[r8];
4142 }
else if (lo8 == 0x3d) {
4145 ic->arg[0] = (size_t)&cpu->
cd.
sh.
fr[r8];
4146 }
else if (lo8 == 0x4d) {
4149 ic->arg[0] = (size_t)&cpu->
cd.
sh.
fr[r8];
4150 }
else if (lo8 == 0x5d) {
4153 ic->arg[0] = (size_t)&cpu->
cd.
sh.
fr[r8];
4154 }
else if (lo8 == 0x6d) {
4157 ic->arg[0] = (size_t)&cpu->
cd.
sh.
fr[r8];
4158 }
else if (lo8 == 0x7d) {
4161 ic->arg[0] = (size_t)&cpu->
cd.
sh.
fr[r8];
4162 }
else if (lo8 == 0x8d) {
4165 ic->arg[0] = (size_t)&cpu->
cd.
sh.
fr[r8];
4166 ic->arg[1] = 0x00000000;
4167 }
else if (lo8 == 0x9d) {
4170 ic->arg[0] = (size_t)&cpu->
cd.
sh.
fr[r8];
4171 ic->arg[1] = 0x3f800000;
4172 }
else if ((iword & 0x01ff) == 0x00ad) {
4174 ic->f =
instr(fcnvsd_fpul_drn);
4175 ic->arg[0] = (size_t)&cpu->
cd.
sh.
fr[r8];
4176 }
else if ((iword & 0x01ff) == 0x00bd) {
4178 ic->f =
instr(fcnvds_drm_fpul);
4179 ic->arg[0] = (size_t)&cpu->
cd.
sh.
fr[r8];
4180 }
else if (lo8 == 0xed) {
4183 ic->arg[0] = (size_t)&cpu->
cd.
sh.
fr[(r8<<2) & 0xc];
4184 ic->arg[1] = (size_t)&cpu->
cd.
sh.
fr[r8 & 0xc];
4185 }
else if ((iword & 0x01ff) == 0x00fd) {
4188 ic->arg[0] = (size_t)&cpu->
cd.
sh.
fr[r8];
4189 }
else if (iword == 0xf3fd) {
4192 }
else if (iword == 0xfbfd) {
4195 }
else if ((iword & 0xf3ff) == 0xf1fd) {
4197 ic->f =
instr(ftrv_xmtrx_fvn);
4198 ic->arg[0] = (size_t)&cpu->
cd.
sh.
fr[r8 & 0xc];
4199 }
else if (lo4 == 0xe) {
4201 ic->f =
instr(fmac_fr0_frm_frn);
4202 ic->arg[0] = (size_t)&cpu->
cd.
sh.
fr[r4];
4203 ic->arg[1] = (
size_t)&cpu->
cd.
sh.
fr[r8];
4206 fatal(
"Unimplemented opcode 0x%x,0x%02x\n",
4213 fatal(
"Unimplemented main opcode 0x%x\n", main_opcode);
4218 #define DYNTRANS_TO_BE_TRANSLATED_TAIL 4220 #undef DYNTRANS_TO_BE_TRANSLATED_TAIL
#define SH_INSTR_ALIGNMENT_SHIFT
uint32_t r_bank[SH_N_GPRS_BANKED]
void fatal(const char *fmt,...)
#define SH4_MMUCR_URC_MASK
void COMBINE() nop(struct cpu *cpu, struct mips_instr_call *ic, int low_addr)
struct arm_instr_call * ic
void f(int s, int func, int only_name)
void ieee_interpret_float_value(uint64_t x, struct ieee_float_value *fvp, int fmt)
void sh_update_fpscr(struct cpu *cpu, uint32_t new_fpscr)
void sh_exception(struct cpu *cpu, int expevt, int intevt, uint32_t vaddr)
#define SH4_PTEH_ASID_MASK
#define EMUL_LITTLE_ENDIAN
int translation_readahead
#define quick_pc_to_pointers(cpu)
int(* memory_rw)(struct cpu *cpu, struct memory *mem, uint64_t vaddr, unsigned char *data, size_t len, int writeflag, int cache_flags)
int sh_ipl_g_emul(struct cpu *)
uint32_t utlb_hi[SH_N_UTLB_ENTRIES]
#define SH_SR_IMASK_SHIFT
#define RES_INST_IF_NOT_MD
#define SH4_MMUCR_URC_SHIFT
#define MACHINE_DREAMCAST
void cpu_functioncall_trace(struct cpu *cpu, uint64_t f)
void cpu_functioncall_trace_return(struct cpu *cpu)
void COMBINE() bt_samepage(struct cpu *cpu, struct sh_instr_call *ic, int low_addr)
#define CACHE_INSTRUCTION
uint64_t ieee_store_float_value(double nf, int fmt, int nan)
#define FLOATING_POINT_AVAILABLE_CHECK
void sh_update_sr(struct cpu *cpu, uint32_t new_sr)
void dreamcast_emul(struct cpu *cpu)
#define SH_IC_ENTRIES_PER_PAGE
#define EXCEPTION_IN_DELAY_SLOT
addr & if(addr >=0x24 &&page !=NULL)
#define N_SAFE_DYNTRANS_LIMIT
uint32_t utlb_lo[SH_N_UTLB_ENTRIES]
void(* invalidate_translation_caches)(struct cpu *, uint64_t paddr, int flags)