vripreg.h Source File

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vripreg.h
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1 /* $NetBSD: vripreg.h,v 1.8 2003/04/01 02:33:52 igy Exp $ */
2 
3 #ifndef VRIPREG_H
4 #define VRIPREG_H
5 
6 /*-
7  * Copyright (c) 1999
8  * Shin Takemura and PocketBSD Project. All rights reserved.
9  * Copyright (c) 2001 SATO Kazumi, All rights reserved.
10  *
11  * Redistribution and use in source and binary forms, with or without
12  * modification, are permitted provided that the following conditions
13  * are met:
14  * 1. Redistributions of source code must retain the above copyright
15  * notice, this list of conditions and the following disclaimer.
16  * 2. Redistributions in binary form must reproduce the above copyright
17  * notice, this list of conditions and the following disclaimer in the
18  * documentation and/or other materials provided with the distribution.
19  * 3. All advertising materials mentioning features or use of this software
20  * must display the following acknowledgement:
21  * This product includes software developed by the PocketBSD project
22  * and its contributors.
23  * 4. Neither the name of the project nor the names of its contributors
24  * may be used to endorse or promote products derived from this software
25  * without specific prior written permission.
26  *
27  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
28  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
29  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
30  * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
31  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
35  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
36  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
37  * SUCH DAMAGE.
38  *
39  */
40 
41 #define VRIP_NO_ADDR 0x00000000
42 /*
43  * VR4181 registers
44  */
45 #define VR4181_BCU_ADDR 0x0a000000
46 #define VR4181_DMAAU_ADDR VRIP_NO_ADDR
47 #define VR4181_DCU_ADDR VRIP_NO_ADDR
48 #define VR4181_CMU_ADDR 0x0a000004
49 #define VR4181_ICU_ADDR 0x0a000080
50 #define VR4181_PMU_ADDR 0x0a0000a0
51 #define VR4181_RTC_ADDR 0x0a0000c0
52 #define VR4181_DSU_ADDR 0x0a0000e0
53 #define VR4181_GIU_ADDR VRIP_NO_ADDR /* XXX: no register */
54 #define VR4181_PIU_ADDR 0x0a000122
55 #define VR4181_AIU_ADDR 0x0a000160
56 #define VR4181_KIU_ADDR 0x0a000180
57 #define VR4181_DSIU_ADDR 0x0a0001a0
58 #define VR4181_LED_ADDR 0x0a000240
59 #define VR4181_SIU_ADDR 0x0c000010
60 #define VR4181_HSP_ADDR 0x0a000020
61 #define VR4181_FIR_ADDR 0x0a000000 /* XXX */
62 #define VR4181_MEMCON_ADDR 0x0a000300
63 #define VR4181_ISABRG_ADDR 0x0b0002c0
64 #define VR4181_ECU_ADDR 0x0b0008e0
65 #define VR4181_DCU81_ADDR 0x0a000020
66 #define VR4181_CSI81_ADDR 0x0b000900
67 #define VR4181_GIU81_ADDR 0x0b000300
68 #define VR4181_LCD_ADDR 0x0a000400
69 #define VR4181_SIU1_ADDR 0x0c000000
70 #define VR4181_SCU_ARR VRIP_NO_ADDR /* XXX: no register */
71 #define VR4181_SDRAMU_ADDR VRIP_NO_ADDR /* XXX: no register */
72 #define VR4181_PCI_ADDR VRIP_NO_ADDR /* XXX: no register */
73 #define VR4181_PCICONF_ADDR VRIP_NO_ADDR /* XXX: no register */
74 #define VR4181_CSI_ADDR VRIP_NO_ADDR /* XXX: no register */
75 
76 /*
77  * VR4101-4121 registers
78  */
79 #define VR4102_BCU_ADDR 0x0b000000
80 #define VR4102_DMAAU_ADDR 0x0b000020
81 #define VR4102_DCU_ADDR 0x0b000040
82 #define VR4102_CMU_ADDR 0x0b000060
83 #define VR4102_ICU_ADDR 0x0b000080
84 #define VR4102_PMU_ADDR 0x0b0000a0
85 #define VR4102_RTC_ADDR 0x0b0000c0
86 #define VR4102_DSU_ADDR 0x0b0000e0
87 #define VR4102_GIU_ADDR 0x0b000100
88 #define VR4102_PIU_ADDR 0x0b000120
89 #define VR4102_AIU_ADDR 0x0b000160
90 #define VR4102_KIU_ADDR 0x0b000180
91 #define VR4102_DSIU_ADDR 0x0b0001a0
92 #define VR4102_LED_ADDR 0x0b000240
93 #define VR4102_SIU_ADDR 0x0c000000
94 #define VR4102_HSP_ADDR 0x0c000020
95 #define VR4102_FIR_ADDR 0x0b000000 /* XXX */
96 #define VR4102_MEMCON_ADDR VRIP_NO_ADDR /* XXX: no register */
97 #define VR4102_ISABRG_ADDR VRIP_NO_ADDR /* XXX: no register */
98 #define VR4102_ECU_ADDR VRIP_NO_ADDR /* XXX: no register */
99 #define VR4102_DCU81_ADDR VRIP_NO_ADDR /* XXX: no register */
100 #define VR4102_CSI81_ADDR VRIP_NO_ADDR /* XXX: no register */
101 #define VR4102_GIU81_ADDR VRIP_NO_ADDR /* XXX: no register */
102 #define VR4102_SIU1_ADDR VRIP_NO_ADDR /* XXX: no register */
103 #define VR4102_SCU_ARR VRIP_NO_ADDR /* XXX: no register */
104 #define VR4102_SDRAMU_ADDR VRIP_NO_ADDR /* XXX: no register */
105 #define VR4102_PCI_ADDR VRIP_NO_ADDR /* XXX: no register */
106 #define VR4102_PCICONF_ADDR VRIP_NO_ADDR /* XXX: no register */
107 #define VR4102_CSI_ADDR VRIP_NO_ADDR /* XXX: no register */
108 /*
109  * VR4122 registers
110  */
111 #define VR4122_BCU_ADDR 0x0f000000
112 #define VR4122_DMAAU_ADDR 0x0f000020
113 #define VR4122_DCU_ADDR 0x0f000040
114 #define VR4122_CMU_ADDR 0x0f000060
115 #define VR4122_ICU_ADDR 0x0f000080
116 #define VR4122_PMU_ADDR 0x0f0000c0
117 #define VR4122_RTC_ADDR 0x0f000100
118 #define VR4122_DSU_ADDR VRIP_NO_ADDR /* XXX: no register */
119 #define VR4122_GIU_ADDR 0x0f000140
120 #define VR4122_PIU_ADDR VRIP_NO_ADDR /* XXX: no register */
121 #define VR4122_AIU_ADDR VRIP_NO_ADDR /* XXX: no register */
122 #define VR4122_KIU_ADDR VRIP_NO_ADDR /* XXX: no register */
123 #define VR4122_DSIU_ADDR 0x0f000820
124 #define VR4122_LED_ADDR 0x0f000180
125 #define VR4122_SIU_ADDR 0x0f000800
126 #define VR4122_HSP_ADDR VRIP_NO_ADDR /* XXX: no register */
127 #define VR4122_FIR_ADDR 0x0f000840 /* XXX */
128 #define VR4122_MEMCON_ADDR VRIP_NO_ADDR /* XXX: no register */
129 #define VR4122_ISABRG_ADDR VRIP_NO_ADDR /* XXX: no register */
130 #define VR4122_ECU_ADDR VRIP_NO_ADDR /* XXX: no register */
131 #define VR4122_DCU81_ADDR VRIP_NO_ADDR /* XXX: no register */
132 #define VR4122_CSI81_ADDR VRIP_NO_ADDR /* XXX: no register */
133 #define VR4122_GIU81_ADDR VRIP_NO_ADDR /* XXX: no register */
134 #define VR4122_SIU1_ADDR VRIP_NO_ADDR /* XXX: no register */
135 #define VR4122_SCU_ARR 0x0f001000
136 #define VR4122_SDRAMU_ADDR 0x0f000400
137 #define VR4122_PCI_ADDR 0x0f000c00
138 #define VR4122_PCICONF_ADDR 0x0f000d00
139 #define VR4122_CSI_ADDR 0x0f0001a0
140 
141 /*
142  * VRIP base address
143  *
144  * REQUIRE: opt_vr41xx.h, vrcpudef.h
145  */
146 #if 0
147 #include "opt_vr41xx.h"
148 #include <hpcmips/vr/vrcpudef.h>
149 #endif
150 
151 #if defined SINGLE_VRIP_BASE
152 
153 #if defined VRGROUP_4181
154 #define VRIP_BASE_ADDR 0x0a000000
155 
156 #define VRIP_BCU_ADDR VR4181_BCU_ADDR
157 #define VRIP_DMAAU_ADDR VR4181_DMAAU_ADDR
158 #define VRIP_DCU_ADDR VR4181_DCU_ADDR
159 #define VRIP_CMU_ADDR VR4181_CMU_ADDR
160 #define VRIP_ICU_ADDR VR4181_ICU_ADDR
161 #define VRIP_PMU_ADDR VR4181_PMU_ADDR
162 #define VRIP_RTC_ADDR VR4181_RTC_ADDR
163 #define VRIP_DSU_ADDR VR4181_DSU_ADDR
164 #define VRIP_GIU_ADDR VR4181_GIU_ADDR
165 #define VRIP_PIU_ADDR VR4181_PIU_ADDR
166 #define VRIP_AIU_ADDR VR4181_AIU_ADDR
167 #define VRIP_KIU_ADDR VR4181_KIU_ADDR
168 #define VRIP_DSIU_ADDR VR4181_DSIU_ADDR
169 #define VRIP_LED_ADDR VR4181_LED_ADDR
170 #define VRIP_SIU_ADDR VR4181_SIU_ADDR
171 #define VRIP_HSP_ADDR VR4181_HSP_ADDR
172 #define VRIP_FIR_ADDR VR4181_FIR_ADDR
173 #define VRIP_MEMCON_ADDR VR4181_MEMCON_ADDR
174 #define VRIP_ISABRG_ADDR VR4181_ISABRG_ADDR
175 #define VRIP_ECU_ADDR VR4181_ECU_ADDR
176 #define VRIP_DCU81_ADDR VR4181_DCU81_ADDR
177 #define VRIP_CSI81_ADDR VR4181_CSI81_ADDR
178 #define VRIP_GIU81_ADDR VR4181_GIU81_ADDR
179 #define VRIP_LCD_ADDR VR4181_LCD_ADDR
180 #define VRIP_SIU1_ADDR VR4181_SIU1_ADDR
181 #define VRIP_SCU_ARR VR4181_SCU_ARR /* XXX: no register */
182 #define VRIP_SDRAMU_ADDR VR4181_SDRAMU_ADDR /* XXX: no register */
183 #define VRIP_PCI_ADDR VR4181_PCI_ADDR /* XXX: no register */
184 #define VRIP_PCICONF_ADDR VR4181_PCICONF_ADDR /* XXX: no register */
185 #define VRIP_CSI_ADDR VR4181_CSI_ADDR /* XXX: no register */
186 
187 #endif /* VRGROUP_4181 */
188 
189 #if defined VRGROUP_4122_4131
190 #define VRIP_BASE_ADDR 0x0f000000
191 
192 #define VRIP_BCU_ADDR VR4122_BCU_ADDR
193 #define VRIP_DMAAU_ADDR VR4122_DMAAU_ADDR
194 #define VRIP_DCU_ADDR VR4122_DCU_ADDR
195 #define VRIP_CMU_ADDR VR4122_CMU_ADDR
196 #define VRIP_ICU_ADDR VR4122_ICU_ADDR
197 #define VRIP_PMU_ADDR VR4122_PMU_ADDR
198 #define VRIP_RTC_ADDR VR4122_RTC_ADDR
199 #define VRIP_DSU_ADDR VR4122_DSU_ADDR
200 #define VRIP_GIU_ADDR VR4122_GIU_ADDR
201 #define VRIP_PIU_ADDR VR4122_PIU_ADDR
202 #define VRIP_AIU_ADDR VR4122_AIU_ADDR
203 #define VRIP_KIU_ADDR VR4122_KIU_ADDR
204 #define VRIP_DSIU_ADDR VR4122_DSIU_ADDR
205 #define VRIP_LED_ADDR VR4122_LED_ADDR
206 #define VRIP_SIU_ADDR VR4122_SIU_ADDR
207 #define VRIP_HSP_ADDR VR4122_HSP_ADDR
208 #define VRIP_FIR_ADDR VR4122_FIR_ADDR
209 #define VRIP_MEMCON_ADDR VR4122_MEMCON_ADDR /* XXX: no register */
210 #define VRIP_ISABRG_ADDR VR4122_ISABRG_ADDR /* XXX: no register */
211 #define VRIP_ECU_ADDR VR4122_ECU_ADDR /* XXX: no register */
212 #define VRIP_DCU81_ADDR VR4122_DCU81_ADDR /* XXX: no register */
213 #define VRIP_CSI81_ADDR VR4122_CSI81_ADDR /* XXX: no register */
214 #define VRIP_GIU81_ADDR VR4122_CSI81_ADDR /* XXX: no register */
215 #define VRIP_SIU1_ADDR VR4122_SIU1_ADDR /* XXX: no register */
216 #define VRIP_SCU_ARR VR4122_SCU_ARR /* XXX: no register */
217 #define VRIP_SDRAMU_ADDR VR4122_SDRAMU_ADDR /* XXX: no register */
218 #define VRIP_PCI_ADDR VR4122_PCI_ADDR /* XXX: no register */
219 #define VRIP_PCICONF_ADDR VR4122_PCICONF_ADDR /* XXX: no register */
220 #define VRIP_CSI_ADDR VR4122_CSI_ADDR /* XXX: no register */
221 
222 #endif /* VRGROUP_4122_4131 */
223 
224 #if defined VRGROUP_4102_4121
225 #define VRIP_BASE_ADDR 0x0b000000
226 
227 #define VRIP_BCU_ADDR VR4102_BCU_ADDR
228 #define VRIP_DMAAU_ADDR VR4102_DMAAU_ADDR
229 #define VRIP_DCU_ADDR VR4102_DCU_ADDR
230 #define VRIP_CMU_ADDR VR4102_CMU_ADDR
231 #define VRIP_ICU_ADDR VR4102_ICU_ADDR
232 #define VRIP_PMU_ADDR VR4102_PMU_ADDR
233 #define VRIP_RTC_ADDR VR4102_RTC_ADDR
234 #define VRIP_DSU_ADDR VR4102_DSU_ADDR
235 #define VRIP_GIU_ADDR VR4102_GIU_ADDR
236 #define VRIP_PIU_ADDR VR4102_PIU_ADDR
237 #define VRIP_AIU_ADDR VR4102_AIU_ADDR
238 #define VRIP_KIU_ADDR VR4102_KIU_ADDR
239 #define VRIP_DSIU_ADDR VR4102_DSIU_ADDR
240 #define VRIP_LED_ADDR VR4102_LED_ADDR
241 #define VRIP_SIU_ADDR VR4102_SIU_ADDR
242 #define VRIP_HSP_ADDR VR4102_HSP_ADDR
243 #define VRIP_FIR_ADDR VR4102_FIR_ADDR
244 #define VRIP_MEMCON_ADDR VR4102_MEMCON_ADDR /* XXX: no register */
245 #define VRIP_ISABRG_ADDR VR4102_ISABRG_ADDR /* XXX: no register */
246 #define VRIP_ECU_ADDR VR4102_ECU_ADDR /* XXX: no register */
247 #define VRIP_DCU81_ADDR VR4102_DCU81_ADDR /* XXX: no register */
248 #define VRIP_CSI81_ADDR VR4102_CSI81_ADDR /* XXX: no register */
249 #define VRIP_GIU81_ADDR VR4102_GIU81_ADDR /* XXX: no register */
250 #define VRIP_SIU1_ADDR VR4102_SIU1_ADDR /* XXX: no register */
251 #define VRIP_SCU_ARR VR4102_SCU_ARR /* XXX: no register */
252 #define VRIP_SDRAMU_ADDR VR4102_SDRAMU_ADDR /* XXX: no register */
253 #define VRIP_PCI_ADDR VR4102_PCI_ADDR /* XXX: no register */
254 #define VRIP_PCICONF_ADDR VR4102_PCICONF_ADDR /* XXX: no register */
255 #define VRIP_CSI_ADDR VR4102_CSI_ADDR /* XXX: no register */
256 
257 #endif /* VRGROUP_4102_4121 */
258 
259 #endif /* SINGLE_VRIP_BASE */
260 
261 /*
262  * ICU interrupt level
263  */
264 /* reserved 62-31 */
265 #define VRIP_INTR_BCU 25
266 #define VRIP_INTR_CSI 24
267 #define VRIP_INTR_SCU 23
268 #define VRIP_INTR_PCI 22
269 #define VRIP_INTR_LCD 22 /* 4181 */
270 #define VRIP_INTR_DSIU 21
271 #define VRIP_INTR_DCU81 21 /* 4181 */
272 #define VRIP_INTR_FIR 20
273 #define VRIP_INTR_TCLK 19
274 #define VRIP_INTR_CSI81 19 /* 4181 */
275 #define VRIP_INTR_HSP 18
276 #define VRIP_INTR_ECU 18 /* 4181 */
277 #define VRIP_INTR_LED 17
278 #define VRIP_INTR_RTCL2 16
279 /* reserved 15,14 */
280 #define VRIP_INTR_DOZEPIU 13
281 #define VRIP_INTR_CLKRUN 12
282 #define VRIP_INTR_SOFT 11
283 #define VRIP_INTR_WRBERR 10
284 #define VRIP_INTR_SIU 9
285 #define VRIP_INTR_GIU 8
286 #define VRIP_INTR_KIU 7
287 #define VRIP_INTR_AIU 6
288 #define VRIP_INTR_PIU 5
289 /* reserved 4 VRC4171 use this ??? */
290 #define VRIP_INTR_ETIMER 3
291 #define VRIP_INTR_RTCL1 2
292 #define VRIP_INTR_POWER 1
293 #define VRIP_INTR_BAT 0
294 
295 #endif /* VRIPREG_H */

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