43 #define RL_IDR0 0x0000 44 #define RL_IDR1 0x0001 45 #define RL_IDR2 0x0002 46 #define RL_IDR3 0x0003 47 #define RL_IDR4 0x0004 48 #define RL_IDR5 0x0005 50 #define RL_MAR0 0x0008 51 #define RL_MAR1 0x0009 52 #define RL_MAR2 0x000A 53 #define RL_MAR3 0x000B 54 #define RL_MAR4 0x000C 55 #define RL_MAR5 0x000D 56 #define RL_MAR6 0x000E 57 #define RL_MAR7 0x000F 59 #define RL_TXSTAT0 0x0010 60 #define RL_TXSTAT1 0x0014 61 #define RL_TXSTAT2 0x0018 62 #define RL_TXSTAT3 0x001C 64 #define RL_TXADDR0 0x0020 65 #define RL_TXADDR1 0x0024 66 #define RL_TXADDR2 0x0028 67 #define RL_TXADDR3 0x002C 69 #define RL_RXADDR 0x0030 70 #define RL_RX_EARLY_BYTES 0x0034 71 #define RL_RX_EARLY_STAT 0x0036 72 #define RL_COMMAND 0x0037 73 #define RL_CURRXADDR 0x0038 74 #define RL_CURRXBUF 0x003A 77 #define RL_TXCFG 0x0040 78 #define RL_RXCFG 0x0044 79 #define RL_TIMERCNT 0x0048 80 #define RL_MISSEDPKT 0x004C 81 #define RL_EECMD 0x0050 82 #define RL_CFG0 0x0051 83 #define RL_CFG1 0x0052 85 #define RL_MEDIASTAT 0x0058 88 #define RL_HALTCLK 0x005B 89 #define RL_MULTIINTR 0x005C 90 #define RL_PCIREV 0x005E 92 #define RL_TXSTAT_ALL 0x0060 95 #define RL_BMCR 0x0062 96 #define RL_BMSR 0x0064 97 #define RL_ANAR 0x0066 98 #define RL_LPAR 0x0068 99 #define RL_ANER 0x006A 101 #define RL_DISCCNT 0x006C 102 #define RL_FALSECAR 0x006E 103 #define RL_NWAYTST 0x0070 104 #define RL_RX_ER 0x0072 105 #define RL_CSCFG 0x0074 112 #define RL_DUMPSTATS_LO 0x0010 113 #define RL_DUMPSTATS_HI 0x0014 114 #define RL_TXLIST_ADDR_LO 0x0020 115 #define RL_TXLIST_ADDR_HI 0x0024 116 #define RL_TXLIST_ADDR_HPRIO_LO 0x0028 117 #define RL_TXLIST_ADDR_HPRIO_HI 0x002C 118 #define RL_CFG2 0x0053 119 #define RL_TIMERINT 0x0054 120 #define RL_TXSTART 0x00D9 121 #define RL_CPLUS_CMD 0x00E0 122 #define RL_RXLIST_ADDR_LO 0x00E4 123 #define RL_RXLIST_ADDR_HI 0x00E8 124 #define RL_EARLY_TX_THRESH 0x00EC 129 #define RL_TIMERINT_8169 0x0058 130 #define RL_PHYAR 0x0060 131 #define RL_TBICSR 0x0064 132 #define RL_TBI_ANAR 0x0068 133 #define RL_TBI_LPAR 0x006A 134 #define RL_GMEDIASTAT 0x006C 135 #define RL_MAXRXPKTLEN 0x00DA 136 #define RL_GTXSTART 0x0038 140 #define RL_TXCFG_CLRABRT 0x00000001 141 #define RL_TXCFG_MAXDMA 0x00000700 142 #define RL_TXCFG_CRCAPPEND 0x00010000 143 #define RL_TXCFG_LOOPBKTST 0x00060000 144 #define RL_TXCFG_IFG2 0x00080000 145 #define RL_TXCFG_IFG 0x03000000 146 #define RL_TXCFG_HWREV 0x7C800000 148 #define RL_LOOPTEST_OFF 0x00000000 149 #define RL_LOOPTEST_ON 0x00020000 150 #define RL_LOOPTEST_ON_CPLUS 0x00060000 154 #define RL_HWREV_8169 0x00000000 155 #define RL_HWREV_8110S 0x00800000 156 #define RL_HWREV_8169S 0x04000000 157 #define RL_HWREV_8169_8110SB 0x10000000 158 #define RL_HWREV_8169_8110SC 0x18000000 159 #define RL_HWREV_8168_SPIN1 0x30000000 160 #define RL_HWREV_8100E_SPIN1 0x30800000 161 #define RL_HWREV_8101E 0x34000000 162 #define RL_HWREV_8168_SPIN2 0x38000000 163 #define RL_HWREV_8100E_SPIN2 0x38800000 164 #define RL_HWREV_8139 0x60000000 165 #define RL_HWREV_8139A 0x70000000 166 #define RL_HWREV_8139AG 0x70800000 167 #define RL_HWREV_8139B 0x78000000 168 #define RL_HWREV_8130 0x7C000000 169 #define RL_HWREV_8139C 0x74000000 170 #define RL_HWREV_8139D 0x74400000 171 #define RL_HWREV_8139CPLUS 0x74800000 172 #define RL_HWREV_8101 0x74c00000 173 #define RL_HWREV_8100 0x78800000 175 #define RL_TXDMA_16BYTES 0x00000000 176 #define RL_TXDMA_32BYTES 0x00000100 177 #define RL_TXDMA_64BYTES 0x00000200 178 #define RL_TXDMA_128BYTES 0x00000300 179 #define RL_TXDMA_256BYTES 0x00000400 180 #define RL_TXDMA_512BYTES 0x00000500 181 #define RL_TXDMA_1024BYTES 0x00000600 182 #define RL_TXDMA_2048BYTES 0x00000700 187 #define RL_TXSTAT_LENMASK 0x00001FFF 188 #define RL_TXSTAT_OWN 0x00002000 189 #define RL_TXSTAT_TX_UNDERRUN 0x00004000 190 #define RL_TXSTAT_TX_OK 0x00008000 191 #define RL_TXSTAT_EARLY_THRESH 0x003F0000 192 #define RL_TXSTAT_COLLCNT 0x0F000000 193 #define RL_TXSTAT_CARR_HBEAT 0x10000000 194 #define RL_TXSTAT_OUTOFWIN 0x20000000 195 #define RL_TXSTAT_TXABRT 0x40000000 196 #define RL_TXSTAT_CARRLOSS 0x80000000 201 #define RL_ISR_RX_OK 0x0001 202 #define RL_ISR_RX_ERR 0x0002 203 #define RL_ISR_TX_OK 0x0004 204 #define RL_ISR_TX_ERR 0x0008 205 #define RL_ISR_RX_OVERRUN 0x0010 206 #define RL_ISR_PKT_UNDERRUN 0x0020 207 #define RL_ISR_LINKCHG 0x0020 208 #define RL_ISR_FIFO_OFLOW 0x0040 209 #define RL_ISR_TX_DESC_UNAVAIL 0x0080 210 #define RL_ISR_SWI 0x0100 211 #define RL_ISR_CABLE_LEN_CHGD 0x2000 212 #define RL_ISR_PCS_TIMEOUT 0x4000 213 #define RL_ISR_TIMEOUT_EXPIRED 0x4000 214 #define RL_ISR_SYSTEM_ERR 0x8000 217 (RL_ISR_TX_OK|RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 218 RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 219 RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR) 221 #define RL_INTRS_CPLUS \ 222 (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 223 RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 224 RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED) 230 #define RL_MEDIASTAT_RXPAUSE 0x01 231 #define RL_MEDIASTAT_TXPAUSE 0x02 232 #define RL_MEDIASTAT_LINK 0x04 233 #define RL_MEDIASTAT_SPEED10 0x08 234 #define RL_MEDIASTAT_RXFLOWCTL 0x40 235 #define RL_MEDIASTAT_TXFLOWCTL 0x80 240 #define RL_RXCFG_RX_ALLPHYS 0x00000001 241 #define RL_RXCFG_RX_INDIV 0x00000002 242 #define RL_RXCFG_RX_MULTI 0x00000004 243 #define RL_RXCFG_RX_BROAD 0x00000008 244 #define RL_RXCFG_RX_RUNT 0x00000010 245 #define RL_RXCFG_RX_ERRPKT 0x00000020 246 #define RL_RXCFG_WRAP 0x00000080 247 #define RL_RXCFG_MAXDMA 0x00000700 248 #define RL_RXCFG_BURSZ 0x00001800 249 #define RL_RXCFG_FIFOTHRESH 0x0000E000 250 #define RL_RXCFG_EARLYTHRESH 0x07000000 252 #define RL_RXDMA_16BYTES 0x00000000 253 #define RL_RXDMA_32BYTES 0x00000100 254 #define RL_RXDMA_64BYTES 0x00000200 255 #define RL_RXDMA_128BYTES 0x00000300 256 #define RL_RXDMA_256BYTES 0x00000400 257 #define RL_RXDMA_512BYTES 0x00000500 258 #define RL_RXDMA_1024BYTES 0x00000600 259 #define RL_RXDMA_UNLIMITED 0x00000700 261 #define RL_RXBUF_8 0x00000000 262 #define RL_RXBUF_16 0x00000800 263 #define RL_RXBUF_32 0x00001000 264 #define RL_RXBUF_64 0x00001800 266 #define RL_RXFIFO_16BYTES 0x00000000 267 #define RL_RXFIFO_32BYTES 0x00002000 268 #define RL_RXFIFO_64BYTES 0x00004000 269 #define RL_RXFIFO_128BYTES 0x00006000 270 #define RL_RXFIFO_256BYTES 0x00008000 271 #define RL_RXFIFO_512BYTES 0x0000A000 272 #define RL_RXFIFO_1024BYTES 0x0000C000 273 #define RL_RXFIFO_NOTHRESH 0x0000E000 279 #define RL_RXSTAT_RXOK 0x00000001 280 #define RL_RXSTAT_ALIGNERR 0x00000002 281 #define RL_RXSTAT_CRCERR 0x00000004 282 #define RL_RXSTAT_GIANT 0x00000008 283 #define RL_RXSTAT_RUNT 0x00000010 284 #define RL_RXSTAT_BADSYM 0x00000020 285 #define RL_RXSTAT_BROAD 0x00002000 286 #define RL_RXSTAT_INDIV 0x00004000 287 #define RL_RXSTAT_MULTI 0x00008000 288 #define RL_RXSTAT_LENMASK 0xFFFF0000 290 #define RL_RXSTAT_UNFINISHED 0xFFF0 294 #define RL_CMD_EMPTY_RXBUF 0x0001 295 #define RL_CMD_TX_ENB 0x0004 296 #define RL_CMD_RX_ENB 0x0008 297 #define RL_CMD_RESET 0x0010 302 #define RL_EE_DATAOUT 0x01 303 #define RL_EE_DATAIN 0x02 304 #define RL_EE_CLK 0x04 305 #define RL_EE_SEL 0x08 306 #define RL_EE_MODE (0x40|0x80) 308 #define RL_EEMODE_OFF 0x00 309 #define RL_EEMODE_AUTOLOAD 0x40 310 #define RL_EEMODE_PROGRAM 0x80 311 #define RL_EEMODE_WRITECFG (0x80|0x40) 315 #define RL_9346_WRITE 0x5 316 #define RL_9346_READ 0x6 317 #define RL_9346_ERASE 0x7 318 #define RL_9346_EWEN 0x4 319 #define RL_9346_EWEN_ADDR 0x30 320 #define RL_9456_EWDS 0x4 321 #define RL_9346_EWDS_ADDR 0x00 323 #define RL_EECMD_WRITE 0x5 324 #define RL_EECMD_READ 0x6 325 #define RL_EECMD_ERASE 0x7 326 #define RL_EECMD_LEN 4 328 #define RL_EEADDR_LEN0 6 329 #define RL_EEADDR_LEN1 8 331 #define RL_EECMD_READ_6BIT 0x180 332 #define RL_EECMD_READ_8BIT 0x600 334 #define RL_EE_ID 0x00 335 #define RL_EE_PCI_VID 0x01 336 #define RL_EE_PCI_DID 0x02 338 #define RL_EE_EADDR 0x07 343 #define RL_MII_CLK 0x01 344 #define RL_MII_DATAIN 0x02 345 #define RL_MII_DATAOUT 0x04 346 #define RL_MII_DIR 0x80 351 #define RL_CFG0_ROM0 0x01 352 #define RL_CFG0_ROM1 0x02 353 #define RL_CFG0_ROM2 0x04 354 #define RL_CFG0_PL0 0x08 355 #define RL_CFG0_PL1 0x10 356 #define RL_CFG0_10MBPS 0x20 357 #define RL_CFG0_PCS 0x40 358 #define RL_CFG0_SCR 0x80 363 #define RL_CFG1_PWRDWN 0x01 364 #define RL_CFG1_SLEEP 0x02 365 #define RL_CFG1_IOMAP 0x04 366 #define RL_CFG1_MEMMAP 0x08 367 #define RL_CFG1_RSVD 0x10 368 #define RL_CFG1_DRVLOAD 0x20 369 #define RL_CFG1_LED0 0x40 370 #define RL_CFG1_FULLDUPLEX 0x40 371 #define RL_CFG1_LED1 0x80 379 #define RL_DUMPSTATS_START 0x00000008 383 #define RL_TXSTART_SWI 0x01 384 #define RL_TXSTART_START 0x40 385 #define RL_TXSTART_HPRIO_START 0x80 390 #define RL_CFG2_BUSFREQ 0x07 391 #define RL_CFG2_BUSWIDTH 0x08 392 #define RL_CFG2_AUXPWRSTS 0x10 394 #define RL_BUSFREQ_33MHZ 0x00 395 #define RL_BUSFREQ_66MHZ 0x01 397 #define RL_BUSWIDTH_32BITS 0x00 398 #define RL_BUSWIDTH_64BITS 0x08 402 #define RL_CPLUSCMD_TXENB 0x0001 403 #define RL_CPLUSCMD_RXENB 0x0002 404 #define RL_CPLUSCMD_PCI_MRW 0x0008 405 #define RL_CPLUSCMD_PCI_DAC 0x0010 406 #define RL_CPLUSCMD_RXCSUM_ENB 0x0020 407 #define RL_CPLUSCMD_VLANSTRIP 0x0040 411 #define RL_EARLYTXTHRESH_CNT 0x003F 417 #define RL_PHYAR_PHYDATA 0x0000FFFF 418 #define RL_PHYAR_PHYREG 0x001F0000 419 #define RL_PHYAR_BUSY 0x80000000 424 #define RL_GMEDIASTAT_FDX 0x01 425 #define RL_GMEDIASTAT_LINK 0x02 426 #define RL_GMEDIASTAT_10MBPS 0x04 427 #define RL_GMEDIASTAT_100MBPS 0x08 428 #define RL_GMEDIASTAT_1000MBPS 0x10 429 #define RL_GMEDIASTAT_RXFLOW 0x20 430 #define RL_GMEDIASTAT_TXFLOW 0x40 431 #define RL_GMEDIASTAT_TBI 0x80 448 #define RL_RX_BUF_SZ RL_RXBUF_64 449 #define RL_RXBUFLEN (1 << ((RL_RX_BUF_SZ >> 11) + 13)) 450 #define RL_TX_LIST_CNT 4 451 #define RL_MIN_FRAMELEN 60 452 #define RL_TXTHRESH(x) ((x) << 11) 453 #define RL_TX_THRESH_INIT 96 454 #define RL_RX_FIFOTHRESH RL_RXFIFO_256BYTES 455 #define RL_RX_MAXDMA RL_RXDMA_UNLIMITED 456 #define RL_TX_MAXDMA RL_TXDMA_2048BYTES 458 #define RL_RXCFG_CONFIG (RL_RX_FIFOTHRESH|RL_RX_MAXDMA|RL_RX_BUF_SZ) 459 #define RL_TXCFG_CONFIG (RL_TXCFG_IFG|RL_TX_MAXDMA) 462 struct rl_chain_data {
465 caddr_t rl_rx_buf_ptr;
466 bus_addr_t rl_rx_buf_pa;
497 #define RL_TDESC_CMD_FRAGLEN 0x0000FFFF 498 #define RL_TDESC_CMD_TCPCSUM 0x00010000 499 #define RL_TDESC_CMD_UDPCSUM 0x00020000 500 #define RL_TDESC_CMD_IPCSUM 0x00040000 501 #define RL_TDESC_CMD_MSSVAL 0x07FF0000 502 #define RL_TDESC_CMD_LGSEND 0x08000000 503 #define RL_TDESC_CMD_EOF 0x10000000 504 #define RL_TDESC_CMD_SOF 0x20000000 505 #define RL_TDESC_CMD_EOR 0x40000000 506 #define RL_TDESC_CMD_OWN 0x80000000 508 #define RL_TDESC_VLANCTL_TAG 0x00020000 509 #define RL_TDESC_VLANCTL_DATA 0x0000FFFF 516 #define RL_TDESC_STAT_COLCNT 0x000F0000 517 #define RL_TDESC_STAT_EXCESSCOL 0x00100000 518 #define RL_TDESC_STAT_LINKFAIL 0x00200000 519 #define RL_TDESC_STAT_OWINCOL 0x00400000 520 #define RL_TDESC_STAT_TXERRSUM 0x00800000 521 #define RL_TDESC_STAT_UNDERRUN 0x02000000 522 #define RL_TDESC_STAT_OWN 0x80000000 528 #define RL_RDESC_CMD_EOR 0x40000000 529 #define RL_RDESC_CMD_OWN 0x80000000 530 #define RL_RDESC_CMD_BUFLEN 0x00001FFF 532 #define RL_RDESC_STAT_OWN 0x80000000 533 #define RL_RDESC_STAT_EOR 0x40000000 534 #define RL_RDESC_STAT_SOF 0x20000000 535 #define RL_RDESC_STAT_EOF 0x10000000 536 #define RL_RDESC_STAT_FRALIGN 0x08000000 537 #define RL_RDESC_STAT_MCAST 0x04000000 538 #define RL_RDESC_STAT_UCAST 0x02000000 539 #define RL_RDESC_STAT_BCAST 0x01000000 540 #define RL_RDESC_STAT_BUFOFLOW 0x00800000 541 #define RL_RDESC_STAT_FIFOOFLOW 0x00400000 542 #define RL_RDESC_STAT_GIANT 0x00200000 543 #define RL_RDESC_STAT_RXERRSUM 0x00100000 544 #define RL_RDESC_STAT_RUNT 0x00080000 545 #define RL_RDESC_STAT_CRCERR 0x00040000 546 #define RL_RDESC_STAT_PROTOID 0x00030000 547 #define RL_RDESC_STAT_IPSUMBAD 0x00008000 548 #define RL_RDESC_STAT_UDPSUMBAD 0x00004000 549 #define RL_RDESC_STAT_TCPSUMBAD 0x00002000 550 #define RL_RDESC_STAT_FRAGLEN 0x00001FFF 551 #define RL_RDESC_STAT_GFRAGLEN 0x00003FFF 552 #define RL_RDESC_STAT_ERRS (RL_RDESC_STAT_GIANT|RL_RDESC_STAT_RUNT| \ 553 RL_RDESC_STAT_CRCERR) 555 #define RL_RDESC_VLANCTL_TAG 0x00010000 557 #define RL_RDESC_VLANCTL_DATA 0x0000FFFF 559 #define RL_PROTOID_NONIP 0x00000000 560 #define RL_PROTOID_TCPIP 0x00010000 561 #define RL_PROTOID_UDPIP 0x00020000 562 #define RL_PROTOID_IP 0x00030000 563 #define RL_TCPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 565 #define RL_UDPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 590 #define RL_RX_DESC_CNT 64 591 #define RL_TX_DESC_CNT_8139 64 592 #define RL_TX_DESC_CNT_8169 1024 594 #define RL_TX_QLEN 64 596 #define RL_NTXDESC_RSVD 4 598 #define RL_RX_LIST_SZ (RL_RX_DESC_CNT * sizeof(struct rl_desc)) 599 #define RL_RING_ALIGN 256 600 #define RL_PKTSZ(x) ((x)) 601 #ifdef __STRICT_ALIGNMENT 602 #define RE_ETHER_ALIGN 2 603 #define RE_RX_DESC_BUFLEN (MCLBYTES - RE_ETHER_ALIGN) 605 #define RE_ETHER_ALIGN 0 606 #define RE_RX_DESC_BUFLEN MCLBYTES 609 #define RL_TX_DESC_CNT(sc) \ 610 ((sc)->rl_ldata.rl_tx_desc_cnt) 611 #define RL_TX_LIST_SZ(sc) \ 612 (RL_TX_DESC_CNT(sc) * sizeof(struct rl_desc)) 613 #define RL_NEXT_TX_DESC(sc, x) \ 614 (((x) + 1) % RL_TX_DESC_CNT(sc)) 615 #define RL_NEXT_RX_DESC(sc, x) \ 616 (((x) + 1) % RL_RX_DESC_CNT) 617 #define RL_NEXT_TXQ(sc, x) \ 618 (((x) + 1) % RL_TX_QLEN) 620 #define RL_TXDESCSYNC(sc, idx, ops) \ 621 bus_dmamap_sync((sc)->sc_dmat, \ 622 (sc)->rl_ldata.rl_tx_list_map, \ 623 sizeof(struct rl_desc) * (idx), \ 624 sizeof(struct rl_desc), \ 626 #define RL_RXDESCSYNC(sc, idx, ops) \ 627 bus_dmamap_sync((sc)->sc_dmat, \ 628 (sc)->rl_ldata.rl_rx_list_map, \ 629 sizeof(struct rl_desc) * (idx), \ 630 sizeof(struct rl_desc), \ 633 #define RL_ADDR_LO(y) ((u_int64_t) (y) & 0xFFFFFFFF) 634 #define RL_ADDR_HI(y) ((u_int64_t) (y) >> 32) 637 #define RL_JUMBO_FRAMELEN 7440 638 #define RL_JUMBO_MTU (RL_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 640 #define MAX_NUM_MULTICAST_ADDRESSES 128 642 #define RL_INC(x) (x = (x + 1) % RL_TX_LIST_CNT) 643 #define RL_CUR_TXADDR(x) ((x->rl_cdata.cur_tx * 4) + RL_TXADDR0) 644 #define RL_CUR_TXSTAT(x) ((x->rl_cdata.cur_tx * 4) + RL_TXSTAT0) 645 #define RL_CUR_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.cur_tx]) 646 #define RL_CUR_TXMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.cur_tx]) 647 #define RL_LAST_TXADDR(x) ((x->rl_cdata.last_tx * 4) + RL_TXADDR0) 648 #define RL_LAST_TXSTAT(x) ((x->rl_cdata.last_tx * 4) + RL_TXSTAT0) 649 #define RL_LAST_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.last_tx]) 650 #define RL_LAST_TXMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.last_tx]) 669 #define RL_MII_STARTDELIM 0x01 670 #define RL_MII_READOP 0x02 671 #define RL_MII_WRITEOP 0x01 672 #define RL_MII_TURNAROUND 0x02 677 #define RL_8139CPLUS 3 680 #define RL_ISCPLUS(x) ((x)->rl_type == RL_8139CPLUS || \ 681 (x)->rl_type == RL_8169) 685 struct mbuf *rxs_mbuf;
686 bus_dmamap_t rxs_dmamap;
690 struct mbuf *txq_mbuf;
691 bus_dmamap_t txq_dmamap;
696 struct rl_list_data {
697 struct rl_txq rl_txq[RL_TX_QLEN];
701 bus_dmamap_t rl_tx_list_map;
706 bus_dma_segment_t rl_tx_listseg;
709 struct rl_rxsoft rl_rxsoft[RL_RX_DESC_CNT];
710 bus_dmamap_t rl_rx_list_map;
713 bus_dma_segment_t rl_rx_listseg;
718 struct device sc_dev;
720 bus_space_handle_t rl_bhandle;
721 bus_space_tag_t rl_btag;
722 bus_dma_tag_t sc_dmat;
723 bus_dma_segment_t sc_rx_seg;
724 bus_dmamap_t sc_rx_dmamap;
725 struct arpcom sc_arpcom;
726 struct mii_data sc_mii;
734 struct rl_chain_data rl_cdata;
735 struct timeout sc_tick_tmo;
738 struct rl_list_data rl_ldata;
739 struct mbuf *rl_head;
740 struct mbuf *rl_tail;
741 u_int32_t rl_rxlenmask;
743 struct timeout timer_handle;
753 #define RL_IP4CSUMTX_MINLEN 28 754 #define RL_IP4CSUMTX_PADLEN (ETHER_HDR_LEN + RL_IP4CSUMTX_MINLEN) 761 #define RL_RX_DMAMEM_SZ (RL_RX_LIST_SZ + RL_IP4CSUMTX_PADLEN) 762 #define RL_TXPADOFF RL_RX_LIST_SZ 763 #define RL_TXPADDADDR(sc) \ 764 ((sc)->rl_ldata.rl_rx_list_map->dm_segs[0].ds_addr + RL_TXPADOFF) 767 #define RL_ATTACHED 0x00000001 768 #define RL_ENABLED 0x00000002 769 #define RL_IS_ENABLED(sc) ((sc)->sc_flags & RL_ENABLED) 774 #define CSR_WRITE_RAW_4(sc, csr, val) \ 775 bus_space_write_raw_region_4(sc->rl_btag, sc->rl_bhandle, csr, val, 4) 776 #define CSR_WRITE_4(sc, csr, val) \ 777 bus_space_write_4(sc->rl_btag, sc->rl_bhandle, csr, val) 778 #define CSR_WRITE_2(sc, csr, val) \ 779 bus_space_write_2(sc->rl_btag, sc->rl_bhandle, csr, val) 780 #define CSR_WRITE_1(sc, csr, val) \ 781 bus_space_write_1(sc->rl_btag, sc->rl_bhandle, csr, val) 783 #define CSR_READ_4(sc, csr) \ 784 bus_space_read_4(sc->rl_btag, sc->rl_bhandle, csr) 785 #define CSR_READ_2(sc, csr) \ 786 bus_space_read_2(sc->rl_btag, sc->rl_bhandle, csr) 787 #define CSR_READ_1(sc, csr) \ 788 bus_space_read_1(sc->rl_btag, sc->rl_bhandle, csr) 790 #define CSR_SETBIT_1(sc, offset, val) \ 791 CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) | (val)) 793 #define CSR_CLRBIT_1(sc, offset, val) \ 794 CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) & ~(val)) 796 #define CSR_SETBIT_2(sc, offset, val) \ 797 CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) | (val)) 799 #define CSR_CLRBIT_2(sc, offset, val) \ 800 CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) & ~(val)) 802 #define CSR_SETBIT_4(sc, offset, val) \ 803 CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) | (val)) 805 #define CSR_CLRBIT_4(sc, offset, val) \ 806 CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) & ~(val)) 808 #define RL_TIMEOUT 1000 815 #define RT_VENDORID 0x10EC 820 #define RT_DEVICEID_8129 0x8129 821 #define RT_DEVICEID_8101E 0x8136 822 #define RT_DEVICEID_8138 0x8138 823 #define RT_DEVICEID_8139 0x8139 824 #define RT_DEVICEID_8169SC 0x8167 825 #define RT_DEVICEID_8168 0x8168 826 #define RT_DEVICEID_8169 0x8169 827 #define RT_DEVICEID_8100 0x8100 832 #define ACCTON_VENDORID 0x1113 837 #define ACCTON_DEVICEID_5030 0x1211 842 #define DELTA_VENDORID 0x1500 847 #define DELTA_DEVICEID_8139 0x1360 852 #define ADDTRON_VENDORID 0x4033 857 #define ADDTRON_DEVICEID_8139 0x1360 860 #define DLINK_VENDORID 0x1186 863 #define DLINK_DEVICEID_8139 0x1300 864 #define DLINK_DEVICEID_8139_2 0x1340 867 #define ABOCOM_DEVICEID_8139 0xab06 875 #define RL_PCI_VENDOR_ID 0x00 876 #define RL_PCI_DEVICE_ID 0x02 877 #define RL_PCI_COMMAND 0x04 878 #define RL_PCI_STATUS 0x06 879 #define RL_PCI_CLASSCODE 0x09 880 #define RL_PCI_LATENCY_TIMER 0x0D 881 #define RL_PCI_HEADER_TYPE 0x0E 882 #define RL_PCI_LOIO 0x10 883 #define RL_PCI_LOMEM 0x14 884 #define RL_PCI_BIOSROM 0x30 885 #define RL_PCI_INTLINE 0x3C 886 #define RL_PCI_INTPIN 0x3D 887 #define RL_PCI_MINGNT 0x3E 888 #define RL_PCI_MINLAT 0x0F 889 #define RL_PCI_RESETOPT 0x48 890 #define RL_PCI_EEPROM_DATA 0x4C 892 #define RL_PCI_CAPID 0x50 893 #define RL_PCI_NEXTPTR 0x51 894 #define RL_PCI_PWRMGMTCAP 0x52 895 #define RL_PCI_PWRMGMTCTRL 0x54 897 #define RL_PSTATE_MASK 0x0003 898 #define RL_PSTATE_D0 0x0000 899 #define RL_PSTATE_D1 0x0002 900 #define RL_PSTATE_D2 0x0002 901 #define RL_PSTATE_D3 0x0003 902 #define RL_PME_EN 0x0010 903 #define RL_PME_STATUS 0x8000 906 extern int rl_attach(
struct rl_softc *);
907 extern int rl_detach(
struct rl_softc *);
908 extern int rl_intr(
void *);
909 extern void rl_setmulti(
struct rl_softc *);
u_int32_t rl_rx_ucasts_lo
volatile u_int32_t rl_vlanctl
volatile u_int32_t rl_cmdstat
u_int32_t rl_tx_multicolls
u_int32_t rl_rx_ucasts_hi
u_int32_t rl_rx_bcasts_hi
u_int32_t rl_rx_bcasts_lo
volatile u_int32_t rl_bufaddr_hi
u_int16_t rl_rx_framealign_errs
u_int16_t rl_rx_underruns
volatile u_int32_t rl_bufaddr_lo