MIPS_CPUComponent.h Source File

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MIPS_CPUComponent.h
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1 #ifndef MIPS_CPUCOMPONENT_H
2 #define MIPS_CPUCOMPONENT_H
3 
4 /*
5  * Copyright (C) 2008-2010 Anders Gavare. All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions are met:
9  *
10  * 1. Redistributions of source code must retain the above copyright
11  * notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  * notice, this list of conditions and the following disclaimer in the
14  * documentation and/or other materials provided with the distribution.
15  * 3. The name of the author may not be used to endorse or promote products
16  * derived from this software without specific prior written permission.
17  *
18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28  * SUCH DAMAGE.
29  */
30 
31 // COMPONENT(mips_cpu)
32 
33 
34 #include "CPUDyntransComponent.h"
35 
36 
37 /***********************************************************************/
38 
39 #define MIPS_INITIAL_PC ((int32_t) 0xbfc00000)
40 #define MIPS_INITIAL_STACK_POINTER ((int32_t) 0xa0008000 - 256)
41 
42 
43 /* FPU control registers: */
44 #define N_MIPS_FCRS 32
45 #define MIPS_FPU_FCIR 0
46 #define MIPS_FPU_FCCR 25
47 #define MIPS_FPU_FCSR 31
48 #define MIPS_FCSR_FCC0_SHIFT 23
49 #define MIPS_FCSR_FCC1_SHIFT 25
50 
51 #define N_MIPS_COPROCS 4
52 
53 #define N_MIPS_GPRS 32 /* General purpose registers */
54 #define N_MIPS_FPRS 32 /* Floating point registers */
55 
56 /*
57  * These should all be 2 characters wide:
58  *
59  * NOTE: For the newer ABIs (n32 and 64-bit ABIs), registers 8..11 are used
60  * to pass arguments and are then called "a4".."a7".
61  */
62 #define MIPS_OLDABI_REGISTER_NAMES { \
63  "zr", "at", "v0", "v1", "a0", "a1", "a2", "a3", \
64  "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", \
65  "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \
66  "t8", "t9", "k0", "k1", "gp", "sp", "fp", "ra" }
67 #define MIPS_REGISTER_NAMES { \
68  "zr", "at", "v0", "v1", "a0", "a1", "a2", "a3", \
69  "a4", "a5", "a6", "a7", "t4", "t5", "t6", "t7", \
70  "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \
71  "t8", "t9", "k0", "k1", "gp", "sp", "fp", "ra" }
72 
73 #define MIPS_GPR_ZERO 0 /* zero */
74 #define MIPS_GPR_AT 1 /* at */
75 #define MIPS_GPR_V0 2 /* v0 */
76 #define MIPS_GPR_V1 3 /* v1 */
77 #define MIPS_GPR_A0 4 /* a0 */
78 #define MIPS_GPR_A1 5 /* a1 */
79 #define MIPS_GPR_A2 6 /* a2 */
80 #define MIPS_GPR_A3 7 /* a3 */
81 #define MIPS_GPR_T0 8 /* t0 */
82 #define MIPS_GPR_T1 9 /* t1 */
83 #define MIPS_GPR_T2 10 /* t2 */
84 #define MIPS_GPR_T3 11 /* t3 */
85 #define MIPS_GPR_T4 12 /* t4 */
86 #define MIPS_GPR_T5 13 /* t5 */
87 #define MIPS_GPR_T6 14 /* t6 */
88 #define MIPS_GPR_T7 15 /* t7 */
89 #define MIPS_GPR_S0 16 /* s0 */
90 #define MIPS_GPR_S1 17 /* s1 */
91 #define MIPS_GPR_S2 18 /* s2 */
92 #define MIPS_GPR_S3 19 /* s3 */
93 #define MIPS_GPR_S4 20 /* s4 */
94 #define MIPS_GPR_S5 21 /* s5 */
95 #define MIPS_GPR_S6 22 /* s6 */
96 #define MIPS_GPR_S7 23 /* s7 */
97 #define MIPS_GPR_T8 24 /* t8 */
98 #define MIPS_GPR_T9 25 /* t9 */
99 #define MIPS_GPR_K0 26 /* k0 */
100 #define MIPS_GPR_K1 27 /* k1 */
101 #define MIPS_GPR_GP 28 /* gp */
102 #define MIPS_GPR_SP 29 /* sp */
103 #define MIPS_GPR_FP 30 /* fp */
104 #define MIPS_GPR_RA 31 /* ra */
105 
106 #define N_HI6 64
107 #define N_SPECIAL 64
108 #define N_REGIMM 32
109 
110 
111 /***********************************************************************/
112 
113 
114 /*
115  * CPU type definitions: See mips_cpu_types.h.
116  */
117 
119  const char * name;
120  int rev;
121  int sub;
122  int flags;
123  int exc_model; /* EXC3K or EXC4K */
124  int mmu_model; /* MMU3K or MMU4K */
125  int isa_level; /* 1, 2, 3, 4, 5, 32, 64 */
126  int isa_revision; /* 1 or 2 (for MIPS32/64) */
127  int nr_of_tlb_entries; /* 32, 48, 64, ... */
128  int instrs_per_cycle; /* simplified, 1, 2, or 4 */
129  int picache;
131  int piways;
132  int pdcache;
134  int pdways;
135  int scache;
137  int sways;
138 };
139 
140 
141 /***********************************************************************/
142 
143 
144 /**
145  * \brief A Component representing a MIPS processor.
146  */
148  : public CPUDyntransComponent
149 {
150 public:
151  /**
152  * \brief Constructs a MIPS_CPUComponent.
153  */
155 
156  /**
157  * \brief Creates a MIPS_CPUComponent.
158  */
159  static refcount_ptr<Component> Create(const ComponentCreateArgs& args);
160 
161  static string GetAttribute(const string& attributeName);
162 
163  virtual void ResetState();
164 
165  virtual bool PreRunCheckForComponent(GXemul* gxemul);
166 
167  virtual size_t DisassembleInstruction(uint64_t vaddr, size_t maxlen,
168  unsigned char *instruction, vector<string>& result);
169 
170 
171  /********************************************************************/
172 
173  static void RunUnitTests(int& nSucceeded, int& nFailures);
174 
175 protected:
176  virtual bool CheckVariableWrite(StateVariable& var, const string& oldValue);
177 
178  virtual bool VirtualToPhysical(uint64_t vaddr, uint64_t& paddr,
179  bool& writable);
180 
181  virtual string VirtualAddressAsString(uint64_t vaddr)
182  {
183  stringstream ss;
184  ss.flags(std::ios::hex | std::ios::showbase | std::ios::right);
185  if (Is32Bit())
186  ss << (uint32_t)vaddr;
187  else
188  ss << vaddr;
189  return ss.str();
190  }
191 
192  virtual uint64_t PCtoInstructionAddress(uint64_t pc);
193 
194  virtual int FunctionTraceArgumentCount();
195  virtual int64_t FunctionTraceArgument(int n);
196  virtual bool FunctionTraceReturnImpl(int64_t& retval);
197 
198  virtual int GetDyntransICshift() const;
200 
201  virtual void ShowRegisters(GXemul* gxemul, const vector<string>& arguments) const;
202 
203 private:
204  size_t DisassembleInstructionMIPS16(uint64_t vaddr,
205  unsigned char *instruction, vector<string>& result);
206 
207  bool Is32Bit() const;
208 
209 private:
210  template<int op, bool samepage, bool singlestep> static void instr_b(CPUDyntransComponent* cpubase, DyntransIC* ic);
211  template<bool link, bool singlestep> static void instr_j(CPUDyntransComponent* cpubase, DyntransIC* ic);
212  template<bool link, bool singlestep> static void instr_jr(CPUDyntransComponent* cpubase, DyntransIC* ic);
213 
214  DECLARE_DYNTRANS_INSTR(multu);
217 
218  template<bool store, typename addressType, typename T, bool signedLoad> static void instr_loadstore(CPUDyntransComponent* cpubase, DyntransIC* ic);
219 
220  void Translate(uint32_t iword, struct DyntransIC* ic);
221  DECLARE_DYNTRANS_INSTR(ToBeTranslated);
222  DECLARE_DYNTRANS_INSTR(ToBeTranslated_MIPS16);
223 
224 private:
225  /*
226  * State:
227  */
228  string m_mips_type; // E.g. "R4400"
229  string m_abi; // "o32", "n32", or "n64"
230  uint64_t m_gpr[N_MIPS_GPRS];
231  uint64_t m_hi;
232  uint64_t m_lo;
233 
234  uint64_t m_scratch; // for loads into the zero register
235 
236  /*
237  * Cached or volatile other state:
238  */
239  mips_cpu_type_def m_type; // based on m_mips_type
240 };
241 
242 
243 #endif // MIPS_CPUCOMPONENT_H
244 
struct arm_instr_call * ic
A dyntrans instruction call.
The main emulator class.
Definition: GXemul.h:54
A Component representing a MIPS processor.
A base-class for processors Component implementations that use dynamic translation.
virtual void(*)(CPUDyntransComponent *, DyntransIC *) GetDyntransToBeTranslated()
StateVariables make up the persistent state of Component objects.
Definition: StateVariable.h:67
#define DECLARE_DYNTRANS_INSTR(name)
virtual string VirtualAddressAsString(uint64_t vaddr)
Format a virtual address as a displayable string.
#define N_MIPS_GPRS

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