vr_rtcreg.h Source File

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vr_rtcreg.h
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1 /* $NetBSD: rtcreg.h,v 1.8 2002/02/10 14:36:52 sato Exp $ */
2 
3 #ifndef VR_RTCREG_H
4 #define VR_RTCREG_H
5 
6 /*-
7  * Copyright (c) 1999 Shin Takemura. All rights reserved.
8  * Copyright (c) 1999-2001 SATO Kazumi. All rights reserved.
9  * Copyright (c) 1999 PocketBSD Project. All rights reserved.
10  *
11  * Redistribution and use in source and binary forms, with or without
12  * modification, are permitted provided that the following conditions
13  * are met:
14  * 1. Redistributions of source code must retain the above copyright
15  * notice, this list of conditions and the following disclaimer.
16  * 2. Redistributions in binary form must reproduce the above copyright
17  * notice, this list of conditions and the following disclaimer in the
18  * documentation and/or other materials provided with the distribution.
19  * 3. All advertising materials mentioning features or use of this software
20  * must display the following acknowledgement:
21  * This product includes software developed by the PocketBSD project
22  * and its contributors.
23  * 4. Neither the name of the project nor the names of its contributors
24  * may be used to endorse or promote products derived from this software
25  * without specific prior written permission.
26  *
27  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
28  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
29  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
30  * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
31  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
35  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
36  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
37  * SUCH DAMAGE.
38  *
39  */
40 
41 #define SECMIN ((unsigned)60) /* seconds per minute */
42 #define SECHOUR ((unsigned)(60*SECMIN)) /* seconds per hour */
43 
44 #define SEC2MIN ((unsigned)60/2) /* 2seconds per minute */
45 #define SEC2HOUR ((unsigned)(60*SECMIN)/2) /* 2seconds per hour */
46 #define SEC2DAY ((unsigned)(24*SECHOUR)/2) /* 2seconds per day */
47 #define SEC2YR ((unsigned)(365*SECDAY)/2) /* 2seconds per common year */
48 
49 #define YRREF 1999
50 #define MREF 1
51 #define DREF 1
52 
53 #ifndef YBASE
54 #define YBASE 1900
55 #endif
56 
57 #define EPOCHOFF 0 /* epoch offset */
58 #ifndef EPOCHYEAR
59 #define EPOCHYEAR 1850 /* XXX */ /* WINCE epoch year */
60 #endif
61 #define EPOCHMONTH 1 /* WINCE epoch month of year */
62 #define EPOCHDATE 1 /* WINCE epoch date of month */
63 
64 #define LEAPYEAR4(year) ((((year) % 4) == 0 && ((year) % 100) != 0) || ((year%400)) == 0)
65 #define LEAPYEAR2(year) (((year) % 4) == 0)
66 
67 /*
68  * RTC (Real Time Clock Unit) Registers definitions.
69  * start 0x0B0000C0 (Vr4102-4121)
70  * start 0x0F000100 (Vr4122-4131)
71  * start 0x0B0000C0 (Vr4181)
72  */
73 #define RTC_NO_REG_W 0xffffffff
74 
75 #define ETIME_L_REG_W 0x000 /* Elapsed Time L */
76 #define ETIME_M_REG_W 0x002 /* Elapsed Time M */
77 #define ETIME_H_REG_W 0x004 /* Elapsed Time H */
78 
79 #define ETIME_L_HZ 0x8000 /* 1 HZ */
80 
81 
82 #define ECMP_L_REG_W 0x008 /* Elapsed Compare L */
83 #define ECMP_M_REG_W 0x00a /* Elapsed Compare M */
84 #define ECMP_H_REG_W 0x00c /* Elapsed Compare H */
85 
86 
87 #define RTCL1_L_REG_W 0x010 /* RTC Long 1 L */
88 #define RTCL1_H_REG_W 0x012 /* RTC Long 1 H */
89 
90 #define RTCL1_L_HZ 0x8000 /* 1 HZ */
91 
92 
93 #define RTCL1_CNT_L_REG_W 0x014 /* RTC Long 1 Count L */
94 #define RTCL1_CNT_H_REG_W 0x016 /* RTC Long 1 Count H */
95 
96 
97 #define RTCL2_L_REG_W 0x018 /* RTC Long 2 L */
98 #define RTCL2_H_REG_W 0x01a /* RTC Long 2 H */
99 
100 #define RTCL2_L_HZ 0x8000 /* 1 HZ */
101 
102 
103 #define RTCL2_CNT_L_REG_W 0x01c /* RTC Long 2 Count L */
104 #define RTCL2_CNT_H_REG_W 0x01e /* RTC Long 2 Count H */
105 
106 
107 #define VR4102_TCLK_L_REG_W 0x100 /* TCLK L */
108 #define VR4102_TCLK_H_REG_W 0x102 /* TCLK H */
109 #define VR4122_TCLK_L_REG_W 0x020 /* TCLK L */
110 #define VR4122_TCLK_H_REG_W 0x022 /* TCLK H */
111 #if defined SINGLE_VRIP_BASE
112 #if defined VRGROUP_4102_4121
113 #define TCLK_L_REG_W VR4102_TCLK_L_REG_W /* TCLK L */
114 #define TCLK_H_REG_W VR4102_TCLK_H_REG_W /* TCLK H */
115 #endif /* VRGROUP_4102_4121 */
116 #if defined VRGROUP_4122_4131
117 #define TCLK_L_REG_W VR4122_TCLK_L_REG_W /* TCLK L */
118 #define TCLK_H_REG_W VR4122_TCLK_H_REG_W /* TCLK H */
119 #endif /* VRGROUP_4122_4131 */
120 #if defined VRGROUP_4181
121 #define TCLK_L_REG_W RTC_NO_REG_W
122 #define TCLK_H_REG_W RTC_NO_REG_W
123 #endif /* VRGROUP_4181 */
124 #endif /* defined SINGLE_VRIP_BASE */
125 
126 
127 #define VR4102_TCLK_CNT_L_REG_W 0x104 /* TCLK Count L */
128 #define VR4102_TCLK_CNT_H_REG_W 0x106 /* TCLK Count H */
129 #define VR4122_TCLK_CNT_L_REG_W 0x024 /* TCLK Count L */
130 #define VR4122_TCLK_CNT_H_REG_W 0x026 /* TCLK Count H */
131 #if defined SINGLE_VRIP_BASE
132 #if defined VRGROUP_4102_4121
133 #define TCLK_CNT_L_REG_W VR4102_TCLK_CNT_L_REG_W /* TCLK Count L */
134 #define TCLK_CNT_H_REG_W VR4102_TCLK_CNT_L_REG_W /* TCLK Count H */
135 #endif /* VRGROUP_4102_4121 */
136 #if defined VRGROUP_4122_4131
137 #define TCLK_CNT_L_REG_W VR4122_TCLK_CNT_L_REG_W /* TCLK Count L */
138 #define TCLK_CNT_H_REG_W VR4122_TCLK_CNT_H_REG_W /* TCLK Count H */
139 #endif /* VRGROUP_4122_4131 */
140 #if defined VRGROUP_4181
141 #define TCLK_CNT_L_REG_W RTC_NO_REG_W
142 #define TCLK_CNT_H_REG_W RTC_NO_REG_W
143 #endif /* VRGROUP_4181 */
144 #endif /* defined SINGLE_VRIP_BASE */
145 
146 
147 #define VR4102_RTCINT_REG_W 0x11e /* RTC intr reg. */
148 #define VR4122_RTCINT_REG_W 0x03e /* RTC intr reg. */
149 #define VR4181_RTCINT_REG_W 0x11e /* RTC intr reg. */
150 #if defined SINGLE_VRIP_BASE
151 #if defined VRGROUP_4102_4121
152 #define RTCINT_REG_W VR4102_RTCINT_REG_W /* RTC intr reg. */
153 #endif /* VRGROUP_4102_4121 */
154 #if defined VRGROUP_4122_4131
155 #define RTCINT_REG_W VR4122_RTCINT_REG_W /* RTC intr reg. */
156 #endif /* VRGROUP_4122 */
157 #if defined VRGROUP_4181
158 #define RTCINT_REG_W VR4181_RTCINT_REG_W /* RTC intr reg. */
159 #endif /* VRGROUP_4181 */
160 #endif /* defined SINGLE_VRIP_BASE */
161 
162 #define RTCINT_TCLOCK (1<<3) /* TClock */
163 #define RTCINT_RTCLONG2 (1<<2) /* RTC Long 2 */
164 #define RTCINT_RTCLONG1 (1<<1) /* RTC Long 1 */
165 #define RTCINT_ELAPSED (1) /* Elapsed time */
166 #define RTCINT_ALL (RTCINT_TCLOCK|RTCINT_RTCLONG2|RTCINT_RTCLONG1|RTCINT_ELAPSED)
167 
168 #endif /* VR_RTCREG_H */

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