pcireg.h File Reference

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pcireg.h File Reference

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Classes

struct  pci_vpd_smallres
 
struct  pci_vpd_largeres
 
struct  pci_vpd
 

Macros

#define __attribute__(x)   /* */
 
#define __noreturn__   /* */
 
#define PCI_ID_REG   0x00
 
#define PCI_VENDOR_SHIFT   0
 
#define PCI_VENDOR_MASK   0xffff
 
#define PCI_VENDOR(id)   (((id) >> PCI_VENDOR_SHIFT) & PCI_VENDOR_MASK)
 
#define PCI_PRODUCT_SHIFT   16
 
#define PCI_PRODUCT_MASK   0xffff
 
#define PCI_PRODUCT(id)   (((id) >> PCI_PRODUCT_SHIFT) & PCI_PRODUCT_MASK)
 
#define PCI_ID_CODE(vid, pid)
 
#define PCI_COMMAND_STATUS_REG   0x04
 
#define PCI_COMMAND_SHIFT   0
 
#define PCI_COMMAND_MASK   0xffff
 
#define PCI_STATUS_SHIFT   16
 
#define PCI_STATUS_MASK   0xffff
 
#define PCI_COMMAND_STATUS_CODE(cmd, stat)
 
#define PCI_COMMAND_IO_ENABLE   0x00000001
 
#define PCI_COMMAND_MEM_ENABLE   0x00000002
 
#define PCI_COMMAND_MASTER_ENABLE   0x00000004
 
#define PCI_COMMAND_SPECIAL_ENABLE   0x00000008
 
#define PCI_COMMAND_INVALIDATE_ENABLE   0x00000010
 
#define PCI_COMMAND_PALETTE_ENABLE   0x00000020
 
#define PCI_COMMAND_PARITY_ENABLE   0x00000040
 
#define PCI_COMMAND_STEPPING_ENABLE   0x00000080
 
#define PCI_COMMAND_SERR_ENABLE   0x00000100
 
#define PCI_COMMAND_BACKTOBACK_ENABLE   0x00000200
 
#define PCI_STATUS_CAPLIST_SUPPORT   0x00100000
 
#define PCI_STATUS_66MHZ_SUPPORT   0x00200000
 
#define PCI_STATUS_UDF_SUPPORT   0x00400000
 
#define PCI_STATUS_BACKTOBACK_SUPPORT   0x00800000
 
#define PCI_STATUS_PARITY_ERROR   0x01000000
 
#define PCI_STATUS_DEVSEL_FAST   0x00000000
 
#define PCI_STATUS_DEVSEL_MEDIUM   0x02000000
 
#define PCI_STATUS_DEVSEL_SLOW   0x04000000
 
#define PCI_STATUS_DEVSEL_MASK   0x06000000
 
#define PCI_STATUS_TARGET_TARGET_ABORT   0x08000000
 
#define PCI_STATUS_MASTER_TARGET_ABORT   0x10000000
 
#define PCI_STATUS_MASTER_ABORT   0x20000000
 
#define PCI_STATUS_SPECIAL_ERROR   0x40000000
 
#define PCI_STATUS_PARITY_DETECT   0x80000000
 
#define PCI_CLASS_REG   0x08
 
#define PCI_CLASS_SHIFT   24
 
#define PCI_CLASS_MASK   0xff
 
#define PCI_CLASS(cr)   (((cr) >> PCI_CLASS_SHIFT) & PCI_CLASS_MASK)
 
#define PCI_SUBCLASS_SHIFT   16
 
#define PCI_SUBCLASS_MASK   0xff
 
#define PCI_SUBCLASS(cr)   (((cr) >> PCI_SUBCLASS_SHIFT) & PCI_SUBCLASS_MASK)
 
#define PCI_INTERFACE_SHIFT   8
 
#define PCI_INTERFACE_MASK   0xff
 
#define PCI_INTERFACE(cr)   (((cr) >> PCI_INTERFACE_SHIFT) & PCI_INTERFACE_MASK)
 
#define PCI_REVISION_SHIFT   0
 
#define PCI_REVISION_MASK   0xff
 
#define PCI_REVISION(cr)   (((cr) >> PCI_REVISION_SHIFT) & PCI_REVISION_MASK)
 
#define PCI_CLASS_CODE(mainclass, subclass, interface)
 
#define PCI_CLASS_PREHISTORIC   0x00
 
#define PCI_CLASS_MASS_STORAGE   0x01
 
#define PCI_CLASS_NETWORK   0x02
 
#define PCI_CLASS_DISPLAY   0x03
 
#define PCI_CLASS_MULTIMEDIA   0x04
 
#define PCI_CLASS_MEMORY   0x05
 
#define PCI_CLASS_BRIDGE   0x06
 
#define PCI_CLASS_COMMUNICATIONS   0x07
 
#define PCI_CLASS_SYSTEM   0x08
 
#define PCI_CLASS_INPUT   0x09
 
#define PCI_CLASS_DOCK   0x0a
 
#define PCI_CLASS_PROCESSOR   0x0b
 
#define PCI_CLASS_SERIALBUS   0x0c
 
#define PCI_CLASS_WIRELESS   0x0d
 
#define PCI_CLASS_I2O   0x0e
 
#define PCI_CLASS_SATCOM   0x0f
 
#define PCI_CLASS_CRYPTO   0x10
 
#define PCI_CLASS_DASP   0x11
 
#define PCI_CLASS_UNDEFINED   0xff
 
#define PCI_SUBCLASS_PREHISTORIC_MISC   0x00
 
#define PCI_SUBCLASS_PREHISTORIC_VGA   0x01
 
#define PCI_SUBCLASS_MASS_STORAGE_SCSI   0x00
 
#define PCI_SUBCLASS_MASS_STORAGE_IDE   0x01
 
#define PCI_SUBCLASS_MASS_STORAGE_FLOPPY   0x02
 
#define PCI_SUBCLASS_MASS_STORAGE_IPI   0x03
 
#define PCI_SUBCLASS_MASS_STORAGE_RAID   0x04
 
#define PCI_SUBCLASS_MASS_STORAGE_ATA   0x05
 
#define PCI_SUBCLASS_MASS_STORAGE_MISC   0x80
 
#define PCI_SUBCLASS_NETWORK_ETHERNET   0x00
 
#define PCI_SUBCLASS_NETWORK_TOKENRING   0x01
 
#define PCI_SUBCLASS_NETWORK_FDDI   0x02
 
#define PCI_SUBCLASS_NETWORK_ATM   0x03
 
#define PCI_SUBCLASS_NETWORK_ISDN   0x04
 
#define PCI_SUBCLASS_NETWORK_WORLDFIP   0x05
 
#define PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP   0x06
 
#define PCI_SUBCLASS_NETWORK_MISC   0x80
 
#define PCI_SUBCLASS_DISPLAY_VGA   0x00
 
#define PCI_SUBCLASS_DISPLAY_XGA   0x01
 
#define PCI_SUBCLASS_DISPLAY_3D   0x02
 
#define PCI_SUBCLASS_DISPLAY_MISC   0x80
 
#define PCI_SUBCLASS_MULTIMEDIA_VIDEO   0x00
 
#define PCI_SUBCLASS_MULTIMEDIA_AUDIO   0x01
 
#define PCI_SUBCLASS_MULTIMEDIA_TELEPHONY   0x02
 
#define PCI_SUBCLASS_MULTIMEDIA_MISC   0x80
 
#define PCI_SUBCLASS_MEMORY_RAM   0x00
 
#define PCI_SUBCLASS_MEMORY_FLASH   0x01
 
#define PCI_SUBCLASS_MEMORY_MISC   0x80
 
#define PCI_SUBCLASS_BRIDGE_HOST   0x00
 
#define PCI_SUBCLASS_BRIDGE_ISA   0x01
 
#define PCI_SUBCLASS_BRIDGE_EISA   0x02
 
#define PCI_SUBCLASS_BRIDGE_MC   0x03 /* XXX _MCA? */
 
#define PCI_SUBCLASS_BRIDGE_PCI   0x04
 
#define PCI_SUBCLASS_BRIDGE_PCMCIA   0x05
 
#define PCI_SUBCLASS_BRIDGE_NUBUS   0x06
 
#define PCI_SUBCLASS_BRIDGE_CARDBUS   0x07
 
#define PCI_SUBCLASS_BRIDGE_RACEWAY   0x08
 
#define PCI_SUBCLASS_BRIDGE_STPCI   0x09
 
#define PCI_SUBCLASS_BRIDGE_INFINIBAND   0x0a
 
#define PCI_SUBCLASS_BRIDGE_MISC   0x80
 
#define PCI_SUBCLASS_COMMUNICATIONS_SERIAL   0x00
 
#define PCI_SUBCLASS_COMMUNICATIONS_PARALLEL   0x01
 
#define PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL   0x02
 
#define PCI_SUBCLASS_COMMUNICATIONS_MODEM   0x03
 
#define PCI_SUBCLASS_COMMUNICATIONS_GPIB   0x04
 
#define PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD   0x05
 
#define PCI_SUBCLASS_COMMUNICATIONS_MISC   0x80
 
#define PCI_SUBCLASS_SYSTEM_PIC   0x00
 
#define PCI_SUBCLASS_SYSTEM_DMA   0x01
 
#define PCI_SUBCLASS_SYSTEM_TIMER   0x02
 
#define PCI_SUBCLASS_SYSTEM_RTC   0x03
 
#define PCI_SUBCLASS_SYSTEM_PCIHOTPLUG   0x04
 
#define PCI_SUBCLASS_SYSTEM_MISC   0x80
 
#define PCI_SUBCLASS_INPUT_KEYBOARD   0x00
 
#define PCI_SUBCLASS_INPUT_DIGITIZER   0x01
 
#define PCI_SUBCLASS_INPUT_MOUSE   0x02
 
#define PCI_SUBCLASS_INPUT_SCANNER   0x03
 
#define PCI_SUBCLASS_INPUT_GAMEPORT   0x04
 
#define PCI_SUBCLASS_INPUT_MISC   0x80
 
#define PCI_SUBCLASS_DOCK_GENERIC   0x00
 
#define PCI_SUBCLASS_DOCK_MISC   0x80
 
#define PCI_SUBCLASS_PROCESSOR_386   0x00
 
#define PCI_SUBCLASS_PROCESSOR_486   0x01
 
#define PCI_SUBCLASS_PROCESSOR_PENTIUM   0x02
 
#define PCI_SUBCLASS_PROCESSOR_ALPHA   0x10
 
#define PCI_SUBCLASS_PROCESSOR_POWERPC   0x20
 
#define PCI_SUBCLASS_PROCESSOR_MIPS   0x30
 
#define PCI_SUBCLASS_PROCESSOR_COPROC   0x40
 
#define PCI_SUBCLASS_SERIALBUS_FIREWIRE   0x00
 
#define PCI_SUBCLASS_SERIALBUS_ACCESS   0x01
 
#define PCI_SUBCLASS_SERIALBUS_SSA   0x02
 
#define PCI_SUBCLASS_SERIALBUS_USB   0x03
 
#define PCI_SUBCLASS_SERIALBUS_FIBER   0x04 /* XXX _FIBRECHANNEL */
 
#define PCI_SUBCLASS_SERIALBUS_SMBUS   0x05
 
#define PCI_SUBCLASS_SERIALBUS_INFINIBAND   0x06
 
#define PCI_SUBCLASS_SERIALBUS_IPMI   0x07
 
#define PCI_SUBCLASS_SERIALBUS_SERCOS   0x08
 
#define PCI_SUBCLASS_SERIALBUS_CANBUS   0x09
 
#define PCI_SUBCLASS_WIRELESS_IRDA   0x00
 
#define PCI_SUBCLASS_WIRELESS_CONSUMERIR   0x01
 
#define PCI_SUBCLASS_WIRELESS_RF   0x10
 
#define PCI_SUBCLASS_WIRELESS_BLUETOOTH   0x11
 
#define PCI_SUBCLASS_WIRELESS_BROADBAND   0x12
 
#define PCI_SUBCLASS_WIRELESS_MISC   0x80
 
#define PCI_SUBCLASS_I2O_STANDARD   0x00
 
#define PCI_SUBCLASS_SATCOM_TV   0x01
 
#define PCI_SUBCLASS_SATCOM_AUDIO   0x02
 
#define PCI_SUBCLASS_SATCOM_VOICE   0x03
 
#define PCI_SUBCLASS_SATCOM_DATA   0x04
 
#define PCI_SUBCLASS_CRYPTO_NETCOMP   0x00
 
#define PCI_SUBCLASS_CRYPTO_ENTERTAINMENT   0x10
 
#define PCI_SUBCLASS_CRYPTO_MISC   0x80
 
#define PCI_SUBCLASS_DASP_DPIO   0x00
 
#define PCI_SUBCLASS_DASP_TIMEFREQ   0x01
 
#define PCI_SUBCLASS_DASP_SYNC   0x10
 
#define PCI_SUBCLASS_DASP_MGMT   0x20
 
#define PCI_SUBCLASS_DASP_MISC   0x80
 
#define PCI_BHLC_REG   0x0c
 
#define PCI_BIST_SHIFT   24
 
#define PCI_BIST_MASK   0xff
 
#define PCI_BIST(bhlcr)   (((bhlcr) >> PCI_BIST_SHIFT) & PCI_BIST_MASK)
 
#define PCI_HDRTYPE_SHIFT   16
 
#define PCI_HDRTYPE_MASK   0xff
 
#define PCI_HDRTYPE(bhlcr)   (((bhlcr) >> PCI_HDRTYPE_SHIFT) & PCI_HDRTYPE_MASK)
 
#define PCI_HDRTYPE_TYPE(bhlcr)   (PCI_HDRTYPE(bhlcr) & 0x7f)
 
#define PCI_HDRTYPE_MULTIFN(bhlcr)   ((PCI_HDRTYPE(bhlcr) & 0x80) != 0)
 
#define PCI_LATTIMER_SHIFT   8
 
#define PCI_LATTIMER_MASK   0xff
 
#define PCI_LATTIMER(bhlcr)   (((bhlcr) >> PCI_LATTIMER_SHIFT) & PCI_LATTIMER_MASK)
 
#define PCI_CACHELINE_SHIFT   0
 
#define PCI_CACHELINE_MASK   0xff
 
#define PCI_CACHELINE(bhlcr)   (((bhlcr) >> PCI_CACHELINE_SHIFT) & PCI_CACHELINE_MASK)
 
#define PCI_BHLC_CODE(bist, type, multi, latency, cacheline)
 
#define PCI_MAPREG_START   0x10
 
#define PCI_MAPREG_END   0x28
 
#define PCI_MAPREG_ROM   0x30
 
#define PCI_MAPREG_PPB_END   0x18
 
#define PCI_MAPREG_PCB_END   0x14
 
#define PCI_MAPREG_TYPE(mr)   ((mr) & PCI_MAPREG_TYPE_MASK)
 
#define PCI_MAPREG_TYPE_MASK   0x00000001
 
#define PCI_MAPREG_TYPE_MEM   0x00000000
 
#define PCI_MAPREG_TYPE_IO   0x00000001
 
#define PCI_MAPREG_ROM_ENABLE   0x00000001
 
#define PCI_MAPREG_MEM_TYPE(mr)   ((mr) & PCI_MAPREG_MEM_TYPE_MASK)
 
#define PCI_MAPREG_MEM_TYPE_MASK   0x00000006
 
#define PCI_MAPREG_MEM_TYPE_32BIT   0x00000000
 
#define PCI_MAPREG_MEM_TYPE_32BIT_1M   0x00000002
 
#define PCI_MAPREG_MEM_TYPE_64BIT   0x00000004
 
#define PCI_MAPREG_MEM_PREFETCHABLE(mr)   (((mr) & PCI_MAPREG_MEM_PREFETCHABLE_MASK) != 0)
 
#define PCI_MAPREG_MEM_PREFETCHABLE_MASK   0x00000008
 
#define PCI_MAPREG_MEM_ADDR(mr)   ((mr) & PCI_MAPREG_MEM_ADDR_MASK)
 
#define PCI_MAPREG_MEM_SIZE(mr)   (PCI_MAPREG_MEM_ADDR(mr) & -PCI_MAPREG_MEM_ADDR(mr))
 
#define PCI_MAPREG_MEM_ADDR_MASK   0xfffffff0
 
#define PCI_MAPREG_MEM64_ADDR(mr)   ((mr) & PCI_MAPREG_MEM64_ADDR_MASK)
 
#define PCI_MAPREG_MEM64_SIZE(mr)   (PCI_MAPREG_MEM64_ADDR(mr) & -PCI_MAPREG_MEM64_ADDR(mr))
 
#define PCI_MAPREG_MEM64_ADDR_MASK   0xfffffffffffffff0ULL
 
#define PCI_MAPREG_IO_ADDR(mr)   ((mr) & PCI_MAPREG_IO_ADDR_MASK)
 
#define PCI_MAPREG_IO_SIZE(mr)   (PCI_MAPREG_IO_ADDR(mr) & -PCI_MAPREG_IO_ADDR(mr))
 
#define PCI_MAPREG_IO_ADDR_MASK   0xfffffffc
 
#define PCI_MAPREG_SIZE_TO_MASK(size)   (-(size))
 
#define PCI_MAPREG_NUM(offset)   (((unsigned)(offset)-PCI_MAPREG_START)/4)
 
#define PCI_CARDBUS_CIS_REG   0x28
 
#define PCI_SUBSYS_ID_REG   0x2c
 
#define PCI_CAPLISTPTR_REG   0x34 /* header type 0 */
 
#define PCI_CARDBUS_CAPLISTPTR_REG   0x14 /* header type 2 */
 
#define PCI_CAPLIST_PTR(cpr)   ((cpr) & 0xff)
 
#define PCI_CAPLIST_NEXT(cr)   (((cr) >> 8) & 0xff)
 
#define PCI_CAPLIST_CAP(cr)   ((cr) & 0xff)
 
#define PCI_CAP_RESERVED0   0x00
 
#define PCI_CAP_PWRMGMT   0x01
 
#define PCI_CAP_AGP   0x02
 
#define PCI_CAP_VPD   0x03
 
#define PCI_CAP_SLOTID   0x04
 
#define PCI_CAP_MBI   0x05
 
#define PCI_CAP_CPCI_HOTSWAP   0x06
 
#define PCI_CAP_PCIX   0x07
 
#define PCI_CAP_LDT   0x08
 
#define PCI_CAP_VENDSPEC   0x09
 
#define PCI_CAP_DEBUGPORT   0x0a
 
#define PCI_CAP_CPCI_RSRCCTL   0x0b
 
#define PCI_CAP_HOTPLUG   0x0c
 
#define PCI_PMCSR_STATE_MASK   0x03
 
#define PCI_PMCSR_STATE_D0   0x00
 
#define PCI_PMCSR_STATE_D1   0x01
 
#define PCI_PMCSR_STATE_D2   0x02
 
#define PCI_PMCSR_STATE_D3   0x03
 
#define PCI_INTERRUPT_REG   0x3c
 
#define PCI_MAX_LAT_SHIFT   24
 
#define PCI_MAX_LAT_MASK   0xff
 
#define PCI_MAX_LAT(icr)   (((icr) >> PCI_MAX_LAT_SHIFT) & PCI_MAX_LAT_MASK)
 
#define PCI_MIN_GNT_SHIFT   16
 
#define PCI_MIN_GNT_MASK   0xff
 
#define PCI_MIN_GNT(icr)   (((icr) >> PCI_MIN_GNT_SHIFT) & PCI_MIN_GNT_MASK)
 
#define PCI_INTERRUPT_GRANT_SHIFT   24
 
#define PCI_INTERRUPT_GRANT_MASK   0xff
 
#define PCI_INTERRUPT_GRANT(icr)   (((icr) >> PCI_INTERRUPT_GRANT_SHIFT) & PCI_INTERRUPT_GRANT_MASK)
 
#define PCI_INTERRUPT_LATENCY_SHIFT   16
 
#define PCI_INTERRUPT_LATENCY_MASK   0xff
 
#define PCI_INTERRUPT_LATENCY(icr)   (((icr) >> PCI_INTERRUPT_LATENCY_SHIFT) & PCI_INTERRUPT_LATENCY_MASK)
 
#define PCI_INTERRUPT_PIN_SHIFT   8
 
#define PCI_INTERRUPT_PIN_MASK   0xff
 
#define PCI_INTERRUPT_PIN(icr)   (((icr) >> PCI_INTERRUPT_PIN_SHIFT) & PCI_INTERRUPT_PIN_MASK)
 
#define PCI_INTERRUPT_LINE_SHIFT   0
 
#define PCI_INTERRUPT_LINE_MASK   0xff
 
#define PCI_INTERRUPT_LINE(icr)   (((icr) >> PCI_INTERRUPT_LINE_SHIFT) & PCI_INTERRUPT_LINE_MASK)
 
#define PCI_INTERRUPT_CODE(lat, gnt, pin, line)
 
#define PCI_INTERRUPT_PIN_NONE   0x00
 
#define PCI_INTERRUPT_PIN_A   0x01
 
#define PCI_INTERRUPT_PIN_B   0x02
 
#define PCI_INTERRUPT_PIN_C   0x03
 
#define PCI_INTERRUPT_PIN_D   0x04
 
#define PCI_INTERRUPT_PIN_MAX   0x04
 
#define PCI_BRIDGE_BUS_REG   0x18
 
#define PCI_BRIDGE_BUS_PRIMARY_SHIFT   0
 
#define PCI_BRIDGE_BUS_SECONDARY_SHIFT   8
 
#define PCI_BRIDGE_BUS_SUBORDINATE_SHIFT   16
 
#define PCI_BRIDGE_STATIO_REG   0x1C
 
#define PCI_BRIDGE_STATIO_IOBASE_SHIFT   0
 
#define PCI_BRIDGE_STATIO_IOLIMIT_SHIFT   8
 
#define PCI_BRIDGE_STATIO_STATUS_SHIFT   16
 
#define PCI_BRIDGE_STATIO_IOBASE_MASK   0xf0
 
#define PCI_BRIDGE_STATIO_IOLIMIT_MASK   0xf0
 
#define PCI_BRIDGE_STATIO_STATUS_MASK   0xffff
 
#define PCI_BRIDGE_IO_32BITS(reg)   (((reg) & 0xf) == 1)
 
#define PCI_BRIDGE_MEMORY_REG   0x20
 
#define PCI_BRIDGE_MEMORY_BASE_SHIFT   4
 
#define PCI_BRIDGE_MEMORY_LIMIT_SHIFT   20
 
#define PCI_BRIDGE_MEMORY_BASE_MASK   0xffff
 
#define PCI_BRIDGE_MEMORY_LIMIT_MASK   0xffff
 
#define PCI_BRIDGE_PREFETCHMEM_REG   0x24
 
#define PCI_BRIDGE_PREFETCHMEM_BASE_SHIFT   4
 
#define PCI_BRIDGE_PREFETCHMEM_LIMIT_SHIFT   20
 
#define PCI_BRIDGE_PREFETCHMEM_BASE_MASK   0xffff
 
#define PCI_BRIDGE_PREFETCHMEM_LIMIT_MASK   0xffff
 
#define PCI_BRIDGE_PREFETCHMEM_64BITS(reg)   ((reg) & 0xf)
 
#define PCI_BRIDGE_PREFETCHBASE32_REG   0x28
 
#define PCI_BRIDGE_PREFETCHLIMIT32_REG   0x2C
 
#define PCI_BRIDGE_IOHIGH_REG   0x30
 
#define PCI_BRIDGE_IOHIGH_BASE_SHIFT   0
 
#define PCI_BRIDGE_IOHIGH_LIMIT_SHIFT   16
 
#define PCI_BRIDGE_IOHIGH_BASE_MASK   0xffff
 
#define PCI_BRIDGE_IOHIGH_LIMIT_MASK   0xffff
 
#define PCI_BRIDGE_CONTROL_REG   0x3C
 
#define PCI_BRIDGE_CONTROL_SHIFT   16
 
#define PCI_BRIDGE_CONTROL_MASK   0xffff
 
#define PCI_BRIDGE_CONTROL_PERE   (1 << 0)
 
#define PCI_BRIDGE_CONTROL_SERR   (1 << 1)
 
#define PCI_BRIDGE_CONTROL_ISA   (1 << 2)
 
#define PCI_BRIDGE_CONTROL_VGA   (1 << 3)
 
#define PCI_BRIDGE_CONTROL_MABRT   (1 << 5)
 
#define PCI_BRIDGE_CONTROL_SECBR   (1 << 6)
 
#define PCI_BRIDGE_CONTROL_SECFASTB2B   (1 << 7)
 
#define PCI_BRIDGE_CONTROL_PRI_DISC_TIMER   (1 << 8)
 
#define PCI_BRIDGE_CONTROL_SEC_DISC_TIMER   (1 << 9)
 
#define PCI_BRIDGE_CONTROL_DISC_TIMER_STAT   (1 << 10)
 
#define PCI_BRIDGE_CONTROL_DISC_TIMER_SERR   (1 << 11)
 
#define PCI_VPDRES_ISLARGE(x)   ((x) & 0x80)
 
#define PCI_VPDRES_SMALL_LENGTH(x)   ((x) & 0x7)
 
#define PCI_VPDRES_SMALL_NAME(x)   (((x) >> 3) & 0xf)
 
#define PCI_VPDRES_LARGE_NAME(x)   ((x) & 0x7f)
 
#define PCI_VPDRES_TYPE_COMPATIBLE_DEVICE_ID   0x3 /* small */
 
#define PCI_VPDRES_TYPE_VENDOR_DEFINED   0xe /* small */
 
#define PCI_VPDRES_TYPE_END_TAG   0xf /* small */
 
#define PCI_VPDRES_TYPE_IDENTIFIER_STRING   0x02 /* large */
 
#define PCI_VPDRES_TYPE_VPD   0x10 /* large */
 

Typedefs

typedef u_int16_t pci_vendor_id_t
 
typedef u_int16_t pci_product_id_t
 
typedef u_int8_t pci_class_t
 
typedef u_int8_t pci_subclass_t
 
typedef u_int8_t pci_interface_t
 
typedef u_int8_t pci_revision_t
 
typedef u_int8_t pci_intr_latency_t
 
typedef u_int8_t pci_intr_grant_t
 
typedef u_int8_t pci_intr_pin_t
 
typedef u_int8_t pci_intr_line_t
 

Functions

struct pci_vpd_smallres __attribute__ ((__packed__))
 

Variables

uint8_t vpdres_byte0
 
uint8_t vpdres_len_lsb
 
uint8_t vpdres_len_msb
 
uint8_t vpd_key0
 
uint8_t vpd_key1
 
uint8_t vpd_len
 

Macro Definition Documentation

◆ __attribute__

#define __attribute__ (   x)    /* */

Definition at line 15 of file pcireg.h.

◆ __noreturn__

#define __noreturn__   /* */

Definition at line 16 of file pcireg.h.

◆ PCI_BHLC_CODE

#define PCI_BHLC_CODE (   bist,
  type,
  multi,
  latency,
  cacheline 
)
Value:
((((bist) & PCI_BIST_MASK) << PCI_BIST_SHIFT) | \
(((type) & PCI_HDRTYPE_MASK) << PCI_HDRTYPE_SHIFT) | \
(((multi)?0x80:0) << PCI_HDRTYPE_SHIFT) | \
(((latency) & PCI_LATTIMER_MASK) << PCI_LATTIMER_SHIFT) | \
#define PCI_BIST_MASK
Definition: pcireg.h:312
#define PCI_HDRTYPE_SHIFT
Definition: pcireg.h:316
#define PCI_LATTIMER_SHIFT
Definition: pcireg.h:326
#define PCI_LATTIMER_MASK
Definition: pcireg.h:327
#define PCI_HDRTYPE_MASK
Definition: pcireg.h:317
#define PCI_CACHELINE_MASK
Definition: pcireg.h:332
#define PCI_BIST_SHIFT
Definition: pcireg.h:311
#define PCI_CACHELINE_SHIFT
Definition: pcireg.h:331

Definition at line 336 of file pcireg.h.

Referenced by PCIINIT().

◆ PCI_BHLC_REG

#define PCI_BHLC_REG   0x0c

Definition at line 309 of file pcireg.h.

Referenced by PCIINIT().

◆ PCI_BIST

#define PCI_BIST (   bhlcr)    (((bhlcr) >> PCI_BIST_SHIFT) & PCI_BIST_MASK)

Definition at line 313 of file pcireg.h.

◆ PCI_BIST_MASK

#define PCI_BIST_MASK   0xff

Definition at line 312 of file pcireg.h.

◆ PCI_BIST_SHIFT

#define PCI_BIST_SHIFT   24

Definition at line 311 of file pcireg.h.

◆ PCI_BRIDGE_BUS_PRIMARY_SHIFT

#define PCI_BRIDGE_BUS_PRIMARY_SHIFT   0

Definition at line 497 of file pcireg.h.

◆ PCI_BRIDGE_BUS_REG

#define PCI_BRIDGE_BUS_REG   0x18

Definition at line 496 of file pcireg.h.

◆ PCI_BRIDGE_BUS_SECONDARY_SHIFT

#define PCI_BRIDGE_BUS_SECONDARY_SHIFT   8

Definition at line 498 of file pcireg.h.

◆ PCI_BRIDGE_BUS_SUBORDINATE_SHIFT

#define PCI_BRIDGE_BUS_SUBORDINATE_SHIFT   16

Definition at line 499 of file pcireg.h.

◆ PCI_BRIDGE_CONTROL_DISC_TIMER_SERR

#define PCI_BRIDGE_CONTROL_DISC_TIMER_SERR   (1 << 11)

Definition at line 546 of file pcireg.h.

◆ PCI_BRIDGE_CONTROL_DISC_TIMER_STAT

#define PCI_BRIDGE_CONTROL_DISC_TIMER_STAT   (1 << 10)

Definition at line 545 of file pcireg.h.

◆ PCI_BRIDGE_CONTROL_ISA

#define PCI_BRIDGE_CONTROL_ISA   (1 << 2)

Definition at line 537 of file pcireg.h.

◆ PCI_BRIDGE_CONTROL_MABRT

#define PCI_BRIDGE_CONTROL_MABRT   (1 << 5)

Definition at line 540 of file pcireg.h.

◆ PCI_BRIDGE_CONTROL_MASK

#define PCI_BRIDGE_CONTROL_MASK   0xffff

Definition at line 534 of file pcireg.h.

◆ PCI_BRIDGE_CONTROL_PERE

#define PCI_BRIDGE_CONTROL_PERE   (1 << 0)

Definition at line 535 of file pcireg.h.

◆ PCI_BRIDGE_CONTROL_PRI_DISC_TIMER

#define PCI_BRIDGE_CONTROL_PRI_DISC_TIMER   (1 << 8)

Definition at line 543 of file pcireg.h.

◆ PCI_BRIDGE_CONTROL_REG

#define PCI_BRIDGE_CONTROL_REG   0x3C

Definition at line 532 of file pcireg.h.

◆ PCI_BRIDGE_CONTROL_SEC_DISC_TIMER

#define PCI_BRIDGE_CONTROL_SEC_DISC_TIMER   (1 << 9)

Definition at line 544 of file pcireg.h.

◆ PCI_BRIDGE_CONTROL_SECBR

#define PCI_BRIDGE_CONTROL_SECBR   (1 << 6)

Definition at line 541 of file pcireg.h.

◆ PCI_BRIDGE_CONTROL_SECFASTB2B

#define PCI_BRIDGE_CONTROL_SECFASTB2B   (1 << 7)

Definition at line 542 of file pcireg.h.

◆ PCI_BRIDGE_CONTROL_SERR

#define PCI_BRIDGE_CONTROL_SERR   (1 << 1)

Definition at line 536 of file pcireg.h.

◆ PCI_BRIDGE_CONTROL_SHIFT

#define PCI_BRIDGE_CONTROL_SHIFT   16

Definition at line 533 of file pcireg.h.

◆ PCI_BRIDGE_CONTROL_VGA

#define PCI_BRIDGE_CONTROL_VGA   (1 << 3)

Definition at line 538 of file pcireg.h.

◆ PCI_BRIDGE_IO_32BITS

#define PCI_BRIDGE_IO_32BITS (   reg)    (((reg) & 0xf) == 1)

Definition at line 508 of file pcireg.h.

◆ PCI_BRIDGE_IOHIGH_BASE_MASK

#define PCI_BRIDGE_IOHIGH_BASE_MASK   0xffff

Definition at line 529 of file pcireg.h.

◆ PCI_BRIDGE_IOHIGH_BASE_SHIFT

#define PCI_BRIDGE_IOHIGH_BASE_SHIFT   0

Definition at line 527 of file pcireg.h.

◆ PCI_BRIDGE_IOHIGH_LIMIT_MASK

#define PCI_BRIDGE_IOHIGH_LIMIT_MASK   0xffff

Definition at line 530 of file pcireg.h.

◆ PCI_BRIDGE_IOHIGH_LIMIT_SHIFT

#define PCI_BRIDGE_IOHIGH_LIMIT_SHIFT   16

Definition at line 528 of file pcireg.h.

◆ PCI_BRIDGE_IOHIGH_REG

#define PCI_BRIDGE_IOHIGH_REG   0x30

Definition at line 526 of file pcireg.h.

◆ PCI_BRIDGE_MEMORY_BASE_MASK

#define PCI_BRIDGE_MEMORY_BASE_MASK   0xffff

Definition at line 513 of file pcireg.h.

◆ PCI_BRIDGE_MEMORY_BASE_SHIFT

#define PCI_BRIDGE_MEMORY_BASE_SHIFT   4

Definition at line 511 of file pcireg.h.

◆ PCI_BRIDGE_MEMORY_LIMIT_MASK

#define PCI_BRIDGE_MEMORY_LIMIT_MASK   0xffff

Definition at line 514 of file pcireg.h.

◆ PCI_BRIDGE_MEMORY_LIMIT_SHIFT

#define PCI_BRIDGE_MEMORY_LIMIT_SHIFT   20

Definition at line 512 of file pcireg.h.

◆ PCI_BRIDGE_MEMORY_REG

#define PCI_BRIDGE_MEMORY_REG   0x20

Definition at line 510 of file pcireg.h.

◆ PCI_BRIDGE_PREFETCHBASE32_REG

#define PCI_BRIDGE_PREFETCHBASE32_REG   0x28

Definition at line 523 of file pcireg.h.

◆ PCI_BRIDGE_PREFETCHLIMIT32_REG

#define PCI_BRIDGE_PREFETCHLIMIT32_REG   0x2C

Definition at line 524 of file pcireg.h.

◆ PCI_BRIDGE_PREFETCHMEM_64BITS

#define PCI_BRIDGE_PREFETCHMEM_64BITS (   reg)    ((reg) & 0xf)

Definition at line 521 of file pcireg.h.

◆ PCI_BRIDGE_PREFETCHMEM_BASE_MASK

#define PCI_BRIDGE_PREFETCHMEM_BASE_MASK   0xffff

Definition at line 519 of file pcireg.h.

◆ PCI_BRIDGE_PREFETCHMEM_BASE_SHIFT

#define PCI_BRIDGE_PREFETCHMEM_BASE_SHIFT   4

Definition at line 517 of file pcireg.h.

◆ PCI_BRIDGE_PREFETCHMEM_LIMIT_MASK

#define PCI_BRIDGE_PREFETCHMEM_LIMIT_MASK   0xffff

Definition at line 520 of file pcireg.h.

◆ PCI_BRIDGE_PREFETCHMEM_LIMIT_SHIFT

#define PCI_BRIDGE_PREFETCHMEM_LIMIT_SHIFT   20

Definition at line 518 of file pcireg.h.

◆ PCI_BRIDGE_PREFETCHMEM_REG

#define PCI_BRIDGE_PREFETCHMEM_REG   0x24

Definition at line 516 of file pcireg.h.

◆ PCI_BRIDGE_STATIO_IOBASE_MASK

#define PCI_BRIDGE_STATIO_IOBASE_MASK   0xf0

Definition at line 505 of file pcireg.h.

◆ PCI_BRIDGE_STATIO_IOBASE_SHIFT

#define PCI_BRIDGE_STATIO_IOBASE_SHIFT   0

Definition at line 502 of file pcireg.h.

◆ PCI_BRIDGE_STATIO_IOLIMIT_MASK

#define PCI_BRIDGE_STATIO_IOLIMIT_MASK   0xf0

Definition at line 506 of file pcireg.h.

◆ PCI_BRIDGE_STATIO_IOLIMIT_SHIFT

#define PCI_BRIDGE_STATIO_IOLIMIT_SHIFT   8

Definition at line 503 of file pcireg.h.

◆ PCI_BRIDGE_STATIO_REG

#define PCI_BRIDGE_STATIO_REG   0x1C

Definition at line 501 of file pcireg.h.

◆ PCI_BRIDGE_STATIO_STATUS_MASK

#define PCI_BRIDGE_STATIO_STATUS_MASK   0xffff

Definition at line 507 of file pcireg.h.

◆ PCI_BRIDGE_STATIO_STATUS_SHIFT

#define PCI_BRIDGE_STATIO_STATUS_SHIFT   16

Definition at line 504 of file pcireg.h.

◆ PCI_CACHELINE

#define PCI_CACHELINE (   bhlcr)    (((bhlcr) >> PCI_CACHELINE_SHIFT) & PCI_CACHELINE_MASK)

Definition at line 333 of file pcireg.h.

◆ PCI_CACHELINE_MASK

#define PCI_CACHELINE_MASK   0xff

Definition at line 332 of file pcireg.h.

◆ PCI_CACHELINE_SHIFT

#define PCI_CACHELINE_SHIFT   0

Definition at line 331 of file pcireg.h.

◆ PCI_CAP_AGP

#define PCI_CAP_AGP   0x02

Definition at line 420 of file pcireg.h.

◆ PCI_CAP_CPCI_HOTSWAP

#define PCI_CAP_CPCI_HOTSWAP   0x06

Definition at line 424 of file pcireg.h.

◆ PCI_CAP_CPCI_RSRCCTL

#define PCI_CAP_CPCI_RSRCCTL   0x0b

Definition at line 429 of file pcireg.h.

◆ PCI_CAP_DEBUGPORT

#define PCI_CAP_DEBUGPORT   0x0a

Definition at line 428 of file pcireg.h.

◆ PCI_CAP_HOTPLUG

#define PCI_CAP_HOTPLUG   0x0c

Definition at line 430 of file pcireg.h.

◆ PCI_CAP_LDT

#define PCI_CAP_LDT   0x08

Definition at line 426 of file pcireg.h.

◆ PCI_CAP_MBI

#define PCI_CAP_MBI   0x05

Definition at line 423 of file pcireg.h.

◆ PCI_CAP_PCIX

#define PCI_CAP_PCIX   0x07

Definition at line 425 of file pcireg.h.

◆ PCI_CAP_PWRMGMT

#define PCI_CAP_PWRMGMT   0x01

Definition at line 419 of file pcireg.h.

◆ PCI_CAP_RESERVED0

#define PCI_CAP_RESERVED0   0x00

Definition at line 418 of file pcireg.h.

◆ PCI_CAP_SLOTID

#define PCI_CAP_SLOTID   0x04

Definition at line 422 of file pcireg.h.

◆ PCI_CAP_VENDSPEC

#define PCI_CAP_VENDSPEC   0x09

Definition at line 427 of file pcireg.h.

◆ PCI_CAP_VPD

#define PCI_CAP_VPD   0x03

Definition at line 421 of file pcireg.h.

◆ PCI_CAPLIST_CAP

#define PCI_CAPLIST_CAP (   cr)    ((cr) & 0xff)

Definition at line 416 of file pcireg.h.

◆ PCI_CAPLIST_NEXT

#define PCI_CAPLIST_NEXT (   cr)    (((cr) >> 8) & 0xff)

Definition at line 415 of file pcireg.h.

◆ PCI_CAPLIST_PTR

#define PCI_CAPLIST_PTR (   cpr)    ((cpr) & 0xff)

Definition at line 414 of file pcireg.h.

◆ PCI_CAPLISTPTR_REG

#define PCI_CAPLISTPTR_REG   0x34 /* header type 0 */

Definition at line 412 of file pcireg.h.

Referenced by PCIINIT().

◆ PCI_CARDBUS_CAPLISTPTR_REG

#define PCI_CARDBUS_CAPLISTPTR_REG   0x14 /* header type 2 */

Definition at line 413 of file pcireg.h.

◆ PCI_CARDBUS_CIS_REG

#define PCI_CARDBUS_CIS_REG   0x28

Definition at line 400 of file pcireg.h.

◆ PCI_CLASS

#define PCI_CLASS (   cr)    (((cr) >> PCI_CLASS_SHIFT) & PCI_CLASS_MASK)

Definition at line 128 of file pcireg.h.

◆ PCI_CLASS_BRIDGE

#define PCI_CLASS_BRIDGE   0x06

Definition at line 158 of file pcireg.h.

Referenced by DEVINIT(), and PCIINIT().

◆ PCI_CLASS_CODE

#define PCI_CLASS_CODE (   mainclass,
  subclass,
  interface 
)
Value:
((((mainclass) & PCI_CLASS_MASK) << PCI_CLASS_SHIFT) | \
(((subclass) & PCI_SUBCLASS_MASK) << PCI_SUBCLASS_SHIFT) | \
#define PCI_INTERFACE_SHIFT
Definition: pcireg.h:136
#define PCI_CLASS_SHIFT
Definition: pcireg.h:126
#define PCI_CLASS_MASK
Definition: pcireg.h:127
#define PCI_SUBCLASS_SHIFT
Definition: pcireg.h:131
#define PCI_INTERFACE_MASK
Definition: pcireg.h:137
#define PCI_SUBCLASS_MASK
Definition: pcireg.h:132

Definition at line 146 of file pcireg.h.

Referenced by DEVINIT(), and PCIINIT().

◆ PCI_CLASS_COMMUNICATIONS

#define PCI_CLASS_COMMUNICATIONS   0x07

Definition at line 159 of file pcireg.h.

◆ PCI_CLASS_CRYPTO

#define PCI_CLASS_CRYPTO   0x10

Definition at line 168 of file pcireg.h.

◆ PCI_CLASS_DASP

#define PCI_CLASS_DASP   0x11

Definition at line 169 of file pcireg.h.

◆ PCI_CLASS_DISPLAY

#define PCI_CLASS_DISPLAY   0x03

Definition at line 155 of file pcireg.h.

Referenced by PCIINIT().

◆ PCI_CLASS_DOCK

#define PCI_CLASS_DOCK   0x0a

Definition at line 162 of file pcireg.h.

◆ PCI_CLASS_I2O

#define PCI_CLASS_I2O   0x0e

Definition at line 166 of file pcireg.h.

◆ PCI_CLASS_INPUT

#define PCI_CLASS_INPUT   0x09

Definition at line 161 of file pcireg.h.

◆ PCI_CLASS_MASK

#define PCI_CLASS_MASK   0xff

Definition at line 127 of file pcireg.h.

◆ PCI_CLASS_MASS_STORAGE

#define PCI_CLASS_MASS_STORAGE   0x01

Definition at line 153 of file pcireg.h.

Referenced by PCIINIT().

◆ PCI_CLASS_MEMORY

#define PCI_CLASS_MEMORY   0x05

Definition at line 157 of file pcireg.h.

◆ PCI_CLASS_MULTIMEDIA

#define PCI_CLASS_MULTIMEDIA   0x04

Definition at line 156 of file pcireg.h.

◆ PCI_CLASS_NETWORK

#define PCI_CLASS_NETWORK   0x02

Definition at line 154 of file pcireg.h.

Referenced by PCIINIT().

◆ PCI_CLASS_PREHISTORIC

#define PCI_CLASS_PREHISTORIC   0x00

Definition at line 152 of file pcireg.h.

◆ PCI_CLASS_PROCESSOR

#define PCI_CLASS_PROCESSOR   0x0b

Definition at line 163 of file pcireg.h.

◆ PCI_CLASS_REG

#define PCI_CLASS_REG   0x08

Definition at line 119 of file pcireg.h.

Referenced by PCIINIT().

◆ PCI_CLASS_SATCOM

#define PCI_CLASS_SATCOM   0x0f

Definition at line 167 of file pcireg.h.

◆ PCI_CLASS_SERIALBUS

#define PCI_CLASS_SERIALBUS   0x0c

Definition at line 164 of file pcireg.h.

◆ PCI_CLASS_SHIFT

#define PCI_CLASS_SHIFT   24

Definition at line 126 of file pcireg.h.

◆ PCI_CLASS_SYSTEM

#define PCI_CLASS_SYSTEM   0x08

Definition at line 160 of file pcireg.h.

Referenced by PCIINIT().

◆ PCI_CLASS_UNDEFINED

#define PCI_CLASS_UNDEFINED   0xff

Definition at line 170 of file pcireg.h.

◆ PCI_CLASS_WIRELESS

#define PCI_CLASS_WIRELESS   0x0d

Definition at line 165 of file pcireg.h.

◆ PCI_COMMAND_BACKTOBACK_ENABLE

#define PCI_COMMAND_BACKTOBACK_ENABLE   0x00000200

Definition at line 99 of file pcireg.h.

◆ PCI_COMMAND_INVALIDATE_ENABLE

#define PCI_COMMAND_INVALIDATE_ENABLE   0x00000010

Definition at line 94 of file pcireg.h.

◆ PCI_COMMAND_IO_ENABLE

#define PCI_COMMAND_IO_ENABLE   0x00000001

◆ PCI_COMMAND_MASK

#define PCI_COMMAND_MASK   0xffff

Definition at line 82 of file pcireg.h.

◆ PCI_COMMAND_MASTER_ENABLE

#define PCI_COMMAND_MASTER_ENABLE   0x00000004

Definition at line 92 of file pcireg.h.

◆ PCI_COMMAND_MEM_ENABLE

#define PCI_COMMAND_MEM_ENABLE   0x00000002

Definition at line 91 of file pcireg.h.

Referenced by bus_pci_add().

◆ PCI_COMMAND_PALETTE_ENABLE

#define PCI_COMMAND_PALETTE_ENABLE   0x00000020

Definition at line 95 of file pcireg.h.

◆ PCI_COMMAND_PARITY_ENABLE

#define PCI_COMMAND_PARITY_ENABLE   0x00000040

Definition at line 96 of file pcireg.h.

◆ PCI_COMMAND_SERR_ENABLE

#define PCI_COMMAND_SERR_ENABLE   0x00000100

Definition at line 98 of file pcireg.h.

◆ PCI_COMMAND_SHIFT

#define PCI_COMMAND_SHIFT   0

Definition at line 81 of file pcireg.h.

◆ PCI_COMMAND_SPECIAL_ENABLE

#define PCI_COMMAND_SPECIAL_ENABLE   0x00000008

Definition at line 93 of file pcireg.h.

◆ PCI_COMMAND_STATUS_CODE

#define PCI_COMMAND_STATUS_CODE (   cmd,
  stat 
)
Value:
#define PCI_STATUS_MASK
Definition: pcireg.h:84
#define PCI_STATUS_SHIFT
Definition: pcireg.h:83
#define PCI_COMMAND_MASK
Definition: pcireg.h:82
#define PCI_COMMAND_SHIFT
Definition: pcireg.h:81

Definition at line 86 of file pcireg.h.

◆ PCI_COMMAND_STATUS_REG

#define PCI_COMMAND_STATUS_REG   0x04

◆ PCI_COMMAND_STEPPING_ENABLE

#define PCI_COMMAND_STEPPING_ENABLE   0x00000080

Definition at line 97 of file pcireg.h.

◆ PCI_HDRTYPE

#define PCI_HDRTYPE (   bhlcr)    (((bhlcr) >> PCI_HDRTYPE_SHIFT) & PCI_HDRTYPE_MASK)

Definition at line 318 of file pcireg.h.

◆ PCI_HDRTYPE_MASK

#define PCI_HDRTYPE_MASK   0xff

Definition at line 317 of file pcireg.h.

◆ PCI_HDRTYPE_MULTIFN

#define PCI_HDRTYPE_MULTIFN (   bhlcr)    ((PCI_HDRTYPE(bhlcr) & 0x80) != 0)

Definition at line 323 of file pcireg.h.

◆ PCI_HDRTYPE_SHIFT

#define PCI_HDRTYPE_SHIFT   16

Definition at line 316 of file pcireg.h.

◆ PCI_HDRTYPE_TYPE

#define PCI_HDRTYPE_TYPE (   bhlcr)    (PCI_HDRTYPE(bhlcr) & 0x7f)

Definition at line 321 of file pcireg.h.

◆ PCI_ID_CODE

#define PCI_ID_CODE (   vid,
  pid 
)
Value:
((((vid) & PCI_VENDOR_MASK) << PCI_VENDOR_SHIFT) | \
(((uint32_t)((pid) & PCI_PRODUCT_MASK)) << PCI_PRODUCT_SHIFT))
#define PCI_PRODUCT_SHIFT
Definition: pcireg.h:68
#define PCI_VENDOR_MASK
Definition: pcireg.h:64
#define PCI_PRODUCT_MASK
Definition: pcireg.h:69
#define PCI_VENDOR_SHIFT
Definition: pcireg.h:63

Definition at line 73 of file pcireg.h.

Referenced by DEVICE_ACCESS(), and PCIINIT().

◆ PCI_ID_REG

#define PCI_ID_REG   0x00

Definition at line 58 of file pcireg.h.

Referenced by PCIINIT().

◆ PCI_INTERFACE

#define PCI_INTERFACE (   cr)    (((cr) >> PCI_INTERFACE_SHIFT) & PCI_INTERFACE_MASK)

Definition at line 138 of file pcireg.h.

◆ PCI_INTERFACE_MASK

#define PCI_INTERFACE_MASK   0xff

Definition at line 137 of file pcireg.h.

◆ PCI_INTERFACE_SHIFT

#define PCI_INTERFACE_SHIFT   8

Definition at line 136 of file pcireg.h.

◆ PCI_INTERRUPT_CODE

#define PCI_INTERRUPT_CODE (   lat,
  gnt,
  pin,
  line 
)
Value:
#define PCI_INTERRUPT_LATENCY_SHIFT
Definition: pcireg.h:467
#define PCI_INTERRUPT_GRANT_SHIFT
Definition: pcireg.h:462
#define PCI_INTERRUPT_PIN_SHIFT
Definition: pcireg.h:472
#define PCI_INTERRUPT_LATENCY_MASK
Definition: pcireg.h:468
#define PCI_INTERRUPT_LINE_MASK
Definition: pcireg.h:478
#define PCI_INTERRUPT_GRANT_MASK
Definition: pcireg.h:463
#define PCI_INTERRUPT_PIN_MASK
Definition: pcireg.h:473
#define PCI_INTERRUPT_LINE_SHIFT
Definition: pcireg.h:477

Definition at line 482 of file pcireg.h.

◆ PCI_INTERRUPT_GRANT

#define PCI_INTERRUPT_GRANT (   icr)    (((icr) >> PCI_INTERRUPT_GRANT_SHIFT) & PCI_INTERRUPT_GRANT_MASK)

Definition at line 464 of file pcireg.h.

◆ PCI_INTERRUPT_GRANT_MASK

#define PCI_INTERRUPT_GRANT_MASK   0xff

Definition at line 463 of file pcireg.h.

◆ PCI_INTERRUPT_GRANT_SHIFT

#define PCI_INTERRUPT_GRANT_SHIFT   24

Definition at line 462 of file pcireg.h.

◆ PCI_INTERRUPT_LATENCY

#define PCI_INTERRUPT_LATENCY (   icr)    (((icr) >> PCI_INTERRUPT_LATENCY_SHIFT) & PCI_INTERRUPT_LATENCY_MASK)

Definition at line 469 of file pcireg.h.

◆ PCI_INTERRUPT_LATENCY_MASK

#define PCI_INTERRUPT_LATENCY_MASK   0xff

Definition at line 468 of file pcireg.h.

◆ PCI_INTERRUPT_LATENCY_SHIFT

#define PCI_INTERRUPT_LATENCY_SHIFT   16

Definition at line 467 of file pcireg.h.

◆ PCI_INTERRUPT_LINE

#define PCI_INTERRUPT_LINE (   icr)    (((icr) >> PCI_INTERRUPT_LINE_SHIFT) & PCI_INTERRUPT_LINE_MASK)

Definition at line 479 of file pcireg.h.

◆ PCI_INTERRUPT_LINE_MASK

#define PCI_INTERRUPT_LINE_MASK   0xff

Definition at line 478 of file pcireg.h.

◆ PCI_INTERRUPT_LINE_SHIFT

#define PCI_INTERRUPT_LINE_SHIFT   0

Definition at line 477 of file pcireg.h.

◆ PCI_INTERRUPT_PIN

#define PCI_INTERRUPT_PIN (   icr)    (((icr) >> PCI_INTERRUPT_PIN_SHIFT) & PCI_INTERRUPT_PIN_MASK)

Definition at line 474 of file pcireg.h.

◆ PCI_INTERRUPT_PIN_A

#define PCI_INTERRUPT_PIN_A   0x01

Definition at line 489 of file pcireg.h.

◆ PCI_INTERRUPT_PIN_B

#define PCI_INTERRUPT_PIN_B   0x02

Definition at line 490 of file pcireg.h.

◆ PCI_INTERRUPT_PIN_C

#define PCI_INTERRUPT_PIN_C   0x03

Definition at line 491 of file pcireg.h.

◆ PCI_INTERRUPT_PIN_D

#define PCI_INTERRUPT_PIN_D   0x04

Definition at line 492 of file pcireg.h.

◆ PCI_INTERRUPT_PIN_MASK

#define PCI_INTERRUPT_PIN_MASK   0xff

Definition at line 473 of file pcireg.h.

◆ PCI_INTERRUPT_PIN_MAX

#define PCI_INTERRUPT_PIN_MAX   0x04

Definition at line 493 of file pcireg.h.

◆ PCI_INTERRUPT_PIN_NONE

#define PCI_INTERRUPT_PIN_NONE   0x00

Definition at line 488 of file pcireg.h.

◆ PCI_INTERRUPT_PIN_SHIFT

#define PCI_INTERRUPT_PIN_SHIFT   8

Definition at line 472 of file pcireg.h.

◆ PCI_INTERRUPT_REG

#define PCI_INTERRUPT_REG   0x3c

Definition at line 445 of file pcireg.h.

Referenced by PCIINIT().

◆ PCI_LATTIMER

#define PCI_LATTIMER (   bhlcr)    (((bhlcr) >> PCI_LATTIMER_SHIFT) & PCI_LATTIMER_MASK)

Definition at line 328 of file pcireg.h.

◆ PCI_LATTIMER_MASK

#define PCI_LATTIMER_MASK   0xff

Definition at line 327 of file pcireg.h.

◆ PCI_LATTIMER_SHIFT

#define PCI_LATTIMER_SHIFT   8

Definition at line 326 of file pcireg.h.

◆ PCI_MAPREG_END

#define PCI_MAPREG_END   0x28

Definition at line 347 of file pcireg.h.

Referenced by bus_pci_add(), and bus_pci_data_access().

◆ PCI_MAPREG_IO_ADDR

#define PCI_MAPREG_IO_ADDR (   mr)    ((mr) & PCI_MAPREG_IO_ADDR_MASK)

Definition at line 384 of file pcireg.h.

◆ PCI_MAPREG_IO_ADDR_MASK

#define PCI_MAPREG_IO_ADDR_MASK   0xfffffffc

Definition at line 388 of file pcireg.h.

◆ PCI_MAPREG_IO_SIZE

#define PCI_MAPREG_IO_SIZE (   mr)    (PCI_MAPREG_IO_ADDR(mr) & -PCI_MAPREG_IO_ADDR(mr))

Definition at line 386 of file pcireg.h.

◆ PCI_MAPREG_MEM64_ADDR

#define PCI_MAPREG_MEM64_ADDR (   mr)    ((mr) & PCI_MAPREG_MEM64_ADDR_MASK)

Definition at line 378 of file pcireg.h.

◆ PCI_MAPREG_MEM64_ADDR_MASK

#define PCI_MAPREG_MEM64_ADDR_MASK   0xfffffffffffffff0ULL

Definition at line 382 of file pcireg.h.

◆ PCI_MAPREG_MEM64_SIZE

#define PCI_MAPREG_MEM64_SIZE (   mr)    (PCI_MAPREG_MEM64_ADDR(mr) & -PCI_MAPREG_MEM64_ADDR(mr))

Definition at line 380 of file pcireg.h.

◆ PCI_MAPREG_MEM_ADDR

#define PCI_MAPREG_MEM_ADDR (   mr)    ((mr) & PCI_MAPREG_MEM_ADDR_MASK)

Definition at line 372 of file pcireg.h.

◆ PCI_MAPREG_MEM_ADDR_MASK

#define PCI_MAPREG_MEM_ADDR_MASK   0xfffffff0

Definition at line 376 of file pcireg.h.

◆ PCI_MAPREG_MEM_PREFETCHABLE

#define PCI_MAPREG_MEM_PREFETCHABLE (   mr)    (((mr) & PCI_MAPREG_MEM_PREFETCHABLE_MASK) != 0)

Definition at line 368 of file pcireg.h.

◆ PCI_MAPREG_MEM_PREFETCHABLE_MASK

#define PCI_MAPREG_MEM_PREFETCHABLE_MASK   0x00000008

Definition at line 370 of file pcireg.h.

◆ PCI_MAPREG_MEM_SIZE

#define PCI_MAPREG_MEM_SIZE (   mr)    (PCI_MAPREG_MEM_ADDR(mr) & -PCI_MAPREG_MEM_ADDR(mr))

Definition at line 374 of file pcireg.h.

◆ PCI_MAPREG_MEM_TYPE

#define PCI_MAPREG_MEM_TYPE (   mr)    ((mr) & PCI_MAPREG_MEM_TYPE_MASK)

Definition at line 360 of file pcireg.h.

◆ PCI_MAPREG_MEM_TYPE_32BIT

#define PCI_MAPREG_MEM_TYPE_32BIT   0x00000000

Definition at line 364 of file pcireg.h.

◆ PCI_MAPREG_MEM_TYPE_32BIT_1M

#define PCI_MAPREG_MEM_TYPE_32BIT_1M   0x00000002

Definition at line 365 of file pcireg.h.

◆ PCI_MAPREG_MEM_TYPE_64BIT

#define PCI_MAPREG_MEM_TYPE_64BIT   0x00000004

Definition at line 366 of file pcireg.h.

◆ PCI_MAPREG_MEM_TYPE_MASK

#define PCI_MAPREG_MEM_TYPE_MASK   0x00000006

Definition at line 362 of file pcireg.h.

◆ PCI_MAPREG_NUM

#define PCI_MAPREG_NUM (   offset)    (((unsigned)(offset)-PCI_MAPREG_START)/4)

Definition at line 393 of file pcireg.h.

◆ PCI_MAPREG_PCB_END

#define PCI_MAPREG_PCB_END   0x14

Definition at line 350 of file pcireg.h.

◆ PCI_MAPREG_PPB_END

#define PCI_MAPREG_PPB_END   0x18

Definition at line 349 of file pcireg.h.

◆ PCI_MAPREG_ROM

#define PCI_MAPREG_ROM   0x30

Definition at line 348 of file pcireg.h.

◆ PCI_MAPREG_ROM_ENABLE

#define PCI_MAPREG_ROM_ENABLE   0x00000001

Definition at line 358 of file pcireg.h.

◆ PCI_MAPREG_SIZE_TO_MASK

#define PCI_MAPREG_SIZE_TO_MASK (   size)    (-(size))

Definition at line 390 of file pcireg.h.

◆ PCI_MAPREG_START

#define PCI_MAPREG_START   0x10

◆ PCI_MAPREG_TYPE

#define PCI_MAPREG_TYPE (   mr)    ((mr) & PCI_MAPREG_TYPE_MASK)

Definition at line 352 of file pcireg.h.

◆ PCI_MAPREG_TYPE_IO

#define PCI_MAPREG_TYPE_IO   0x00000001

Definition at line 357 of file pcireg.h.

◆ PCI_MAPREG_TYPE_MASK

#define PCI_MAPREG_TYPE_MASK   0x00000001

Definition at line 354 of file pcireg.h.

◆ PCI_MAPREG_TYPE_MEM

#define PCI_MAPREG_TYPE_MEM   0x00000000

Definition at line 356 of file pcireg.h.

◆ PCI_MAX_LAT

#define PCI_MAX_LAT (   icr)    (((icr) >> PCI_MAX_LAT_SHIFT) & PCI_MAX_LAT_MASK)

Definition at line 454 of file pcireg.h.

◆ PCI_MAX_LAT_MASK

#define PCI_MAX_LAT_MASK   0xff

Definition at line 453 of file pcireg.h.

◆ PCI_MAX_LAT_SHIFT

#define PCI_MAX_LAT_SHIFT   24

Definition at line 452 of file pcireg.h.

◆ PCI_MIN_GNT

#define PCI_MIN_GNT (   icr)    (((icr) >> PCI_MIN_GNT_SHIFT) & PCI_MIN_GNT_MASK)

Definition at line 459 of file pcireg.h.

◆ PCI_MIN_GNT_MASK

#define PCI_MIN_GNT_MASK   0xff

Definition at line 458 of file pcireg.h.

◆ PCI_MIN_GNT_SHIFT

#define PCI_MIN_GNT_SHIFT   16

Definition at line 457 of file pcireg.h.

◆ PCI_PMCSR_STATE_D0

#define PCI_PMCSR_STATE_D0   0x00

Definition at line 437 of file pcireg.h.

◆ PCI_PMCSR_STATE_D1

#define PCI_PMCSR_STATE_D1   0x01

Definition at line 438 of file pcireg.h.

◆ PCI_PMCSR_STATE_D2

#define PCI_PMCSR_STATE_D2   0x02

Definition at line 439 of file pcireg.h.

◆ PCI_PMCSR_STATE_D3

#define PCI_PMCSR_STATE_D3   0x03

Definition at line 440 of file pcireg.h.

◆ PCI_PMCSR_STATE_MASK

#define PCI_PMCSR_STATE_MASK   0x03

Definition at line 436 of file pcireg.h.

◆ PCI_PRODUCT

#define PCI_PRODUCT (   id)    (((id) >> PCI_PRODUCT_SHIFT) & PCI_PRODUCT_MASK)

Definition at line 70 of file pcireg.h.

◆ PCI_PRODUCT_MASK

#define PCI_PRODUCT_MASK   0xffff

Definition at line 69 of file pcireg.h.

◆ PCI_PRODUCT_SHIFT

#define PCI_PRODUCT_SHIFT   16

Definition at line 68 of file pcireg.h.

◆ PCI_REVISION

#define PCI_REVISION (   cr)    (((cr) >> PCI_REVISION_SHIFT) & PCI_REVISION_MASK)

Definition at line 143 of file pcireg.h.

◆ PCI_REVISION_MASK

#define PCI_REVISION_MASK   0xff

Definition at line 142 of file pcireg.h.

◆ PCI_REVISION_SHIFT

#define PCI_REVISION_SHIFT   0

Definition at line 141 of file pcireg.h.

◆ PCI_STATUS_66MHZ_SUPPORT

#define PCI_STATUS_66MHZ_SUPPORT   0x00200000

Definition at line 102 of file pcireg.h.

◆ PCI_STATUS_BACKTOBACK_SUPPORT

#define PCI_STATUS_BACKTOBACK_SUPPORT   0x00800000

Definition at line 104 of file pcireg.h.

◆ PCI_STATUS_CAPLIST_SUPPORT

#define PCI_STATUS_CAPLIST_SUPPORT   0x00100000

Definition at line 101 of file pcireg.h.

◆ PCI_STATUS_DEVSEL_FAST

#define PCI_STATUS_DEVSEL_FAST   0x00000000

Definition at line 106 of file pcireg.h.

◆ PCI_STATUS_DEVSEL_MASK

#define PCI_STATUS_DEVSEL_MASK   0x06000000

Definition at line 109 of file pcireg.h.

◆ PCI_STATUS_DEVSEL_MEDIUM

#define PCI_STATUS_DEVSEL_MEDIUM   0x02000000

Definition at line 107 of file pcireg.h.

◆ PCI_STATUS_DEVSEL_SLOW

#define PCI_STATUS_DEVSEL_SLOW   0x04000000

Definition at line 108 of file pcireg.h.

◆ PCI_STATUS_MASK

#define PCI_STATUS_MASK   0xffff

Definition at line 84 of file pcireg.h.

◆ PCI_STATUS_MASTER_ABORT

#define PCI_STATUS_MASTER_ABORT   0x20000000

Definition at line 112 of file pcireg.h.

◆ PCI_STATUS_MASTER_TARGET_ABORT

#define PCI_STATUS_MASTER_TARGET_ABORT   0x10000000

Definition at line 111 of file pcireg.h.

◆ PCI_STATUS_PARITY_DETECT

#define PCI_STATUS_PARITY_DETECT   0x80000000

Definition at line 114 of file pcireg.h.

◆ PCI_STATUS_PARITY_ERROR

#define PCI_STATUS_PARITY_ERROR   0x01000000

Definition at line 105 of file pcireg.h.

◆ PCI_STATUS_SHIFT

#define PCI_STATUS_SHIFT   16

Definition at line 83 of file pcireg.h.

◆ PCI_STATUS_SPECIAL_ERROR

#define PCI_STATUS_SPECIAL_ERROR   0x40000000

Definition at line 113 of file pcireg.h.

◆ PCI_STATUS_TARGET_TARGET_ABORT

#define PCI_STATUS_TARGET_TARGET_ABORT   0x08000000

Definition at line 110 of file pcireg.h.

◆ PCI_STATUS_UDF_SUPPORT

#define PCI_STATUS_UDF_SUPPORT   0x00400000

Definition at line 103 of file pcireg.h.

◆ PCI_SUBCLASS

#define PCI_SUBCLASS (   cr)    (((cr) >> PCI_SUBCLASS_SHIFT) & PCI_SUBCLASS_MASK)

Definition at line 133 of file pcireg.h.

◆ PCI_SUBCLASS_BRIDGE_CARDBUS

#define PCI_SUBCLASS_BRIDGE_CARDBUS   0x07

Definition at line 220 of file pcireg.h.

◆ PCI_SUBCLASS_BRIDGE_EISA

#define PCI_SUBCLASS_BRIDGE_EISA   0x02

Definition at line 215 of file pcireg.h.

◆ PCI_SUBCLASS_BRIDGE_HOST

#define PCI_SUBCLASS_BRIDGE_HOST   0x00

Definition at line 213 of file pcireg.h.

Referenced by DEVINIT(), and PCIINIT().

◆ PCI_SUBCLASS_BRIDGE_INFINIBAND

#define PCI_SUBCLASS_BRIDGE_INFINIBAND   0x0a

Definition at line 223 of file pcireg.h.

◆ PCI_SUBCLASS_BRIDGE_ISA

#define PCI_SUBCLASS_BRIDGE_ISA   0x01

Definition at line 214 of file pcireg.h.

Referenced by PCIINIT().

◆ PCI_SUBCLASS_BRIDGE_MC

#define PCI_SUBCLASS_BRIDGE_MC   0x03 /* XXX _MCA? */

Definition at line 216 of file pcireg.h.

◆ PCI_SUBCLASS_BRIDGE_MISC

#define PCI_SUBCLASS_BRIDGE_MISC   0x80

Definition at line 224 of file pcireg.h.

◆ PCI_SUBCLASS_BRIDGE_NUBUS

#define PCI_SUBCLASS_BRIDGE_NUBUS   0x06

Definition at line 219 of file pcireg.h.

◆ PCI_SUBCLASS_BRIDGE_PCI

#define PCI_SUBCLASS_BRIDGE_PCI   0x04

Definition at line 217 of file pcireg.h.

◆ PCI_SUBCLASS_BRIDGE_PCMCIA

#define PCI_SUBCLASS_BRIDGE_PCMCIA   0x05

Definition at line 218 of file pcireg.h.

◆ PCI_SUBCLASS_BRIDGE_RACEWAY

#define PCI_SUBCLASS_BRIDGE_RACEWAY   0x08

Definition at line 221 of file pcireg.h.

◆ PCI_SUBCLASS_BRIDGE_STPCI

#define PCI_SUBCLASS_BRIDGE_STPCI   0x09

Definition at line 222 of file pcireg.h.

◆ PCI_SUBCLASS_COMMUNICATIONS_GPIB

#define PCI_SUBCLASS_COMMUNICATIONS_GPIB   0x04

Definition at line 231 of file pcireg.h.

◆ PCI_SUBCLASS_COMMUNICATIONS_MISC

#define PCI_SUBCLASS_COMMUNICATIONS_MISC   0x80

Definition at line 233 of file pcireg.h.

◆ PCI_SUBCLASS_COMMUNICATIONS_MODEM

#define PCI_SUBCLASS_COMMUNICATIONS_MODEM   0x03

Definition at line 230 of file pcireg.h.

◆ PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL

#define PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL   0x02

Definition at line 229 of file pcireg.h.

◆ PCI_SUBCLASS_COMMUNICATIONS_PARALLEL

#define PCI_SUBCLASS_COMMUNICATIONS_PARALLEL   0x01

Definition at line 228 of file pcireg.h.

◆ PCI_SUBCLASS_COMMUNICATIONS_SERIAL

#define PCI_SUBCLASS_COMMUNICATIONS_SERIAL   0x00

Definition at line 227 of file pcireg.h.

◆ PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD

#define PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD   0x05

Definition at line 232 of file pcireg.h.

◆ PCI_SUBCLASS_CRYPTO_ENTERTAINMENT

#define PCI_SUBCLASS_CRYPTO_ENTERTAINMENT   0x10

Definition at line 296 of file pcireg.h.

◆ PCI_SUBCLASS_CRYPTO_MISC

#define PCI_SUBCLASS_CRYPTO_MISC   0x80

Definition at line 297 of file pcireg.h.

◆ PCI_SUBCLASS_CRYPTO_NETCOMP

#define PCI_SUBCLASS_CRYPTO_NETCOMP   0x00

Definition at line 295 of file pcireg.h.

◆ PCI_SUBCLASS_DASP_DPIO

#define PCI_SUBCLASS_DASP_DPIO   0x00

Definition at line 300 of file pcireg.h.

◆ PCI_SUBCLASS_DASP_MGMT

#define PCI_SUBCLASS_DASP_MGMT   0x20

Definition at line 303 of file pcireg.h.

◆ PCI_SUBCLASS_DASP_MISC

#define PCI_SUBCLASS_DASP_MISC   0x80

Definition at line 304 of file pcireg.h.

◆ PCI_SUBCLASS_DASP_SYNC

#define PCI_SUBCLASS_DASP_SYNC   0x10

Definition at line 302 of file pcireg.h.

◆ PCI_SUBCLASS_DASP_TIMEFREQ

#define PCI_SUBCLASS_DASP_TIMEFREQ   0x01

Definition at line 301 of file pcireg.h.

◆ PCI_SUBCLASS_DISPLAY_3D

#define PCI_SUBCLASS_DISPLAY_3D   0x02

Definition at line 198 of file pcireg.h.

◆ PCI_SUBCLASS_DISPLAY_MISC

#define PCI_SUBCLASS_DISPLAY_MISC   0x80

Definition at line 199 of file pcireg.h.

◆ PCI_SUBCLASS_DISPLAY_VGA

#define PCI_SUBCLASS_DISPLAY_VGA   0x00

Definition at line 196 of file pcireg.h.

Referenced by PCIINIT().

◆ PCI_SUBCLASS_DISPLAY_XGA

#define PCI_SUBCLASS_DISPLAY_XGA   0x01

Definition at line 197 of file pcireg.h.

◆ PCI_SUBCLASS_DOCK_GENERIC

#define PCI_SUBCLASS_DOCK_GENERIC   0x00

Definition at line 252 of file pcireg.h.

◆ PCI_SUBCLASS_DOCK_MISC

#define PCI_SUBCLASS_DOCK_MISC   0x80

Definition at line 253 of file pcireg.h.

◆ PCI_SUBCLASS_I2O_STANDARD

#define PCI_SUBCLASS_I2O_STANDARD   0x00

Definition at line 285 of file pcireg.h.

◆ PCI_SUBCLASS_INPUT_DIGITIZER

#define PCI_SUBCLASS_INPUT_DIGITIZER   0x01

Definition at line 245 of file pcireg.h.

◆ PCI_SUBCLASS_INPUT_GAMEPORT

#define PCI_SUBCLASS_INPUT_GAMEPORT   0x04

Definition at line 248 of file pcireg.h.

◆ PCI_SUBCLASS_INPUT_KEYBOARD

#define PCI_SUBCLASS_INPUT_KEYBOARD   0x00

Definition at line 244 of file pcireg.h.

◆ PCI_SUBCLASS_INPUT_MISC

#define PCI_SUBCLASS_INPUT_MISC   0x80

Definition at line 249 of file pcireg.h.

◆ PCI_SUBCLASS_INPUT_MOUSE

#define PCI_SUBCLASS_INPUT_MOUSE   0x02

Definition at line 246 of file pcireg.h.

◆ PCI_SUBCLASS_INPUT_SCANNER

#define PCI_SUBCLASS_INPUT_SCANNER   0x03

Definition at line 247 of file pcireg.h.

◆ PCI_SUBCLASS_MASK

#define PCI_SUBCLASS_MASK   0xff

Definition at line 132 of file pcireg.h.

◆ PCI_SUBCLASS_MASS_STORAGE_ATA

#define PCI_SUBCLASS_MASS_STORAGE_ATA   0x05

Definition at line 182 of file pcireg.h.

◆ PCI_SUBCLASS_MASS_STORAGE_FLOPPY

#define PCI_SUBCLASS_MASS_STORAGE_FLOPPY   0x02

Definition at line 179 of file pcireg.h.

◆ PCI_SUBCLASS_MASS_STORAGE_IDE

#define PCI_SUBCLASS_MASS_STORAGE_IDE   0x01

Definition at line 178 of file pcireg.h.

Referenced by PCIINIT().

◆ PCI_SUBCLASS_MASS_STORAGE_IPI

#define PCI_SUBCLASS_MASS_STORAGE_IPI   0x03

Definition at line 180 of file pcireg.h.

◆ PCI_SUBCLASS_MASS_STORAGE_MISC

#define PCI_SUBCLASS_MASS_STORAGE_MISC   0x80

Definition at line 183 of file pcireg.h.

◆ PCI_SUBCLASS_MASS_STORAGE_RAID

#define PCI_SUBCLASS_MASS_STORAGE_RAID   0x04

Definition at line 181 of file pcireg.h.

◆ PCI_SUBCLASS_MASS_STORAGE_SCSI

#define PCI_SUBCLASS_MASS_STORAGE_SCSI   0x00

Definition at line 177 of file pcireg.h.

Referenced by PCIINIT().

◆ PCI_SUBCLASS_MEMORY_FLASH

#define PCI_SUBCLASS_MEMORY_FLASH   0x01

Definition at line 209 of file pcireg.h.

◆ PCI_SUBCLASS_MEMORY_MISC

#define PCI_SUBCLASS_MEMORY_MISC   0x80

Definition at line 210 of file pcireg.h.

◆ PCI_SUBCLASS_MEMORY_RAM

#define PCI_SUBCLASS_MEMORY_RAM   0x00

Definition at line 208 of file pcireg.h.

◆ PCI_SUBCLASS_MULTIMEDIA_AUDIO

#define PCI_SUBCLASS_MULTIMEDIA_AUDIO   0x01

Definition at line 203 of file pcireg.h.

◆ PCI_SUBCLASS_MULTIMEDIA_MISC

#define PCI_SUBCLASS_MULTIMEDIA_MISC   0x80

Definition at line 205 of file pcireg.h.

◆ PCI_SUBCLASS_MULTIMEDIA_TELEPHONY

#define PCI_SUBCLASS_MULTIMEDIA_TELEPHONY   0x02

Definition at line 204 of file pcireg.h.

◆ PCI_SUBCLASS_MULTIMEDIA_VIDEO

#define PCI_SUBCLASS_MULTIMEDIA_VIDEO   0x00

Definition at line 202 of file pcireg.h.

◆ PCI_SUBCLASS_NETWORK_ATM

#define PCI_SUBCLASS_NETWORK_ATM   0x03

Definition at line 189 of file pcireg.h.

◆ PCI_SUBCLASS_NETWORK_ETHERNET

#define PCI_SUBCLASS_NETWORK_ETHERNET   0x00

Definition at line 186 of file pcireg.h.

Referenced by PCIINIT().

◆ PCI_SUBCLASS_NETWORK_FDDI

#define PCI_SUBCLASS_NETWORK_FDDI   0x02

Definition at line 188 of file pcireg.h.

◆ PCI_SUBCLASS_NETWORK_ISDN

#define PCI_SUBCLASS_NETWORK_ISDN   0x04

Definition at line 190 of file pcireg.h.

◆ PCI_SUBCLASS_NETWORK_MISC

#define PCI_SUBCLASS_NETWORK_MISC   0x80

Definition at line 193 of file pcireg.h.

◆ PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP

#define PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP   0x06

Definition at line 192 of file pcireg.h.

◆ PCI_SUBCLASS_NETWORK_TOKENRING

#define PCI_SUBCLASS_NETWORK_TOKENRING   0x01

Definition at line 187 of file pcireg.h.

◆ PCI_SUBCLASS_NETWORK_WORLDFIP

#define PCI_SUBCLASS_NETWORK_WORLDFIP   0x05

Definition at line 191 of file pcireg.h.

◆ PCI_SUBCLASS_PREHISTORIC_MISC

#define PCI_SUBCLASS_PREHISTORIC_MISC   0x00

Definition at line 173 of file pcireg.h.

◆ PCI_SUBCLASS_PREHISTORIC_VGA

#define PCI_SUBCLASS_PREHISTORIC_VGA   0x01

Definition at line 174 of file pcireg.h.

◆ PCI_SUBCLASS_PROCESSOR_386

#define PCI_SUBCLASS_PROCESSOR_386   0x00

Definition at line 256 of file pcireg.h.

◆ PCI_SUBCLASS_PROCESSOR_486

#define PCI_SUBCLASS_PROCESSOR_486   0x01

Definition at line 257 of file pcireg.h.

◆ PCI_SUBCLASS_PROCESSOR_ALPHA

#define PCI_SUBCLASS_PROCESSOR_ALPHA   0x10

Definition at line 259 of file pcireg.h.

◆ PCI_SUBCLASS_PROCESSOR_COPROC

#define PCI_SUBCLASS_PROCESSOR_COPROC   0x40

Definition at line 262 of file pcireg.h.

◆ PCI_SUBCLASS_PROCESSOR_MIPS

#define PCI_SUBCLASS_PROCESSOR_MIPS   0x30

Definition at line 261 of file pcireg.h.

◆ PCI_SUBCLASS_PROCESSOR_PENTIUM

#define PCI_SUBCLASS_PROCESSOR_PENTIUM   0x02

Definition at line 258 of file pcireg.h.

◆ PCI_SUBCLASS_PROCESSOR_POWERPC

#define PCI_SUBCLASS_PROCESSOR_POWERPC   0x20

Definition at line 260 of file pcireg.h.

◆ PCI_SUBCLASS_SATCOM_AUDIO

#define PCI_SUBCLASS_SATCOM_AUDIO   0x02

Definition at line 290 of file pcireg.h.

◆ PCI_SUBCLASS_SATCOM_DATA

#define PCI_SUBCLASS_SATCOM_DATA   0x04

Definition at line 292 of file pcireg.h.

◆ PCI_SUBCLASS_SATCOM_TV

#define PCI_SUBCLASS_SATCOM_TV   0x01

Definition at line 289 of file pcireg.h.

◆ PCI_SUBCLASS_SATCOM_VOICE

#define PCI_SUBCLASS_SATCOM_VOICE   0x03

Definition at line 291 of file pcireg.h.

◆ PCI_SUBCLASS_SERIALBUS_ACCESS

#define PCI_SUBCLASS_SERIALBUS_ACCESS   0x01

Definition at line 266 of file pcireg.h.

◆ PCI_SUBCLASS_SERIALBUS_CANBUS

#define PCI_SUBCLASS_SERIALBUS_CANBUS   0x09

Definition at line 274 of file pcireg.h.

◆ PCI_SUBCLASS_SERIALBUS_FIBER

#define PCI_SUBCLASS_SERIALBUS_FIBER   0x04 /* XXX _FIBRECHANNEL */

Definition at line 269 of file pcireg.h.

◆ PCI_SUBCLASS_SERIALBUS_FIREWIRE

#define PCI_SUBCLASS_SERIALBUS_FIREWIRE   0x00

Definition at line 265 of file pcireg.h.

◆ PCI_SUBCLASS_SERIALBUS_INFINIBAND

#define PCI_SUBCLASS_SERIALBUS_INFINIBAND   0x06

Definition at line 271 of file pcireg.h.

◆ PCI_SUBCLASS_SERIALBUS_IPMI

#define PCI_SUBCLASS_SERIALBUS_IPMI   0x07

Definition at line 272 of file pcireg.h.

◆ PCI_SUBCLASS_SERIALBUS_SERCOS

#define PCI_SUBCLASS_SERIALBUS_SERCOS   0x08

Definition at line 273 of file pcireg.h.

◆ PCI_SUBCLASS_SERIALBUS_SMBUS

#define PCI_SUBCLASS_SERIALBUS_SMBUS   0x05

Definition at line 270 of file pcireg.h.

◆ PCI_SUBCLASS_SERIALBUS_SSA

#define PCI_SUBCLASS_SERIALBUS_SSA   0x02

Definition at line 267 of file pcireg.h.

◆ PCI_SUBCLASS_SERIALBUS_USB

#define PCI_SUBCLASS_SERIALBUS_USB   0x03

Definition at line 268 of file pcireg.h.

◆ PCI_SUBCLASS_SHIFT

#define PCI_SUBCLASS_SHIFT   16

Definition at line 131 of file pcireg.h.

◆ PCI_SUBCLASS_SYSTEM_DMA

#define PCI_SUBCLASS_SYSTEM_DMA   0x01

Definition at line 237 of file pcireg.h.

◆ PCI_SUBCLASS_SYSTEM_MISC

#define PCI_SUBCLASS_SYSTEM_MISC   0x80

Definition at line 241 of file pcireg.h.

◆ PCI_SUBCLASS_SYSTEM_PCIHOTPLUG

#define PCI_SUBCLASS_SYSTEM_PCIHOTPLUG   0x04

Definition at line 240 of file pcireg.h.

◆ PCI_SUBCLASS_SYSTEM_PIC

#define PCI_SUBCLASS_SYSTEM_PIC   0x00

Definition at line 236 of file pcireg.h.

Referenced by PCIINIT().

◆ PCI_SUBCLASS_SYSTEM_RTC

#define PCI_SUBCLASS_SYSTEM_RTC   0x03

Definition at line 239 of file pcireg.h.

◆ PCI_SUBCLASS_SYSTEM_TIMER

#define PCI_SUBCLASS_SYSTEM_TIMER   0x02

Definition at line 238 of file pcireg.h.

◆ PCI_SUBCLASS_WIRELESS_BLUETOOTH

#define PCI_SUBCLASS_WIRELESS_BLUETOOTH   0x11

Definition at line 280 of file pcireg.h.

◆ PCI_SUBCLASS_WIRELESS_BROADBAND

#define PCI_SUBCLASS_WIRELESS_BROADBAND   0x12

Definition at line 281 of file pcireg.h.

◆ PCI_SUBCLASS_WIRELESS_CONSUMERIR

#define PCI_SUBCLASS_WIRELESS_CONSUMERIR   0x01

Definition at line 278 of file pcireg.h.

◆ PCI_SUBCLASS_WIRELESS_IRDA

#define PCI_SUBCLASS_WIRELESS_IRDA   0x00

Definition at line 277 of file pcireg.h.

◆ PCI_SUBCLASS_WIRELESS_MISC

#define PCI_SUBCLASS_WIRELESS_MISC   0x80

Definition at line 282 of file pcireg.h.

◆ PCI_SUBCLASS_WIRELESS_RF

#define PCI_SUBCLASS_WIRELESS_RF   0x10

Definition at line 279 of file pcireg.h.

◆ PCI_SUBSYS_ID_REG

#define PCI_SUBSYS_ID_REG   0x2c

Definition at line 407 of file pcireg.h.

◆ PCI_VENDOR

#define PCI_VENDOR (   id)    (((id) >> PCI_VENDOR_SHIFT) & PCI_VENDOR_MASK)

Definition at line 65 of file pcireg.h.

◆ PCI_VENDOR_MASK

#define PCI_VENDOR_MASK   0xffff

Definition at line 64 of file pcireg.h.

◆ PCI_VENDOR_SHIFT

#define PCI_VENDOR_SHIFT   0

Definition at line 63 of file pcireg.h.

◆ PCI_VPDRES_ISLARGE

#define PCI_VPDRES_ISLARGE (   x)    ((x) & 0x80)

Definition at line 564 of file pcireg.h.

◆ PCI_VPDRES_LARGE_NAME

#define PCI_VPDRES_LARGE_NAME (   x)    ((x) & 0x7f)

Definition at line 569 of file pcireg.h.

◆ PCI_VPDRES_SMALL_LENGTH

#define PCI_VPDRES_SMALL_LENGTH (   x)    ((x) & 0x7)

Definition at line 566 of file pcireg.h.

◆ PCI_VPDRES_SMALL_NAME

#define PCI_VPDRES_SMALL_NAME (   x)    (((x) >> 3) & 0xf)

Definition at line 567 of file pcireg.h.

◆ PCI_VPDRES_TYPE_COMPATIBLE_DEVICE_ID

#define PCI_VPDRES_TYPE_COMPATIBLE_DEVICE_ID   0x3 /* small */

Definition at line 571 of file pcireg.h.

◆ PCI_VPDRES_TYPE_END_TAG

#define PCI_VPDRES_TYPE_END_TAG   0xf /* small */

Definition at line 573 of file pcireg.h.

◆ PCI_VPDRES_TYPE_IDENTIFIER_STRING

#define PCI_VPDRES_TYPE_IDENTIFIER_STRING   0x02 /* large */

Definition at line 575 of file pcireg.h.

◆ PCI_VPDRES_TYPE_VENDOR_DEFINED

#define PCI_VPDRES_TYPE_VENDOR_DEFINED   0xe /* small */

Definition at line 572 of file pcireg.h.

◆ PCI_VPDRES_TYPE_VPD

#define PCI_VPDRES_TYPE_VPD   0x10 /* large */

Definition at line 576 of file pcireg.h.

Typedef Documentation

◆ pci_class_t

typedef u_int8_t pci_class_t

Definition at line 121 of file pcireg.h.

◆ pci_interface_t

typedef u_int8_t pci_interface_t

Definition at line 123 of file pcireg.h.

◆ pci_intr_grant_t

typedef u_int8_t pci_intr_grant_t

Definition at line 448 of file pcireg.h.

◆ pci_intr_latency_t

typedef u_int8_t pci_intr_latency_t

Definition at line 447 of file pcireg.h.

◆ pci_intr_line_t

typedef u_int8_t pci_intr_line_t

Definition at line 450 of file pcireg.h.

◆ pci_intr_pin_t

typedef u_int8_t pci_intr_pin_t

Definition at line 449 of file pcireg.h.

◆ pci_product_id_t

typedef u_int16_t pci_product_id_t

Definition at line 61 of file pcireg.h.

◆ pci_revision_t

typedef u_int8_t pci_revision_t

Definition at line 124 of file pcireg.h.

◆ pci_subclass_t

typedef u_int8_t pci_subclass_t

Definition at line 122 of file pcireg.h.

◆ pci_vendor_id_t

typedef u_int16_t pci_vendor_id_t

Definition at line 60 of file pcireg.h.

Function Documentation

◆ __attribute__()

struct pci_vpd_smallres __attribute__ ( (__packed__)  )

Variable Documentation

◆ vpd_key0

uint8_t vpd_key0

Definition at line 451 of file pcireg.h.

◆ vpd_key1

uint8_t vpd_key1

Definition at line 452 of file pcireg.h.

◆ vpd_len

uint8_t vpd_len

Definition at line 453 of file pcireg.h.

◆ vpdres_byte0

uint8_t vpdres_byte0

Definition at line 451 of file pcireg.h.

◆ vpdres_len_lsb

uint8_t vpdres_len_lsb

Definition at line 452 of file pcireg.h.

◆ vpdres_len_msb

uint8_t vpdres_len_msb

Definition at line 453 of file pcireg.h.


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