tulipreg.h Source File

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tulipreg.h
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1 /* $NetBSD: tulipreg.h,v 1.31 2005/06/23 23:51:42 rpaulo Exp $ */
2 
3 #ifndef __volatile
4 #define __volatile
5 #endif
6 
7 /*-
8  * Copyright (c) 1999, 2000 The NetBSD Foundation, Inc.
9  * All rights reserved.
10  *
11  * This code is derived from software contributed to The NetBSD Foundation
12  * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
13  * NASA Ames Research Center.
14  *
15  * Redistribution and use in source and binary forms, with or without
16  * modification, are permitted provided that the following conditions
17  * are met:
18  * 1. Redistributions of source code must retain the above copyright
19  * notice, this list of conditions and the following disclaimer.
20  * 2. Redistributions in binary form must reproduce the above copyright
21  * notice, this list of conditions and the following disclaimer in the
22  * documentation and/or other materials provided with the distribution.
23  * 3. All advertising materials mentioning features or use of this software
24  * must display the following acknowledgement:
25  * This product includes software developed by the NetBSD
26  * Foundation, Inc. and its contributors.
27  * 4. Neither the name of The NetBSD Foundation nor the names of its
28  * contributors may be used to endorse or promote products derived
29  * from this software without specific prior written permission.
30  *
31  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
32  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
33  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
34  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
35  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
36  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
37  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
38  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
39  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
40  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
41  * POSSIBILITY OF SUCH DAMAGE.
42  */
43 
44 #ifndef _DEV_IC_TULIPREG_H_
45 #define _DEV_IC_TULIPREG_H_
46 
47 /*
48  * Register description for the Digital Semiconductor ``Tulip'' (21x4x)
49  * Ethernet controller family, and a variety of clone chips, including:
50  *
51  * - Macronix 98713, 98713A, 98715, 98715A, 98725 (PMAC):
52  *
53  * These chips are fairly straight-forward Tulip clones.
54  * The 98713 is a very close 21140A clone. It has GPR
55  * and MII media, and a GPIO facility, and uses the ISV
56  * SROM format (or, at least, should, because of the GPIO
57  * facility). The 98713A has MII, no GPIO facility, and
58  * an internal NWay block. The 98715, 98715A, and 98725
59  * have only GPR media and the NWay block. The 98715,
60  * 98715A, and 98725 support power management.
61  *
62  * The 98715AEC adds 802.3x flow Frame based Flow Control to the
63  * 98715A.
64  *
65  * - Lite-On 82C115 (PNIC II):
66  *
67  * A clone of the Macronix MX98725, with the following differences:
68  *
69  * - Wake-On-LAN support
70  * - 128-bit multicast hash table rather than the
71  * standard 512-bit hash table
72  * - 802.3x flow control
73  *
74  * - Lite-On 82C168, 82C169 (PNIC):
75  *
76  * Pretty close, with only a few minor differences:
77  *
78  * - EEPROM is accessed completely differently.
79  * - MII is accessed completely differently.
80  * - No SIO facility (due to the above two differences).
81  * - GPIO interface is different than the 21140's.
82  * - Boards that lack PHYs use the internal NWay block
83  * and transceiver.
84  *
85  * - Winbond 89C840F
86  *
87  * Less similar, but still roughly compatible (enough so
88  * that the driver can be adapted, at least):
89  *
90  * - Registers lack the pad word between them.
91  * - Instead of a setup frame, there are two station
92  * address registers and two multicast hash table
93  * registers (64-bit multicast hash table).
94  * - Only supported media interface is MII-over-SIO.
95  * - Different OPMODE register bits for various things
96  * (mostly media related).
97  *
98  * - ADMtek AL981
99  *
100  * Another pretty-close clone:
101  *
102  * - Wake-On-LAN support
103  * - Instead of a setup frame, there are two station
104  * address registers and two multicast hash table
105  * registers (64-bit multicast hash table).
106  * - 802.3x flow control
107  * - Only supported media interface is built-in PHY
108  * which is accessed through a set of special registers.
109  * - Not all registers have the pad word between them,
110  * but luckily, there are all AL981-specific registers,
111  * so this is easy to deal with.
112  *
113  * - ADMtek AN983 and AN985
114  *
115  * Similar to the ADMtek AL981, but with a few differences.
116  *
117  * - Xircom X3201-3
118  *
119  * CardBus 21143 clone, with a few differences:
120  *
121  * - No MicroWire SROM; Ethernet address must come
122  * from CIS.
123  * - Transmit buffers must also be 32-bit aligned.
124  * - The BUSMODE_SWR bit is not self-clearing.
125  * - Must include FS|LS in setup packet descriptor.
126  * - SIA is not 21143-like, and all media attachments
127  * are MII-on-SIO.
128  *
129  * - Davicom DM9102 and DM9102A
130  *
131  * Pretty similar to the 21140A, with a few differences:
132  *
133  * - Wake-On-LAN support
134  * - DM9102 has built-in 10/100 PHY on MII interface.
135  * - DM9102A has built-in 10/100 PHY on MII interface,
136  * as well as a HomePNA 1 PHY on an alternate MII
137  * interface (selected by clearing OPMODE_PS).
138  * - The chip has a bug in the transmit DMA logic,
139  * requiring that the packet be comprised of only
140  * one DMA segment.
141  * - The bus interface is buggy, and the BUSMODE register
142  * must be initialized to 0.
143  * - There seems to be an interrupt logic bug, requiring
144  * that interrupts be disabled on the chip during the
145  * interrupt handler.
146  *
147  * - ASIX AX88140
148  *
149  * 21433 clone with a few differences:
150  *
151  * - Specific broadcast bit in the OPMODE register.
152  * - Transmit buffer must be 32-bit aligned.
153  * - The BUSMODE_SWR bit is not self-clearing.
154  * - External 10BaseT PHY or 10/100 MII.
155  *
156  * Some of the clone chips have different registers, and some have
157  * different bits in the same registers. These will be denoted by
158  * PMAC, PNICII, PNIC, DM, WINB, ADM and AX in the register/bit names.
159  */
160 
161 /*
162  * Tulip buffer descriptor. Must be 4-byte aligned.
163  *
164  * Note for receive descriptors, the byte count fields must
165  * be a multiple of 4.
166  */
167 struct tulip_desc {
168  __volatile u_int32_t td_status; /* Status */
169  __volatile u_int32_t td_ctl; /* Control and Byte Counts */
170  __volatile u_int32_t td_bufaddr1; /* Buffer Address 1 */
171  __volatile u_int32_t td_bufaddr2; /* Buffer Address 2 */
172 };
173 
174 /*
175  * Descriptor Status bits common to transmit and receive.
176  */
177 #define TDSTAT_OWN 0x80000000 /* Tulip owns descriptor */
178 #define TDSTAT_ES 0x00008000 /* Error Summary */
179 
180 /*
181  * Descriptor Status bits for Receive Descriptor.
182  */
183 #define TDSTAT_Rx_FF 0x40000000 /* Filtering Fail */
184 #define TDSTAT_WINB_Rx_RCMP 0x40000000 /* Receive Complete */
185 #define TDSTAT_Rx_FL 0x3fff0000 /* Frame Length including CRC */
186 #define TDSTAT_Rx_DE 0x00004000 /* Descriptor Error */
187 #define TDSTAT_Rx_DT 0x00003000 /* Data Type */
188 #define TDSTAT_Rx_RF 0x00000800 /* Runt Frame */
189 #define TDSTAT_Rx_MF 0x00000400 /* Multicast Frame */
190 #define TDSTAT_Rx_FS 0x00000200 /* First Descriptor */
191 #define TDSTAT_Rx_LS 0x00000100 /* Last Descriptor */
192 #define TDSTAT_Rx_TL 0x00000080 /* Frame Too Long */
193 #define TDSTAT_Rx_CS 0x00000040 /* Collision Seen */
194 #define TDSTAT_Rx_RT 0x00000020 /* Frame Type */
195 #define TDSTAT_Rx_RW 0x00000010 /* Receive Watchdog */
196 #define TDSTAT_Rx_RE 0x00000008 /* Report on MII Error */
197 #define TDSTAT_Rx_DB 0x00000004 /* Dribbling Bit */
198 #define TDSTAT_Rx_CE 0x00000002 /* CRC Error */
199 #define TDSTAT_Rx_ZER 0x00000001 /* Zero (always 0) */
200 
201 #define TDSTAT_Rx_LENGTH(x) (((x) & TDSTAT_Rx_FL) >> 16)
202 
203 #define TDSTAT_Rx_DT_SR 0x00000000 /* Serial Received Frame */
204 #define TDSTAT_Rx_DT_IL 0x00001000 /* Internal Loopback Frame */
205 #define TDSTAT_Rx_DT_EL 0x00002000 /* External Loopback Frame */
206 #define TDSTAT_Rx_DT_r 0x00003000 /* Reserved */
207 
208 /*
209  * Descriptor Status bits for Transmit Descriptor.
210  */
211 #define TDSTAT_WINB_Tx_TE 0x00008000 /* Transmit Error */
212 #define TDSTAT_Tx_TO 0x00004000 /* Transmit Jabber Timeout */
213 #define TDSTAT_Tx_LO 0x00000800 /* Loss of Carrier */
214 #define TDSTAT_Tx_NC 0x00000400 /* No Carrier */
215 #define TDSTAT_Tx_LC 0x00000200 /* Late Collision */
216 #define TDSTAT_Tx_EC 0x00000100 /* Excessive Collisions */
217 #define TDSTAT_Tx_HF 0x00000080 /* Heartbeat Fail */
218 #define TDSTAT_Tx_CC 0x00000078 /* Collision Count */
219 #define TDSTAT_Tx_LF 0x00000004 /* Link Fail */
220 #define TDSTAT_Tx_UF 0x00000002 /* Underflow Error */
221 #define TDSTAT_Tx_DE 0x00000001 /* Deferred */
222 
223 #define TDSTAT_Tx_COLLISIONS(x) (((x) & TDSTAT_Tx_CC) >> 3)
224 
225 /*
226  * Descriptor Control bits common to transmit and receive.
227  */
228 #define TDCTL_SIZE1 0x000007ff /* Size of buffer 1 */
229 #define TDCTL_SIZE1_SHIFT 0
230 
231 #define TDCTL_SIZE2 0x003ff800 /* Size of buffer 2 */
232 #define TDCTL_SIZE2_SHIFT 11
233 
234 #define TDCTL_ER 0x02000000 /* End of Ring */
235 #define TDCTL_CH 0x01000000 /* Second Address Chained */
236 
237 /*
238  * Descriptor Control bits for Transmit Descriptor.
239  */
240 #define TDCTL_Tx_IC 0x80000000 /* Interrupt on Completion */
241 #define TDCTL_Tx_LS 0x40000000 /* Last Segment */
242 #define TDCTL_Tx_FS 0x20000000 /* First Segment */
243 #define TDCTL_Tx_FT1 0x10000000 /* Filtering Type 1 */
244 #define TDCTL_Tx_SET 0x08000000 /* Setup Packet */
245 #define TDCTL_Tx_AC 0x04000000 /* Add CRC Disable */
246 #define TDCTL_Tx_DPD 0x00800000 /* Disabled Padding */
247 #define TDCTL_Tx_FT0 0x00400000 /* Filtering Type 0 */
248 
249 /*
250  * The Tulip filter is programmed by "transmitting" a Setup Packet
251  * (indicated by TDCTL_Tx_SET). The filtering type is indicated
252  * as follows:
253  *
254  * FT1 FT0 Description
255  * --- --- -----------
256  * 0 0 Perfect Filtering: The Tulip interprets the
257  * descriptor buffer as a table of 16 MAC addresses
258  * that the Tulip should receive.
259  *
260  * 0 1 Hash Filtering: The Tulip interprets the
261  * descriptor buffer as a 512-bit hash table
262  * plus one perfect address. If the incoming
263  * address is Multicast, the hash table filters
264  * the address, else the address is filtered by
265  * the perfect address.
266  *
267  * 1 0 Inverse Filtering: Like Perfect Filtering, except
268  * the table is addresses that the Tulip does NOT
269  * receive.
270  *
271  * 1 1 Hash-only Filtering: Like Hash Filtering, but
272  * physical addresses are matched by the hash table
273  * as well, and not by matching a single perfect
274  * address.
275  *
276  * A Setup Packet must always be 192 bytes long. The Tulip can store
277  * 16 MAC addresses. If not all 16 are specified in Perfect Filtering
278  * or Inverse Filtering mode, then unused entries should duplicate
279  * one of the valid entries.
280  */
281 #define TDCTL_Tx_FT_PERFECT 0
282 #define TDCTL_Tx_FT_HASH TDCTL_Tx_FT0
283 #define TDCTL_Tx_FT_INVERSE TDCTL_Tx_FT1
284 #define TDCTL_Tx_FT_HASHONLY (TDCTL_Tx_FT1|TDCTL_Tx_FT0)
285 
286 #define TULIP_SETUP_PACKET_LEN 192
287 #define TULIP_MAXADDRS 16
288 #define TULIP_MCHASHSIZE 512
289 #define TULIP_PNICII_HASHSIZE 128
290 
291 /*
292  * Maximum size of a Tulip Ethernet Address ROM or SROM.
293  */
294 #define TULIP_ROM_SIZE(bits) (2 << (bits))
295 #define TULIP_MAX_ROM_SIZE 512
296 
297 /*
298  * Format of the standard Tulip SROM information:
299  *
300  * Byte offset Size Usage
301  * 0 18 reserved
302  * 18 1 SROM Format Version
303  * 19 1 Chip Count
304  * 20 6 IEEE Network Address
305  * 26 1 Chip 0 Device Number
306  * 27 2 Chip 0 Info Leaf Offset
307  * 29 1 Chip 1 Device Number
308  * 30 2 Chip 1 Info Leaf Offset
309  * 32 1 Chip 2 Device Number
310  * 33 2 Chip 2 Info Leaf Offset
311  * ... 1 Chip n Device Number
312  * ... 2 Chip n Info Leaf Offset
313  * ... ... ...
314  * Chip Info Leaf Information
315  * ...
316  * ...
317  * ...
318  * 126 2 CRC32 checksum
319  */
320 #define TULIP_ROM_SROM_FORMAT_VERION 18 /* B */
321 #define TULIP_ROM_CHIP_COUNT 19 /* B */
322 #define TULIP_ROM_IEEE_NETWORK_ADDRESS 20
323 #define TULIP_ROM_CHIPn_DEVICE_NUMBER(n) (26 + ((n) * 3))/* B */
324 #define TULIP_ROM_CHIPn_INFO_LEAF_OFFSET(n) (27 + ((n) * 3))/* W */
325 #define TULIP_ROM_CRC32_CHECKSUM 126 /* W */
326 #define TULIP_ROM_CRC32_CHECKSUM1 94 /* W */
327 
328 #define TULIP_ROM_IL_SELECT_CONN_TYPE 0 /* W */
329 #define TULIP_ROM_IL_MEDIA_COUNT 2 /* B */
330 #define TULIP_ROM_IL_MEDIAn_BLOCK_BASE 3
331 
332 #define SELECT_CONN_TYPE_TP 0x0000
333 #define SELECT_CONN_TYPE_BNC 0x0001
334 #define SELECT_CONN_TYPE_AUI 0x0002
335 #define SELECT_CONN_TYPE_100TX 0x0003
336 #define SELECT_CONN_TYPE_100T4 0x0006
337 #define SELECT_CONN_TYPE_100FX 0x0007
338 #define SELECT_CONN_TYPE MII_10T 0x0009
339 #define SELECT_CONN_TYPE_MII_100TX 0x000d
340 #define SELECT_CONN_TYPE_MII_100T4 0x000f
341 #define SELECT_CONN_TYPE_MII_100FX 0x0010
342 #define SELECT_CONN_TYPE_TP_AUTONEG 0x0100
343 #define SELECT_CONN_TYPE_TP_FDX 0x0204
344 #define SELECT_CONN_TYPE_MII_10T_FDX 0x020a
345 #define SELECT_CONN_TYPE_100TX_FDX 0x020e
346 #define SELECT_CONN_TYPE_MII_100TX_FDX 0x0211
347 #define SELECT_CONN_TYPE_TP_NOLINKPASS 0x0400
348 #define SELECT_CONN_TYPE_ASENSE 0x0800
349 #define SELECT_CONN_TYPE_ASENSE_POWERUP 0x8800
350 #define SELECT_CONN_TYPE_ASENSE_AUTONEG 0x0900
351 
352 #define TULIP_ROM_MB_MEDIA_CODE 0x3f
353 #define TULIP_ROM_MB_MEDIA_TP 0x00
354 #define TULIP_ROM_MB_MEDIA_BNC 0x01
355 #define TULIP_ROM_MB_MEDIA_AUI 0x02
356 #define TULIP_ROM_MB_MEDIA_100TX 0x03
357 #define TULIP_ROM_MB_MEDIA_TP_FDX 0x04
358 #define TULIP_ROM_MB_MEDIA_100TX_FDX 0x05
359 #define TULIP_ROM_MB_MEDIA_100T4 0x06
360 #define TULIP_ROM_MB_MEDIA_100FX 0x07
361 #define TULIP_ROM_MB_MEDIA_100FX_FDX 0x08
362 
363 #define TULIP_ROM_MB_EXT 0x40
364 
365 #define TULIP_ROM_MB_CSR13 1 /* W */
366 #define TULIP_ROM_MB_CSR14 3 /* W */
367 #define TULIP_ROM_MB_CSR15 5 /* W */
368 
369 #define TULIP_ROM_MB_SIZE(mc) (((mc) & TULIP_ROM_MB_EXT) ? 7 : 1)
370 
371 #define TULIP_ROM_MB_NOINDICATOR 0x8000
372 #define TULIP_ROM_MB_DEFAULT 0x4000
373 #define TULIP_ROM_MB_POLARITY 0x0080
374 #define TULIP_ROM_MB_OPMODE(x) (((x) & 0x71) << 18)
375 #define TULIP_ROM_MB_BITPOS(x) (1 << (((x) & 0x0e) >> 1))
376 
377 #define TULIP_ROM_MB_21140_GPR 0 /* 21140[A] GPR block */
378 #define TULIP_ROM_MB_21140_MII 1 /* 21140[A] MII block */
379 #define TULIP_ROM_MB_21142_SIA 2 /* 2114[23] SIA block */
380 #define TULIP_ROM_MB_21142_MII 3 /* 2114[23] MII block */
381 #define TULIP_ROM_MB_21143_SYM 4 /* 21143 SYM block */
382 #define TULIP_ROM_MB_21143_RESET 5 /* 21143 reset block */
383 
384 #define TULIP_ROM_GETW(data, off) ((uint32_t)(data)[(off)] | \
385  (uint32_t)((data)[(off) + 1]) << 8)
386 
387 /*
388  * Tulip control registers.
389  */
390 
391 #define TULIP_CSR0 0x00
392 #define TULIP_CSR1 0x08
393 #define TULIP_CSR2 0x10
394 #define TULIP_CSR3 0x18
395 #define TULIP_CSR4 0x20
396 #define TULIP_CSR5 0x28
397 #define TULIP_CSR6 0x30
398 #define TULIP_CSR7 0x38
399 #define TULIP_CSR8 0x40
400 #define TULIP_CSR9 0x48
401 #define TULIP_CSR10 0x50
402 #define TULIP_CSR11 0x58
403 #define TULIP_CSR12 0x60
404 #define TULIP_CSR13 0x68
405 #define TULIP_CSR14 0x70
406 #define TULIP_CSR15 0x78
407 #define TULIP_CSR16 0x80
408 #define TULIP_CSR17 0x88
409 #define TULIP_CSR18 0x90
410 #define TULIP_CSR19 0x98
411 #define TULIP_CSR20 0xa0
412 #define TULIP_CSR21 0xa8
413 #define TULIP_CSR22 0xb0
414 #define TULIP_CSR23 0xb8
415 #define TULIP_CSR24 0xc0
416 #define TULIP_CSR25 0xc8
417 #define TULIP_CSR26 0xd0
418 #define TULIP_CSR27 0xd8
419 #define TULIP_CSR28 0xe0
420 #define TULIP_CSR29 0xe8
421 #define TULIP_CSR30 0xf0
422 #define TULIP_CSR31 0xf8
423 
424 #define TULIP_CSR_INDEX(csr) ((csr) >> 3)
425 
426 /* CSR0 - Bus Mode */
427 #define CSR_BUSMODE TULIP_CSR0
428 #define BUSMODE_SWR 0x00000001 /* software reset */
429 #define BUSMODE_BAR 0x00000002 /* bus arbitration */
430 #define BUSMODE_DSL 0x0000007c /* descriptor skip length */
431 #define BUSMODE_BLE 0x00000080 /* big endian */
432  /* programmable burst length */
433 #define BUSMODE_PBL_DEFAULT 0x00000000 /* default value */
434 #define BUSMODE_PBL_1LW 0x00000100 /* 1 longword */
435 #define BUSMODE_PBL_2LW 0x00000200 /* 2 longwords */
436 #define BUSMODE_PBL_4LW 0x00000400 /* 4 longwords */
437 #define BUSMODE_PBL_8LW 0x00000800 /* 8 longwords */
438 #define BUSMODE_PBL_16LW 0x00001000 /* 16 longwords */
439 #define BUSMODE_PBL_32LW 0x00002000 /* 32 longwords */
440  /* cache alignment */
441 #define BUSMODE_CAL_NONE 0x00000000 /* no alignment */
442 #define BUSMODE_CAL_8LW 0x00004000 /* 8 longwords */
443 #define BUSMODE_CAL_16LW 0x00008000 /* 16 longwords */
444 #define BUSMODE_CAL_32LW 0x0000c000 /* 32 longwords */
445 #define BUSMODE_DAS 0x00010000 /* diagnostic address space */
446  /* must be zero on most */
447  /* transmit auto-poll */
448  /*
449  * Transmit auto-polling not supported on:
450  * Winbond 89C040F
451  * Xircom X3201-3
452  * Davicom DM9102 (buggy BUSMODE register)
453  * ASIX AX88140
454  */
455 #define BUSMODE_TAP_NONE 0x00000000 /* no auto-polling */
456 #define BUSMODE_TAP_200us 0x00020000 /* 200 uS */
457 #define BUSMODE_TAP_800us 0x00040000 /* 400 uS */
458 #define BUSMODE_TAP_1_6ms 0x00060000 /* 1.6 mS */
459 #define BUSMODE_TAP_12_8us 0x00080000 /* 12.8 uS (21041+) */
460 #define BUSMODE_TAP_25_6us 0x000a0000 /* 25.6 uS (21041+) */
461 #define BUSMODE_TAP_51_2us 0x000c0000 /* 51.2 uS (21041+) */
462 #define BUSMODE_TAP_102_4us 0x000e0000 /* 102.4 uS (21041+) */
463 #define BUSMODE_DBO 0x00100000 /* desc-only b/e (21041+) */
464 #define BUSMODE_RME 0x00200000 /* rd/mult enab (21140+) */
465 #define BUSMODE_WINB_WAIT 0x00200000 /* wait state insertion */
466 #define BUSMODE_RLE 0x00800000 /* rd/line enab (21140+) */
467 #define BUSMODE_WLE 0x01000000 /* wt/line enab (21140+) */
468 #define BUSMODE_PNIC_MBO 0x04000000 /* magic `must be one' bit */
469  /* on Lite-On PNIC */
470 
471 
472 /* CSR1 - Transmit Poll Demand */
473 #define CSR_TXPOLL TULIP_CSR1
474 #define TXPOLL_TPD 0x00000001 /* transmit poll demand */
475 
476 
477 /* CSR2 - Receive Poll Demand */
478 #define CSR_RXPOLL TULIP_CSR2
479 #define RXPOLL_RPD 0x00000001 /* receive poll demand */
480 
481 
482 /* CSR3 - Receive List Base Address */
483 #define CSR_RXLIST TULIP_CSR3
484 
485 /* CSR4 - Transmit List Base Address */
486 #define CSR_TXLIST TULIP_CSR4
487 
488 /* CSR5 - Status */
489 #define CSR_STATUS TULIP_CSR5
490 #define STATUS_TI 0x00000001 /* transmit interrupt */
491 #define STATUS_TPS 0x00000002 /* transmit process stopped */
492 #define STATUS_TU 0x00000004 /* transmit buffer unavail */
493 #define STATUS_TJT 0x00000008 /* transmit jabber timeout */
494 #define STATUS_WINB_REI 0x00000008 /* receive early interrupt */
495 #define STATUS_LNPANC 0x00000010 /* link pass (21041) */
496 #define STATUS_WINB_RERR 0x00000010 /* receive error */
497 #define STATUS_UNF 0x00000020 /* transmit underflow */
498 #define STATUS_RI 0x00000040 /* receive interrupt */
499 #define STATUS_RU 0x00000080 /* receive buffer unavail */
500 #define STATUS_RPS 0x00000100 /* receive process stopped */
501 #define STATUS_RWT 0x00000200 /* receive watchdog timeout */
502 #define STATUS_AT 0x00000400 /* SIA AUI/TP pin changed
503  (21040) */
504 #define STATUS_ETI 0x00000400 /* early transmit interrupt
505  (21142/PMAC/Winbond) */
506 #define STATUS_FD 0x00000800 /* full duplex short frame
507  received (21040) */
508 #define STATUS_TM 0x00000800 /* timer expired (21041) */
509 #define STATUS_LNF 0x00001000 /* link fail (21040) */
510 #define STATUS_SE 0x00002000 /* system error */
511 #define STATUS_ER 0x00004000 /* early receive (21041) */
512 #define STATUS_AIS 0x00008000 /* abnormal interrupt summary */
513 #define STATUS_NIS 0x00010000 /* normal interrupt summary */
514 #define STATUS_RS 0x000e0000 /* receive process state */
515 #define STATUS_RS_STOPPED 0x00000000 /* Stopped */
516 #define STATUS_RS_FETCH 0x00020000 /* Running - fetch receive
517  descriptor */
518 #define STATUS_RS_CHECK 0x00040000 /* Running - check for end
519  of receive */
520 #define STATUS_RS_WAIT 0x00060000 /* Running - wait for packet */
521 #define STATUS_RS_SUSPENDED 0x00080000 /* Suspended */
522 #define STATUS_RS_CLOSE 0x000a0000 /* Running - close receive
523  descriptor */
524 #define STATUS_RS_FLUSH 0x000c0000 /* Running - flush current
525  frame from FIFO */
526 #define STATUS_RS_QUEUE 0x000e0000 /* Running - queue current
527  frame from FIFO into
528  buffer */
529 #define STATUS_DM_RS_STOPPED 0x00000000 /* Stopped */
530 #define STATUS_DM_RS_FETCH 0x00020000 /* Running - fetch receive
531  descriptor */
532 #define STATUS_DM_RS_WAIT 0x00040000 /* Running - wait for packet */
533 #define STATUS_DM_RS_QUEUE 0x00060000 /* Running - queue current
534  frame from FIFO into
535  buffer */
536 #define STATUS_DM_RS_CLOSE_OWN 0x00080000 /* Running - close receive
537  descriptor, clear own */
538 #define STATUS_DM_RS_CLOSE_ST 0x000a0000 /* Running - close receive
539  descriptor, write status */
540 #define STATUS_DM_RS_SUSPENDED 0x000c0000 /* Suspended */
541 #define STATUS_DM_RS_FLUSH 0x000e0000 /* Running - flush current
542  frame from FIFO */
543 #define STATUS_TS 0x00700000 /* transmit process state */
544 #define STATUS_TS_STOPPED 0x00000000 /* Stopped */
545 #define STATUS_TS_FETCH 0x00100000 /* Running - fetch transmit
546  descriptor */
547 #define STATUS_TS_WAIT 0x00200000 /* Running - wait for end
548  of transmission */
549 #define STATUS_TS_READING 0x00300000 /* Running - read buffer from
550  memory and queue into
551  FIFO */
552 #define STATUS_TS_RESERVED 0x00400000 /* RESERVED */
553 #define STATUS_TS_SETUP 0x00500000 /* Running - Setup packet */
554 #define STATUS_TS_SUSPENDED 0x00600000 /* Suspended */
555 #define STATUS_TS_CLOSE 0x00700000 /* Running - close transmit
556  descriptor */
557 #define STATUS_DM_TS_STOPPED 0x00000000 /* Stopped */
558 #define STATUS_DM_TS_FETCH 0x00100000 /* Running - fetch transmit
559  descriptor */
560 #define STATUS_DM_TS_SETUP 0x00200000 /* Running - Setup packet */
561 #define STATUS_DM_TS_READING 0x00300000 /* Running - read buffer from
562  memory and queue into
563  FIFO */
564 #define STATUS_DM_TS_CLOSE_OWN 0x00400000 /* Running - close transmit
565  descriptor, clear own */
566 #define STATUS_DM_TS_WAIT 0x00500000 /* Running - wait for end
567  of transmission */
568 #define STATUS_DM_TS_CLOSE_ST 0x00600000 /* Running - close transmit
569  descriptor, write status */
570 #define STATUS_DM_TS_SUSPENDED 0x00700000 /* Suspended */
571 #define STATUS_EB 0x03800000 /* error bits */
572 #define STATUS_EB_PARITY 0x00000000 /* parity errror */
573 #define STATUS_EB_MABT 0x00800000 /* master abort */
574 #define STATUS_EB_TABT 0x01000000 /* target abort */
575 #define STATUS_GPPI 0x04000000 /* GPIO interrupt (21142) */
576 #define STATUS_PNIC_TXABORT 0x04000000 /* transmit aborted */
577 #define STATUS_LC 0x08000000 /* 100baseTX link change
578  (21142/PMAC) */
579 #define STATUS_PMAC_WKUPI 0x10000000 /* wake up event */
580 #define STATUS_X3201_PMEIS 0x10000000 /* power management event
581  interrupt summary */
582 #define STATUS_X3201_SFIS 0x80000000 /* second function (Modem)
583  interrupt status */
584 
585 
586 /* CSR6 - Operation Mode */
587 #define CSR_OPMODE TULIP_CSR6
588 #define OPMODE_HP 0x00000001 /* hash/perfect mode (ro) */
589 #define OPMODE_SR 0x00000002 /* start receive */
590 #define OPMODE_HO 0x00000004 /* hash only mode (ro) */
591 #define OPMODE_PB 0x00000008 /* pass bad frames */
592 #define OPMODE_WINB_APP 0x00000008 /* accept all physcal packet */
593 #define OPMODE_IF 0x00000010 /* inverse filter mode (ro) */
594 #define OPMODE_WINB_AMP 0x00000010 /* accept multicast packet */
595 #define OPMODE_SB 0x00000020 /* start backoff counter */
596 #define OPMODE_WINB_ABP 0x00000020 /* accept broadcast packet */
597 #define OPMODE_PR 0x00000040 /* promiscuous mode */
598 #define OPMODE_WINB_ARP 0x00000040 /* accept runt packet */
599 #define OPMODE_PM 0x00000080 /* pass all multicast */
600 #define OPMODE_WINB_AEP 0x00000080 /* accept error packet */
601 #define OPMODE_FKD 0x00000100 /* flaky oscillator disable */
602 #define OPMODE_AX_RB 0x00000100 /* recieve broadcast packets */
603 #define OPMODE_FD 0x00000200 /* full-duplex mode */
604 #define OPMODE_OM 0x00000c00 /* operating mode */
605 #define OPMODE_OM_NORMAL 0x00000000 /* normal mode */
606 #define OPMODE_OM_INTLOOP 0x00000400 /* internal loopback */
607 #define OPMODE_OM_EXTLOOP 0x00000800 /* external loopback */
608 #define OPMODE_FC 0x00001000 /* force collision */
609 #define OPMODE_ST 0x00002000 /* start transmitter */
610 #define OPMODE_TR 0x0000c000 /* threshold control */
611 #define OPMODE_TR_72 0x00000000 /* 72 bytes */
612 #define OPMODE_TR_96 0x00004000 /* 96 bytes */
613 #define OPMODE_TR_128 0x00008000 /* 128 bytes */
614 #define OPMODE_TR_160 0x0000c000 /* 160 bytes */
615 #define OPMODE_WINB_TTH 0x001fc000 /* transmit threshold */
616 #define OPMODE_WINB_TTH_SHIFT 14
617 #define OPMODE_BP 0x00010000 /* backpressure enable */
618 #define OPMODE_CA 0x00020000 /* capture effect enable */
619 #define OPMODE_PNIC_TBEN 0x00020000 /* Tx backoff offset enable */
620  /*
621  * On Davicom DM9102, OPMODE_PS and OPMODE_HBD must
622  * always be set.
623  */
624 #define OPMODE_PS 0x00040000 /* port select:
625  1 = MII/SYM, 0 = SRL
626  (21140) */
627 #define OPMODE_HBD 0x00080000 /* heartbeat disable:
628  set in MII/SYM 100mbps,
629  set according to PHY
630  in MII 10mbps mode
631  (21140) */
632 #define OPMODE_PNIC_IT 0x00100000 /* immediate transmit */
633 #define OPMODE_SF 0x00200000 /* store and forward mode
634  (21140) */
635 #define OPMODE_WINB_REIT 0x1fe00000 /* receive eartly intr thresh */
636 #define OPMODE_WINB_REIT_SHIFT 21
637 #define OPMODE_TTM 0x00400000 /* Transmit Threshold Mode:
638  1 = 10mbps, 0 = 100mbps
639  (21140) */
640 #define OPMODE_PCS 0x00800000 /* PCS function (21140) */
641 #define OPMODE_SCR 0x01000000 /* scrambler mode (21140) */
642 #define OPMODE_MBO 0x02000000 /* must be one (21140,
643  DM9102) */
644 #define OPMODE_IDAMSB 0x04000000 /* ignore dest addr MSB
645  (21142) */
646 #define OPMODE_PNIC_DRC 0x20000000 /* don't include CRC in Rx
647  frames (PNIC) */
648 #define OPMODE_WINB_FES 0x20000000 /* fast ethernet select */
649 #define OPMODE_RA 0x40000000 /* receive all (21140) */
650 #define OPMODE_PNIC_EED 0x40000000 /* 1 == ext, 0 == int ENDEC
651  (PNIC) */
652 #define OPMODE_WINB_TEIO 0x40000000 /* transmit early intr on */
653 #define OPMODE_SC 0x80000000 /* special capture effect
654  enable (21041+) */
655 #define OPMODE_WINB_REIO 0x80000000 /* receive early intr on */
656 
657 /* Shorthand for media-related OPMODE bits */
658 #define OPMODE_MEDIA_BITS (OPMODE_FD|OPMODE_PS|OPMODE_TTM|OPMODE_PCS|OPMODE_SCR)
659 
660 /* CSR7 - Interrupt Enable */
661 #define CSR_INTEN TULIP_CSR7
662  /* See bits for CSR5 -- Status */
663 
664 
665 /* CSR8 - Missed Frames */
666 #define CSR_MISSED TULIP_CSR8
667 #define MISSED_MFC 0x0000ffff /* missed packet count */
668 #define MISSED_MFO 0x00010000 /* missed packet count
669  overflowed */
670 #define MISSED_FOC 0x0ffe0000 /* fifo overflow counter
671  (21140) */
672 #define MISSED_OCO 0x10000000 /* overflow counter overflowed
673  (21140) */
674 
675 #define MISSED_GETMFC(x) ((x) & MISSED_MFC)
676 #define MISSED_GETFOC(x) (((x) & MISSED_FOC) >> 17)
677 
678 
679 /* CSR9 - MII, SROM, Boot ROM, Ethernet Address ROM register. */
680 #define CSR_MIIROM TULIP_CSR9
681 #define MIIROM_DATA 0x000000ff /* byte of data from
682  Ethernet Address ROM
683  (21040), byte of data
684  to/from Boot ROM (21041+) */
685 #define MIIROM_SROMCS 0x00000001 /* SROM chip select */
686 #define MIIROM_SROMSK 0x00000002 /* SROM clock */
687 #define MIIROM_SROMDI 0x00000004 /* SROM data in (to) */
688 #define MIIROM_SROMDO 0x00000008 /* SROM data out (from) */
689 #define MIIROM_REG 0x00000400 /* external register select */
690 #define MIIROM_SR 0x00000800 /* SROM select */
691 #define MIIROM_BR 0x00001000 /* boot ROM select */
692 #define MIIROM_WR 0x00002000 /* write to boot ROM */
693 #define MIIROM_RD 0x00004000 /* read from boot ROM */
694 #define MIIROM_MOD 0x00008000 /* mode select (ro) (21041) */
695 #define MIIROM_MDC 0x00010000 /* MII clock */
696 #define MIIROM_MDO 0x00020000 /* MII data out */
697 #define MIIROM_MIIDIR 0x00040000 /* MII direction mode
698  1 = PHY in read,
699  0 = PHY in write */
700 #define MIIROM_MDI 0x00080000 /* MII data in */
701 #define MIIROM_DN 0x80000000 /* data not valid (21040) */
702 
703 #define MIIROM_PMAC_LED0SEL 0x10000000 /* 0 == LED0 activity (def)
704  1 == LED0 speed */
705 #define MIIROM_PMAC_LED1SEL 0x20000000 /* 0 == LED1 link (def)
706  1 == LED1 link/act */
707 #define MIIROM_PMAC_LED2SEL 0x40000000 /* 0 == LED2 speed (def)
708  1 == LED2 collision */
709 #define MIIROM_PMAC_LED3SEL 0x80000000 /* 0 == LED3 receive (def)
710  1 == LED3 full duplex */
711 
712  /* SROM opcodes */
713 #define TULIP_SROM_OPC_ERASE 0x04
714 #define TULIP_SROM_OPC_WRITE 0x05
715 #define TULIP_SROM_OPC_READ 0x06
716 
717  /* The Lite-On PNIC does this completely differently */
718 #define PNIC_MIIROM_DATA 0x0000ffff /* mask of data bits ??? */
719 #define PNIC_MIIROM_BUSY 0x80000000 /* EEPROM is busy */
720 
721 
722 /* CSR10 - Boot ROM address register (21041+). */
723 #define CSR_ROMADDR TULIP_CSR10
724 #define ROMADDR_MASK 0x000003ff /* boot rom address */
725 
726 
727 /* CSR11 - General Purpose Timer (21041+). */
728 #define CSR_GPT TULIP_CSR11
729 #define GPT_VALUE 0x0000ffff /* timer value */
730 #define GPT_CON 0x00010000 /* continuous mode */
731  /* 21143-PD and 21143-TD Interrupt Mitigation bits */
732 #define GPT_NRX 0x000e0000 /* number of Rx packets */
733 #define GPT_RXT 0x00f00000 /* Rx timer */
734 #define GPT_NTX 0x07000000 /* number of Tx packets */
735 #define GPT_TXT 0x78000000 /* Tx timer */
736 #define GPT_CYCLE 0x80000000 /* cycle size */
737 
738 
739 /* CSR12 - SIA Status Register. */
740 #define CSR_SIASTAT TULIP_CSR12
741 #define SIASTAT_PAUI 0x00000001 /* pin AUI/TP indication
742  (21040) */
743 #define SIASTAT_MRA 0x00000001 /* MII receive activity
744  (21142) */
745 #define SIASTAT_NCR 0x00000002 /* network connection error */
746 #define SIASTAT_LS100 0x00000002 /* 100baseT link status
747  0 == pass (21142) */
748 #define SIASTAT_LKF 0x00000004 /* link fail status */
749 #define SIASTAT_LS10 0x00000004 /* 10baseT link status
750  0 == pass (21142) */
751 #define SIASTAT_APS 0x00000008 /* auto polarity status */
752 #define SIASTAT_DSD 0x00000010 /* PLL self test done */
753 #define SIASTAT_DSP 0x00000020 /* PLL self test pass */
754 #define SIASTAT_DAZ 0x00000040 /* PLL all zero */
755 #define SIASTAT_DAO 0x00000080 /* PLL all one */
756 #define SIASTAT_SRA 0x00000100 /* selected port receive
757  activity (21041) */
758 #define SIASTAT_ARA 0x00000100 /* AUI receive activity
759  (21142) */
760 #define SIASTAT_NRA 0x00000200 /* non-selected port
761  receive activity (21041) */
762 #define SIASTAT_TRA 0x00000200 /* 10base-T receive activity
763  (21142) */
764 #define SIASTAT_NSN 0x00000400 /* non-stable NLPs detected
765  (21041) */
766 #define SIASTAT_TRF 0x00000800 /* transmit remote fault
767  (21041) */
768 #define SIASTAT_ANS 0x00007000 /* autonegotiation state
769  (21041) */
770 #define SIASTAT_ANS_DIS 0x00000000 /* disabled */
771 #define SIASTAT_ANS_TXDIS 0x00001000 /* transmit disabled */
772 #define SIASTAT_ANS_START 0x00001000 /* (MX98715AEC) */
773 #define SIASTAT_ANS_ABD 0x00002000 /* ability detect */
774 #define SIASTAT_ANS_ACKD 0x00003000 /* acknowledge detect */
775 #define SIASTAT_ANS_ACKC 0x00004000 /* complete acknowledge */
776 #define SIASTAT_ANS_FLPGOOD 0x00005000 /* FLP link good */
777 #define SIASTAT_ANS_LINKCHECK 0x00006000 /* link check */
778 #define SIASTAT_LPN 0x00008000 /* link partner negotiable
779  (21041) */
780 #define SIASTAT_LPC 0xffff0000 /* link partner code word */
781 
782 #define SIASTAT_GETLPC(x) (((x) & SIASTAT_LPC) >> 16)
783 
784 
785 /* CSR13 - SIA Connectivity Register. */
786 #define CSR_SIACONN TULIP_CSR13
787 #define SIACONN_SRL 0x00000001 /* SIA reset
788  (0 == reset) */
789 #define SIACONN_PS 0x00000002 /* pin AUI/TP selection
790  (21040) */
791 #define SIACONN_CAC 0x00000004 /* CSR autoconfiguration */
792 #define SIACONN_AUI 0x00000008 /* select AUI (0 = TP) */
793 #define SIACONN_EDP 0x00000010 /* SIA PLL external input
794  enable (21040) */
795 #define SIACONN_ENI 0x00000020 /* encoder input multiplexer
796  (21040) */
797 #define SIACONN_SIM 0x00000040 /* serial interface input
798  multiplexer (21040) */
799 #define SIACONN_ASE 0x00000080 /* APLL start enable
800  (21040) */
801 #define SIACONN_SEL 0x00000f00 /* external port output
802  multiplexer select
803  (21040) */
804 #define SIACONN_IE 0x00001000 /* input enable (21040) */
805 #define SIACONN_OE1_3 0x00002000 /* output enable 1, 3
806  (21040) */
807 #define SIACONN_OE2_4 0x00004000 /* output enable 2, 4
808  (21040) */
809 #define SIACONN_OE5_6_7 0x00008000 /* output enable 5, 6, 7
810  (21040) */
811 #define SIACONN_SDM 0x0000ef00 /* SIA diagnostic mode;
812  always set to this value
813  for normal operation
814  (21041) */
815 
816 
817 /* CSR14 - SIA Transmit Receive Register. */
818 #define CSR_SIATXRX TULIP_CSR14
819 #define SIATXRX_ECEN 0x00000001 /* encoder enable */
820 #define SIATXRX_LBK 0x00000002 /* loopback enable */
821 #define SIATXRX_DREN 0x00000004 /* driver enable */
822 #define SIATXRX_LSE 0x00000008 /* link pulse send enable */
823 #define SIATXRX_CPEN 0x00000030 /* compensation enable */
824 #define SIATXRX_CPEN_DIS0 0x00000000 /* disabled */
825 #define SIATXRX_CPEN_DIS1 0x00000010 /* disabled */
826 #define SIATXRX_CPEN_HIGHPWR 0x00000020 /* high power */
827 #define SIATXRX_CPEN_NORMAL 0x00000030 /* normal */
828 #define SIATXRX_MBO 0x00000040 /* must be one (21041 pass 2) */
829 #define SIATXRX_TH 0x00000040 /* 10baseT HDX enable (21142) */
830 #define SIATXRX_ANE 0x00000080 /* autonegotiation enable
831  (21041/21142) */
832 #define SIATXRX_RSQ 0x00000100 /* receive squelch enable */
833 #define SIATXRX_CSQ 0x00000200 /* collision squelch enable */
834 #define SIATXRX_CLD 0x00000400 /* collision detect enable */
835 #define SIATXRX_SQE 0x00000800 /* signal quality generation
836  enable */
837 #define SIATXRX_LTE 0x00001000 /* link test enable */
838 #define SIATXRX_APE 0x00002000 /* auto-polarity enable */
839 #define SIATXRX_SPP 0x00004000 /* set polarity plus */
840 #define SIATXRX_TAS 0x00008000 /* 10base-T/AUI autosensing
841  enable (21041/21142) */
842 #define SIATXRX_THX 0x00010000 /* 100baseTX-HDX (21142) */
843 #define SIATXRX_TXF 0x00020000 /* 100baseTX-FDX (21142) */
844 #define SIATXRX_T4 0x00040000 /* 100baseT4 (21142) */
845 
846 
847 /* CSR15 - SIA General Register. */
848 #define CSR_SIAGEN TULIP_CSR15
849 #define SIAGEN_JBD 0x00000001 /* jabber disable */
850 #define SIAGEN_HUJ 0x00000002 /* host unjab */
851 #define SIAGEN_JCK 0x00000004 /* jabber clock */
852 #define SIAGEN_ABM 0x00000008 /* BNC select (21041) */
853 #define SIAGEN_RWD 0x00000010 /* receive watchdog disable */
854 #define SIAGEN_RWR 0x00000020 /* receive watchdog release */
855 #define SIAGEN_LE1 0x00000040 /* LED 1 enable (21041) */
856 #define SIAGEN_LV1 0x00000080 /* LED 1 value (21041) */
857 #define SIAGEN_TSCK 0x00000100 /* test clock */
858 #define SIAGEN_FUSQ 0x00000200 /* force unsquelch */
859 #define SIAGEN_FLF 0x00000400 /* force link fail */
860 #define SIAGEN_LSD 0x00000800 /* LED stretch disable
861  (21041) */
862 #define SIAGEN_LEE 0x00000800 /* Link extend enable (21142) */
863 #define SIAGEN_DPST 0x00001000 /* PLL self-test start */
864 #define SIAGEN_FRL 0x00002000 /* force receiver low */
865 #define SIAGEN_LE2 0x00004000 /* LED 2 enable (21041) */
866 #define SIAGEN_RMP 0x00004000 /* received magic packet
867  (21143) */
868 #define SIAGEN_LV2 0x00008000 /* LED 2 value (21041) */
869 #define SIAGEN_HCKR 0x00008000 /* hacker (21143) */
870 #define SIAGEN_MD 0x000f0000 /* general purpose mode/data */
871 #define SIAGEN_LGS0 0x00100000 /* LED/GEP 0 select */
872 #define SIAGEN_LGS1 0x00200000 /* LED/GEP 1 select */
873 #define SIAGEN_LGS2 0x00400000 /* LED/GEP 2 select */
874 #define SIAGEN_LGS3 0x00800000 /* LED/GEP 3 select */
875 #define SIAGEN_GEI0 0x01000000 /* GEP pin 0 intr enable */
876 #define SIAGEN_GEI1 0x02000000 /* GEP pin 1 intr enable */
877 #define SIAGEN_RME 0x04000000 /* receive match enable */
878 #define SIAGEN_CWE 0x08000000 /* control write enable */
879 #define SIAGEN_GI0 0x10000000 /* GEP pin 0 interrupt */
880 #define SIAGEN_GI1 0x20000000 /* GEP pin 1 interrupt */
881 #define SIAGEN_RMI 0x40000000 /* receive match interrupt */
882 
883 
884 /* CSR12 - General Purpose Port (21140+). */
885 #define CSR_GPP TULIP_CSR12
886 #define GPP_MD 0x000000ff /* general purpose mode/data */
887 #define GPP_GPC 0x00000100 /* general purpose control */
888 #define GPP_PNIC_GPD 0x0000000f /* general purpose data */
889 #define GPP_PNIC_GPC 0x000000f0 /* general purpose control */
890 
891 #define GPP_PNIC_IN(x) (1 << (x))
892 #define GPP_PNIC_OUT(x, on) (((on) << (x)) | (1 << ((x) + 4)))
893 
894 /*
895  * The Lite-On PNIC manual recommends the following for the General Purpose
896  * I/O pins:
897  *
898  * 0 Speed Relay 1 == 100mbps
899  * 1 100mbps loopback 1 == loopback
900  * 2 BNC DC-DC converter 1 == select BNC
901  * 3 Link 100 1 == 100baseTX link status
902  */
903 #define GPP_PNIC_PIN_SPEED_RLY 0
904 #define GPP_PNIC_PIN_100M_LPKB 1
905 #define GPP_PNIC_PIN_BNC_XMER 2
906 #define GPP_PNIC_PIN_LNK100X 3
907 
908 /*
909  * Definitions used for the SMC 9332DST (21140) board.
910  */
911 #define GPP_SMC9332DST_PINS 0x3f /* General Purpose Pin directions */
912 #define GPP_SMC9332DST_OK10 0x80 /* 10 Mb/sec Signal Detect gep<7> */
913 #define GPP_SMC9332DST_OK100 0x40 /* 100 Mb/sec Signal Detect gep<6> */
914 #define GPP_SMC9332DST_INIT 0x09 /* No loopback --- point-to-point */
915 
916 /*
917  * Definitions used for the Cogent EM1x0 (21140) board.
918  */
919 #define GPP_COGENT_EM1x0_PINS 0x3f /* General Purpose Pin directions */
920 #define GPP_COGENT_EM1x0_INIT 0x09 /* No loopback --- point-to-point */
921 
922 
923 /*
924  * Digital Semiconductor 21040 registers.
925  */
926 
927 /* CSR11 - Full Duplex Register */
928 #define CSR_21040_FDX TULIP_CSR11
929 #define FDX21040_FDXACV 0x0000ffff /* full duplex
930  autoconfiguration value */
931 
932 
933 /* SIA configuration for 10base-T (from the 21040 manual) */
934 #define SIACONN_21040_10BASET 0x0000ef01
935 #define SIATXRX_21040_10BASET 0x0000ffff
936 #define SIAGEN_21040_10BASET 0x00000000
937 
938 
939 /* SIA configuration for 10base-T full-duplex (from the 21040 manual) */
940 #define SIACONN_21040_10BASET_FDX 0x0000ef01
941 #define SIATXRX_21040_10BASET_FDX 0x0000fffd
942 #define SIAGEN_21040_10BASET_FDX 0x00000000
943 
944 
945 /* SIA configuration for 10base-5 (from the 21040 manual) */
946 #define SIACONN_21040_AUI 0x0000ef09
947 #define SIATXRX_21040_AUI 0x00000705
948 #define SIAGEN_21040_AUI 0x00000006
949 
950 
951 /* SIA configuration for External SIA (from the 21040 manual) */
952 #define SIACONN_21040_EXTSIA 0x00003041
953 #define SIATXRX_21040_EXTSIA 0x00000000
954 #define SIAGEN_21040_EXTSIA 0x00000006
955 
956 
957 /*
958  * Digital Semiconductor 21041 registers.
959  */
960 
961 /* SIA configuration for 10base-T (from the 21041 manual) */
962 #define SIACONN_21041_10BASET 0x0000ef01
963 #define SIATXRX_21041_10BASET 0x0000ff3f
964 #define SIAGEN_21041_10BASET 0x00000000
965 
966 #define SIACONN_21041P2_10BASET SIACONN_21041_10BASET
967 #define SIATXRX_21041P2_10BASET 0x0000ffff
968 #define SIAGEN_21041P2_10BASET SIAGEN_21041_10BASET
969 
970 
971 /* SIA configuration for 10base-T full-duplex (from the 21041 manual) */
972 #define SIACONN_21041_10BASET_FDX 0x0000ef01
973 #define SIATXRX_21041_10BASET_FDX 0x0000ff3d
974 #define SIAGEN_21041_10BASET_FDX 0x00000000
975 
976 #define SIACONN_21041P2_10BASET_FDX SIACONN_21041_10BASET_FDX
977 #define SIATXRX_21041P2_10BASET_FDX 0x0000ffff
978 #define SIAGEN_21041P2_10BASET_FDX SIAGEN_21041_10BASET_FDX
979 
980 
981 /* SIA configuration for 10base-5 (from the 21041 manual) */
982 #define SIACONN_21041_AUI 0x0000ef09
983 #define SIATXRX_21041_AUI 0x0000f73d
984 #define SIAGEN_21041_AUI 0x0000000e
985 
986 #define SIACONN_21041P2_AUI SIACONN_21041_AUI
987 #define SIATXRX_21041P2_AUI 0x0000f7fd
988 #define SIAGEN_21041P2_AUI SIAGEN_21041_AUI
989 
990 
991 /* SIA configuration for 10base-2 (from the 21041 manual) */
992 #define SIACONN_21041_BNC 0x0000ef09
993 #define SIATXRX_21041_BNC 0x0000f73d
994 #define SIAGEN_21041_BNC 0x00000006
995 
996 #define SIACONN_21041P2_BNC SIACONN_21041_BNC
997 #define SIATXRX_21041P2_BNC 0x0000f7fd
998 #define SIAGEN_21041P2_BNC SIAGEN_21041_BNC
999 
1000 
1001 /*
1002  * Digital Semiconductor 21142/21143 registers.
1003  */
1004 
1005 /* SIA configuration for 10baseT (from the 21143 manual) */
1006 #define SIACONN_21142_10BASET 0x00000001
1007 #define SIATXRX_21142_10BASET 0x00007f3f
1008 #define SIAGEN_21142_10BASET 0x00000008
1009 
1010 
1011 /* SIA configuration for 10baseT full-duplex (from the 21143 manual) */
1012 #define SIACONN_21142_10BASET_FDX 0x00000001
1013 #define SIATXRX_21142_10BASET_FDX 0x00007f3d
1014 #define SIAGEN_21142_10BASET_FDX 0x00000008
1015 
1016 
1017 /* SIA configuration for 10base5 (from the 21143 manual) */
1018 #define SIACONN_21142_AUI 0x00000009
1019 #define SIATXRX_21142_AUI 0x00004705
1020 #define SIAGEN_21142_AUI 0x0000000e
1021 
1022 
1023 /* SIA configuration for 10base2 (from the 21143 manual) */
1024 #define SIACONN_21142_BNC 0x00000009
1025 #define SIATXRX_21142_BNC 0x00004705
1026 #define SIAGEN_21142_BNC 0x00000006
1027 
1028 
1029 /*
1030  * Lite-On 82C168/82C169 registers.
1031  */
1032 
1033 /* ENDEC General Register */
1034 #define CSR_PNIC_ENDEC 0x78
1035 #define PNIC_ENDEC_JDIS 0x00000001 /* jabber disable */
1036 
1037 /* SROM Power Register */
1038 #define CSR_PNIC_SROMPWR 0x90
1039 #define PNIC_SROMPWR_MRLE 0x00000001 /* Memory-Read-Line enable */
1040 #define PNIC_SROMPWR_CB 0x00000002 /* cache boundary alignment
1041  burst type; 1 == burst to
1042  boundary, 0 == single-cycle
1043  to boundary */
1044 
1045 /* SROM Control Register */
1046 #define CSR_PNIC_SROMCTL 0x98
1047 #define PNIC_SROMCTL_addr 0x0000003f /* mask of address bits */
1048 /* XXX THESE ARE WRONG ACCORDING TO THE MANUAL! */
1049 #define PNIC_SROMCTL_READ 0x00000600 /* read command */
1050 
1051 /* MII Access Register */
1052 #define CSR_PNIC_MII 0xa0
1053 #define PNIC_MII_DATA 0x0000ffff /* mask of data bits */
1054 #define PNIC_MII_REG 0x007c0000 /* register mask */
1055 #define PNIC_MII_REGSHIFT 18
1056 #define PNIC_MII_PHY 0x0f800000 /* phy mask */
1057 #define PNIC_MII_PHYSHIFT 23
1058 #define PNIC_MII_OPCODE 0x30000000 /* opcode mask */
1059 #define PNIC_MII_RESERVED 0x00020000 /* must be one/must be zero;
1060  2 bits are described here */
1061 #define PNIC_MII_MBO 0x40000000 /* must be one */
1062 #define PNIC_MII_BUSY 0x80000000 /* MII is busy */
1063 
1064 #define PNIC_MII_WRITE 0x10000000 /* write PHY command */
1065 #define PNIC_MII_READ 0x20000000 /* read PHY command */
1066 
1067 /* NWAY Register */
1068 #define CSR_PNIC_NWAY 0xb8
1069 #define PNIC_NWAY_RS 0x00000001 /* reset NWay block */
1070 #define PNIC_NWAY_PD 0x00000002 /* power down NWay block */
1071 #define PNIC_NWAY_BX 0x00000004 /* bypass transceiver */
1072 #define PNIC_NWAY_LC 0x00000008 /* AUI low current mode */
1073 #define PNIC_NWAY_UV 0x00000010 /* low squelch voltage */
1074 #define PNIC_NWAY_DX 0x00000020 /* disable TP pol. correction */
1075 #define PNIC_NWAY_TW 0x00000040 /* select TP (0 == AUI) */
1076 #define PNIC_NWAY_AF 0x00000080 /* AUI full/half step input
1077  voltage */
1078 #define PNIC_NWAY_FD 0x00000100 /* full duplex mode */
1079 #define PNIC_NWAY_DL 0x00000200 /* disable link integrity
1080  test */
1081 #define PNIC_NWAY_DM 0x00000400 /* disable AUI/TP autodetect */
1082 #define PNIC_NWAY_100 0x00000800 /* 1 == 100mbps, 0 == 10mbps */
1083 #define PNIC_NWAY_NW 0x00001000 /* enable NWay block */
1084 #define PNIC_NWAY_CAP10T 0x00002000 /* adv. 10baseT */
1085 #define PNIC_NWAY_CAP10TFDX 0x00004000 /* adv. 10baseT-FDX */
1086 #define PNIC_NWAY_CAP100TXFDX 0x00008000 /* adv. 100baseTX-FDX */
1087 #define PNIC_NWAY_CAP100TX 0x00010000 /* adv. 100baseTX */
1088 #define PNIC_NWAY_CAP100T4 0x00020000 /* adv. 100base-T4 */
1089 #define PNIC_NWAY_RN 0x02000000 /* re-negotiate enable */
1090 #define PNIC_NWAY_RF 0x04000000 /* remote fault detected */
1091 #define PNIC_NWAY_LPAR10T 0x08000000 /* link part. 10baseT */
1092 #define PNIC_NWAY_LPAR10TFDX 0x10000000 /* link part. 10baseT-FDX */
1093 #define PNIC_NWAY_LPAR100TXFDX 0x20000000 /* link part. 100baseTX-FDX */
1094 #define PNIC_NWAY_LPAR100TX 0x40000000 /* link part. 100baseTX */
1095 #define PNIC_NWAY_LPAR100T4 0x80000000 /* link part. 100base-T4 */
1096 #define PNIC_NWAY_LPAR_MASK 0xf8000000
1097 
1098 
1099 /*
1100  * Macronix 98713, 98713A, 98715, 98715A, 98715AEC, 98725, and
1101  * Lite-On 82C115 registers.
1102  */
1103 
1104  /*
1105  * Note, the MX98713 is very Tulip-like:
1106  *
1107  * CSR12 General Purpose Port (like 21140)
1108  * CSR13 reserved
1109  * CSR14 reserved
1110  * CSR15 Watchdog Timer (like 21140)
1111  *
1112  * The Macronix CSR12, CSR13, CSR14, and CSR15 exist only
1113  * on the MX98713A and higher.
1114  */
1115 
1116 /* CSR12 - 10base-T Status Port (similar to SIASTAT) */
1117  /* See SIASTAT 21142/21143 bits */
1118 #define CSR_PMAC_10TSTAT TULIP_CSR12
1119 #define PMAC_SIASTAT_MASK (SIASTAT_LS100|SIASTAT_LS10| \
1120  SIASTAT_APS|SIASTAT_TRF|SIASTAT_ANS| \
1121  SIASTAT_LPN|SIASTAT_LPC)
1122 
1123 
1124 /* CSR13 - NWAY Reset Register */
1125 #define CSR_PMAC_NWAYRESET TULIP_CSR13
1126  /* See SIACONN 21142/21143 bits */
1127 #define PMAC_SIACONN_MASK (SIACONN_SRL)
1128 #define PMAC_NWAYRESET_100TXRESET 0x00000002 /* 100base PMD reset */
1129 
1130 
1131 /* CSR14 - 10base-T Control Port */
1132 #define CSR_PMAC_10TCTL TULIP_CSR14
1133  /* See SIATXRX 21142/21143 bits */
1134 #define PMAC_SIATXRX_MASK (SIATXRX_LBK|SIATXRX_DREN|SIATXRX_TH| \
1135  SIATXRX_ANE|SIATXRX_RSQ|SIATXRX_LTE| \
1136  SIATXRX_THX|SIATXRX_TXF|SIATXRX_T4)
1137 
1138 
1139 /* CSR15 - Watchdog Timer Register */
1140  /* MX98713: see 21140 CSR15 */
1141  /* others: see SIAGEN 21142/21143 bits */
1142 #define PMAC_SIAGEN_MASK (SIAGEN_JBD|SIAGEN_HUJ|SIAGEN_JCK| \
1143  SIAGEN_RWD|SIAGEN_RWR)
1144 
1145 
1146 /* CSR16 - Test Operation Register (a.k.a. Magic Packet Register) */
1147 #define CSR_PMAC_TOR TULIP_CSR16
1148 #define PMAC_TOR_98713 0x0F370000
1149 #define PMAC_TOR_98715 0x0B3C0000
1150 
1151 
1152 /* CSR20 - NWAY Status */
1153 #define CSR_PMAC_NWAYSTAT TULIP_CSR20
1154  /*
1155  * Note: the MX98715A manual claims that EQTEST and PCITEST
1156  * must be set to 1 by software for normal operation, but
1157  * this does not appear to be necessary. This is probably
1158  * one of the things that frobbing the Test Operation Register
1159  * does.
1160  *
1161  * MX98715AEC uses this register for Auto Compensation.
1162  * CSR20<14> and CSR20<9> are called DS130 and DS120
1163  */
1164 #define PMAC_NWAYSTAT_DS120 0x00000200 /* Auto-compensation circ */
1165 #define PMAC_NWAYSTAT_DS130 0x00004000 /* Auto-compensation circ */
1166 #define PMAC_NWAYSTAT_EQTEST 0x00001000 /* EQ test */
1167 #define PMAC_NWAYSTAT_PCITEST 0x00010000 /* PCI test */
1168 #define PMAC_NWAYSTAT_10TXH 0x08000000 /* 10t accepted */
1169 #define PMAC_NWAYSTAT_10TXF 0x10000000 /* 10t-fdx accepted */
1170 #define PMAC_NWAYSTAT_100TXH 0x20000000 /* 100tx accepted */
1171 #define PMAC_NWAYSTAT_100TXF 0x40000000 /* 100tx-fdx accepted */
1172 #define PMAC_NWAYSTAT_T4 0x80000000 /* 100t4 accepted */
1173 
1174 
1175 /* CSR21 - Flow Control Register */
1176 #define CSR_PNICII_FLOWCTL TULIP_CSR21
1177 #define PNICII_FLOWCTL_WKFCATEN 0x00000010 /* enable wake-up frame
1178  catenation feature */
1179 #define PNICII_FLOWCTL_NFCE 0x00000020 /* accept flow control result
1180  from NWay */
1181 #define PNICII_FLOWCTL_FCTH0 0x00000040 /* rx flow control thresh 0 */
1182 #define PNICII_FLOWCTL_FCTH1 0x00000080 /* rx flow control thresh 1 */
1183 #define PNICII_FLOWCTL_REJECTFC 0x00000100 /* abort rx flow control */
1184 #define PNICII_FLOWCTL_STOPTX 0x00000200 /* tx flow stopped */
1185 #define PNICII_FLOWCTL_RUFCEN 0x00000400 /* send flow control when
1186  RU interrupt occurs */
1187 #define PNICII_FLOWCTL_RXFCEN 0x00000800 /* rx flow control enable */
1188 #define PNICII_FLOWCTL_TXFCEN 0x00001000 /* tx flow control enable */
1189 #define PNICII_FLOWCTL_RESTOP 0x00002000 /* restop mode */
1190 #define PNICII_FLOWCTL_RESTART 0x00004000 /* restart mode */
1191 #define PNICII_FLOWCTL_TEST 0x00008000 /* test flow control timer */
1192 #define PNICII_FLOWCTL_TMVAL 0xffff0000 /* timer value in flow
1193  control frame */
1194 
1195 #define PNICII_FLOWCTL_TH_512 (PNICII_FLOWCTL_FCTH0|PNICII_FLOWCTL_FCTH1)
1196 #define PNICII_FLOWCTL_TH_256 (PNICII_FLOWCTL_FCTH1)
1197 #define PNICII_FLOWCTL_TH_128 (PNICII_FLOWCTL_FCTH0)
1198 #define PNICII_FLOWCTL_TH_OVFLW (0)
1199 
1200 
1201 /* CSR22 - MAC ID Byte 3-0 Register */
1202 #define CSR_PNICII_MACID0 TULIP_CSR22
1203 #define PNICII_MACID_1 0 /* shift */
1204 #define PNICII_MACID_0 8 /* shift */
1205 #define PNICII_MACID_3 16 /* shift */
1206 #define PNICII_MACID_2 24 /* shift */
1207 
1208 
1209 /* CSR23 - Magic ID Byte 5,4/MACID Byte 5,4 Register */
1210 #define PNICII_MACID_5 0 /* shift */
1211 #define PNICII_MACID_4 8 /* shift */
1212 #define PNICII_MAGID_5 16 /* shift */
1213 #define PNICII_MAGIC_4 24 /* shift */
1214 
1215 
1216 /* CSR24 - Magic ID Byte 3-0 Register */
1217 #define PNICII_MAGID_1 0 /* shift */
1218 #define PNICII_MAGID_0 8 /* shift */
1219 #define PNICII_MAGID_3 16 /* shift */
1220 #define PNICII_MAGID_2 24 /* shift */
1221 
1222 
1223 /* CSR25 - CSR28 - Filter Byte Mask Registers */
1224 #define CSR_PNICII_MASK0 TULIP_CSR25
1225 
1226 #define CSR_PNICII_MASK1 TULIP_CSR26
1227 
1228 #define CSR_PNICII_MASK2 TULIP_CSR27
1229 
1230 #define CSR_PNICII_MASK3 TULIP_CSR28
1231 
1232 
1233 /* CSR29 - Filter Offset Register */
1234 #define CSR_PNICII_FILOFF TULIP_CSR29
1235 #define PNICII_FILOFF_PAT0 0x0000007f /* pattern 0 offset */
1236 #define PNICII_FILOFF_EN0 0x00000080 /* enable pattern 0 */
1237 #define PNICII_FILOFF_PAT1 0x00007f00 /* pattern 1 offset */
1238 #define PNICII_FILOFF_EN1 0x00008000 /* enable pattern 1 */
1239 #define PNICII_FILOFF_PAT2 0x007f0000 /* pattern 2 offset */
1240 #define PNICII_FILOFF_EN2 0x00800000 /* enable pattern 2 */
1241 #define PNICII_FILOFF_PAT3 0x7f000000 /* pattern 3 offset */
1242 #define PNICII_FILOFF_EN3 0x80000000 /* enable pattern 3 */
1243 
1244 
1245 /* CSR30 - Filter 1 and 0 CRC-16 Register */
1246 #define CSR_PNICII_FIL01 TULIP_CSR30
1247 #define PNICII_FIL01_CRC0 0x0000ffff /* CRC-16 of pattern 0 */
1248 #define PNICII_FIL01_CRC1 0xffff0000 /* CRC-16 of pattern 1 */
1249 
1250 
1251 /* CSR31 = Filter 3 and 2 CRC-16 Register */
1252 #define CSR_PNICII_FIL23 TULIP_CSR31
1253 #define PNICII_FIL23_CRC2 0x0000ffff /* CRC-16 of pattern 2 */
1254 #define PNICII_FIL23_CRC3 0xffff0000 /* CRC-16 of pattern 3 */
1255 
1256 
1257 /*
1258  * Winbond 89C840F registers.
1259  */
1260 
1261 /* CSR12 - Current Receive Descriptor Register */
1262 #define CSR_WINB_CRDAR TULIP_CSR12
1263 
1264 
1265 /* CSR13 - Current Receive Buffer Register */
1266 #define CSR_WINB_CCRBAR TULIP_CSR13
1267 
1268 
1269 /* CSR14 - Multicast Address Register 0 */
1270 #define CSR_WINB_CMA0 TULIP_CSR14
1271 
1272 
1273 /* CSR15 - Multicast Address Register 1 */
1274 #define CSR_WINB_CMA1 TULIP_CSR15
1275 
1276 
1277 /* CSR16 - Physical Address Register 0 */
1278 #define CSR_WINB_CPA0 TULIP_CSR16
1279 
1280 
1281 /* CSR17 - Physical Address Register 1 */
1282 #define CSR_WINB_CPA1 TULIP_CSR17
1283 
1284 
1285 /* CSR18 - Boot ROM Size Register */
1286 #define CSR_WINB_CBRCR TULIP_CSR18
1287 #define WINB_CBRCR_NONE 0x00000000 /* no boot rom */
1288  /* 0x00000001 also no boot rom */
1289 #define WINB_CBRCR_8K 0x00000002 /* 8k */
1290 #define WINB_CBRCR_16K 0x00000003 /* 16k */
1291 #define WINB_CBRCR_32K 0x00000004 /* 32k */
1292 #define WINB_CBRCR_64K 0x00000005 /* 64k */
1293 #define WINB_CBRCR_128K 0x00000006 /* 128k */
1294 #define WINB_CBRCR_256K 0x00000007
1295 
1296 
1297 /* CSR19 - Current Transmit Descriptor Register */
1298 #define CSR_WINB_CTDAR TULIP_CSR19
1299 
1300 
1301 /* CSR20 - Current Transmit Buffer Register */
1302 #define CSR_WINB_CTBAR TULIP_CSR20
1303 
1304 
1305 /*
1306  * ADMtek AL981 registers
1307  *
1308  * We define these as strict byte offsets into PCI space, since
1309  * not all of them have consistent access rules.
1310  */
1311 
1312 /* CSR13 - Wake-up Control/Status Register */
1313 #define CSR_ADM_WCSR 0x68
1314 #define ADM_WCSR_LSC 0x00000001 /* link status changed */
1315 #define ADM_WCSR_MPR 0x00000002 /* magic packet received */
1316 #define ADM_WCSR_WFR 0x00000004 /* wake up frame received */
1317 #define ADM_WCSR_LSCE 0x00000100 /* link status changed en. */
1318 #define ADM_WCSR_MPRE 0x00000200 /* magic packet receive en. */
1319 #define ADM_WCSR_WFRE 0x00000400 /* wake up frame receive en. */
1320 #define ADM_WCSR_LINKON 0x00010000 /* link-on detect en. */
1321 #define ADM_WCSR_LINKOFF 0x00020000 /* link-off detect en. */
1322 #define ADM_WCSR_WP5E 0x02000000 /* wake up pat. 5 en. */
1323 #define ADM_WCSR_WP4E 0x04000000 /* wake up pat. 4 en. */
1324 #define ADM_WCSR_WP3E 0x08000000 /* wake up pat. 3 en. */
1325 #define ADM_WCSR_WP2E 0x10000000 /* wake up pat. 2 en. */
1326 #define ADM_WCSR_WP1E 0x20000000 /* wake up pat. 1 en. */
1327 #define ADM_WCSR_CRCT 0x40000000 /* CRC-16 type:
1328  0 == 0000 initial
1329  1 == ffff initial */
1330 
1331 
1332 /* CSR14 - Wake-up Pattern Data Register */
1333 #define CSR_ADM_WPDR 0x70
1334 
1335  /*
1336  * 25 consecutive longword writes are issued to WPDR to
1337  * program the wake-up pattern filter. The data written
1338  * is as follows:
1339  *
1340  * XXX
1341  */
1342 
1343 
1344 /* CSR15 - see 21140 CSR15 (Watchdog Timer) */
1345 
1346 
1347 /* CSR16 - Assistant CSR5 (Status Register 2) */
1348 #define CSR_ADM_ASR 0x80
1349  /* 0 - 14: same as CSR5 */
1350 #define ADM_ASR_AAISS 0x00080000 /* added abnormal int. sum. */
1351 #define ADM_ASR_ANISS 0x00010000 /* added normal int. sum. */
1352  /* XXX Receive state */
1353  /* XXX Transmit state */
1354 #define ADM_ASR_BET 0x03800000 /* bus error type */
1355 #define ADM_ASR_BET_PERR 0x00000000 /* parity error */
1356 #define ADM_ASR_BET_MABT 0x00800000 /* master abort */
1357 #define ADM_ASR_BET_TABT 0x01000000 /* target abort */
1358 #define ADM_ASR_PFR 0x04000000 /* PAUSE frame received */
1359 #define ADM_ASR_TDIS 0x10000000 /* transmit def. int. status */
1360 #define ADM_ASR_XIS 0x20000000 /* xcvr int. status */
1361 #define ADM_ASR_REIS 0x40000000 /* receive early int. status */
1362 #define ADM_ASR_TEIS 0x80000000 /* transmit early int. status */
1363 
1364 
1365 /* CSR17 - Assistant CSR7 (Interrupt Enable Register 2) */
1366 #define CSR_ADM_AIE 0x84
1367  /* See CSR16 for valid bits */
1368 
1369 
1370 /* CSR18 - Command Register */
1371 #define CSR_ADM_CR 0x88
1372 #define ADM_CR_ATUR 0x00000001 /* auto. tx underrun recover */
1373 #define ADM_CR_SINT 0x00000002 /* software interrupt */
1374 #define ADM_CR_DRT 0x0000000c /* drain receive threshold */
1375 #define ADM_CR_DRT_8LW 0x00000000 /* 8 longwords */
1376 #define ADM_CR_DRT_16LW 0x00000004 /* 16 longwords */
1377 #define ADM_CR_DRT_SF 0x00000008 /* store-and-forward */
1378 #define ADM_CR_RTE 0x00000010 /* receive threshold enable */
1379 #define ADM_CR_PAUSE 0x00000020 /* enable PAUSE function */
1380 #define ADM_CR_RWP 0x00000040 /* reset wake-up pattern
1381  data register pointer */
1382  /* 16 - 31 are automatically recalled from the EEPROM */
1383 #define ADM_CR_WOL 0x00040000 /* wake-on-lan enable */
1384 #define ADM_CR_PM 0x00080000 /* power management enable */
1385 #define ADM_CR_RFS 0x00600000 /* Receive FIFO size */
1386 #define ADM_CR_RFS_1K 0x00600000 /* 1K FIFO */
1387 #define ADM_CR_RFS_2K 0x00400000 /* 2K FIFO */
1388 #define ADM_CR_LEDMODE 0x00800000 /* LED mode */
1389 #define ADM_CR_AUXCL 0x30000000 /* aux current load */
1390 #define ADM_CR_D3CS 0x80000000 /* D3 cold wake up enable */
1391 
1392 
1393 /* CSR19 - PCI bus performance counter */
1394 #define CSR_ADM_PCIC 0x8c
1395 #define ADM_PCIC_DWCNT 0x000000ff /* double-word count of
1396  last bus-master
1397  transaction */
1398 #define ADM_PCIC_CLKCNT 0xffff0000 /* number of PCI clocks
1399  between read request
1400  and access completed */
1401 
1402 /* CSR20 - Power Management Control/Status Register */
1403 #define CSR_ADM_PMCSR 0x90
1404  /*
1405  * This register is also mapped into the PCI configuration
1406  * space as the PMCSR.
1407  */
1408 
1409 
1410 /* CSR23 - Transmit Burst Count/Time Out Register */
1411 #define CSR_ADM_TXBR 0x9c
1412 #define ADM_TXBR_TTO 0x00000fff /* transmit timeout */
1413 #define ADM_TXBR_TBCNT 0x001f0000 /* transmit burst count */
1414 
1415 
1416 /* CSR24 - Flash ROM Port Register */
1417 #define CSR_ADM_FROM 0xa0
1418 #define ADM_FROM_DATA 0x000000ff /* data to/from Flash */
1419 #define ADM_FROM_ADDR 0x01ffff00 /* Flash address */
1420 #define ADM_FROM_ADDR_SHIFT 8
1421 #define ADM_FROM_WEN 0x04000000 /* write enable */
1422 #define ADM_FROM_REN 0x08000000 /* read enable */
1423 #define ADM_FROM_bra16on 0x80000000 /* pin 87 is brA16, else
1424  pin 87 is fd/col LED pin */
1425 
1426 
1427 /* CSR25 - Physical Address Register 0 */
1428 #define CSR_ADM_PAR0 0xa4
1429 
1430 
1431 /* CSR26 - Physical Address Register 1 */
1432 #define CSR_ADM_PAR1 0xa8
1433 
1434 
1435 /* CSR27 - Multicast Address Register 0 */
1436 #define CSR_ADM_MAR0 0xac
1437 
1438 
1439 /* CSR28 - Multicast Address Register 1 */
1440 #define CSR_ADM_MAR1 0xb0
1441 
1442 
1443 /* Internal PHY registers are mapped here (lower 16 bits valid) */
1444 
1445 #define CSR_ADM_BMCR 0xb4
1446 #define CSR_ADM_BMSR 0xb8
1447 #define CSR_ADM_PHYIDR1 0xbc
1448 #define CSR_ADM_PHYIDR2 0xc0
1449 #define CSR_ADM_ANAR 0xc4
1450 #define CSR_ADM_ANLPAR 0xc8
1451 #define CSR_ADM_ANER 0xcc
1452 
1453 /* XCVR Mode Control Register */
1454 #define CSR_ADM_XMC 0xd0
1455 #define ADM_XMC_LD 0x00000800 /* long distance mode
1456  (low squelch enable) */
1457 
1458 
1459 /* XCVR Configuration Information and Interrupt Status Register */
1460 #define CSR_ADM_XCIIS 0xd4
1461 #define ADM_XCIIS_REF 0x0001 /* 64 error packets received */
1462 #define ADM_XCIIS_ANPR 0x0002 /* autoneg page received */
1463 #define ADM_XCIIS_PDF 0x0004 /* parallel detection fault */
1464 #define ADM_XCIIS_ANAR 0x0008 /* autoneg ACK */
1465 #define ADM_XCIIS_LS 0x0010 /* link status (1 == fail) */
1466 #define ADM_XCIIS_RFD 0x0020 /* remote fault */
1467 #define ADM_XCIIS_ANC 0x0040 /* autoneg completed */
1468 #define ADM_XCIIS_PAUSE 0x0080 /* PAUSE enabled */
1469 #define ADM_XCIIS_DUPLEX 0x0100 /* full duplex */
1470 #define ADM_XCIIS_SPEED 0x0200 /* 100Mb/s */
1471 
1472 
1473 /* XCVR Interrupt Enable Register */
1474 #define CSR_ADM_XIE 0xd8
1475  /* Bits are as for XCIIS */
1476 
1477 
1478 /* XCVR 100baseTX PHY Control/Status Register */
1479 #define CSR_ADM_100CTR 0xdc
1480 #define ADM_100CTR_DISCRM 0x0001 /* disable scrambler */
1481 #define ADM_100CTR_DISMLT 0x0002 /* disable MLT3 ENDEC */
1482 #define ADM_100CTR_CMODE 0x001c /* current operating mode */
1483 #define ADM_100CTR_CMODE_AUTO 0x0000 /* in autoneg */
1484 #define ADM_100CTR_CMODE_10 0x0004 /* 10baseT */
1485 #define ADM_100CTR_CMODE_100 0x0008 /* 100baseTX */
1486  /* 0x000c reserved */
1487  /* 0x0010 reserved */
1488 #define ADM_100CTR_CMODE_10FD 0x0014 /* 10baseT-FDX */
1489 #define ADM_100CTR_CMODE_100FD 0x0018 /* 100baseTX-FDX */
1490 #define ADM_100CTR_CMODE_ISO 0x001c /* isolated */
1491 #define ADM_100CTR_ISOTX 0x0020 /* transmit isolation */
1492 #define ADM_100CTR_ENRZI 0x0080 /* enable NRZ <> NRZI conv. */
1493 #define ADM_100CTR_ENDCR 0x0100 /* enable DC restoration */
1494 #define ADM_100CTR_ENRLB 0x0200 /* enable remote loopback */
1495 #define ADM_100CTR_RXVPP 0x0800 /* peak Rx voltage:
1496  0 == 1.0 VPP
1497  1 == 1.4 VPP */
1498 #define ADM_100CTR_ANC 0x1000 /* autoneg completed */
1499 #define ADM_100CTR_DISRER 0x2000 /* disable Rx error counter */
1500 
1501 /* Operation Mode Register (AN983) */
1502 #define CSR_ADM983_OPMODE 0xfc
1503 #define ADM983_OPMODE_SPEED 0x80000000 /* 1 == 100, 0 == 10 */
1504 #define ADM983_OPMODE_FD 0x40000000 /* 1 == fd, 0 == hd */
1505 #define ADM983_OPMODE_LINK 0x20000000 /* 1 == link, 0 == no link */
1506 #define ADM983_OPMODE_EERLOD 0x04000000 /* reload from EEPROM */
1507 #define ADM983_OPMODE_SingleChip 0x00000007 /* single-chip mode */
1508 #define ADM983_OPMODE_MacOnly 0x00000004 /* MAC-only mode */
1509 
1510 /*
1511  * Xircom X3201-3 registers
1512  */
1513 
1514 /* Power Management Register */
1515 #define CSR_X3201_PMR TULIP_CSR16
1516 #define X3201_PMR_EDINT 0x0000000f /* energy detect interval */
1517 #define X3201_PMR_EDEN 0x00000100 /* energy detect enable */
1518 #define X3201_PMR_MPEN 0x00000200 /* magic packet enable */
1519 #define X3201_PMR_WOLEN 0x00000400 /* Wake On Lan enable */
1520 #define X3201_PMR_PMGP0EN 0x00001000 /* GP0 change enable */
1521 #define X3201_PMR_PMLCEN 0x00002000 /* link change enable */
1522 #define X3201_PMR_WOLTMEN 0x00008000 /* WOL template mem enable */
1523 #define X3201_PMR_EP 0x00010000 /* energy present */
1524 #define X3201_PMR_LP 0x00200000 /* link present */
1525 #define X3201_PMR_EDES 0x01000000 /* ED event status */
1526 #define X3201_PMR_MPES 0x02000000 /* MP event status */
1527 #define X3201_PMR_WOLES 0x04000000 /* WOL event status */
1528 #define X3201_PMR_WOLPS 0x08000000 /* WOL process status */
1529 #define X3201_PMR_GP0ES 0x10000000 /* GP0 event status */
1530 #define X3201_PMR_LCES 0x20000000 /* LC event status */
1531 
1532 /*
1533  * Davicom DM9102 registers.
1534  */
1535 
1536 /* PHY Status Register */
1537 #define CSR_DM_PHYSTAT TULIP_CSR12
1538 #define DM_PHYSTAT_10 0x00000001 /* 10Mb/s */
1539 #define DM_PHYSTAT_100 0x00000002 /* 100Mb/s */
1540 #define DM_PHYSTAT_FDX 0x00000004 /* full-duplex */
1541 #define DM_PHYSTAT_LINK 0x00000008 /* link up */
1542 #define DM_PHYSTAT_RXLOCK 0x00000010 /* RX-lock */
1543 #define DM_PHYSTAT_SIGNAL 0x00000020 /* signal detection */
1544 #define DM_PHYSTAT_UTPSIG 0x00000040 /* UTP SIG */
1545 #define DM_PHYSTAT_GPED 0x00000080 /* general PHY reset control */
1546 #define DM_PHYSTAT_GEPC 0x00000100 /* GPED bits control */
1547 
1548 
1549 /* Sample Frame Access Register */
1550 #define CSR_DM_SFAR TULIP_CSR13
1551 
1552 
1553 /* Sample Frame Data Register */
1554 #define CSR_DM_SFDR TULIP_CSR14
1555  /* See 21143 SIAGEN register */
1556 
1557 /*
1558  * ASIX AX88140A and AX88141 registers.
1559  */
1560 
1561 /* CSR13 - Filtering Index */
1562 #define CSR_AX_FILTIDX TULIP_CSR13
1563 
1564 /* CSR14 - Filtering data */
1565 #define CSR_AX_FILTDATA TULIP_CSR14
1566 
1567 /* Filtering Index values */
1568 #define AX_FILTIDX_PAR0 0x00000000
1569 #define AX_FILTIDX_PAR1 0x00000001
1570 #define AX_FILTIDX_MAR0 0x00000002
1571 #define AX_FILTIDX_MAR1 0x00000003
1572 
1573 #endif /* _DEV_IC_TULIPREG_H_ */
__volatile u_int32_t td_ctl
Definition: tulipreg.h:169
__volatile u_int32_t td_bufaddr1
Definition: tulipreg.h:170
__volatile u_int32_t td_status
Definition: tulipreg.h:168
__volatile u_int32_t td_bufaddr2
Definition: tulipreg.h:171

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